TargetMachine: Use LLVMTargetMachine in CodeGen

[MatzeB]

Summary

While preparing a talk about CodeGen I looked at the TargetMachine/LLVMTargetMachine classes; reading the doxygen comments it seems that the intention is that TargetMachine is a general interface to be used by all targets, while LLVMTargetMachine is a specialization for targets using code from lib/CodeGen.

In practice some methods that were only useful for lib/CodeGen based targets sneaked into TargetMachine anyway. The problem as it turns out is that most of the time we only had a reference to TargetMachine instead of LLVMTargetMachine at hand.

This commit:

• Changes most reference in CodeGen from TargetMachine to LLVMTargetMachine
• Moves some methods from TargetMachine to LLVMTargetMachine: getSubtarget, targetSchedulesPostRAScheduling, usesPhysRegsForPEI, useIPRA
• Add two new methods into TargetMachine for the two cases where non-CodeGen code was directly accessing CodeGen interfaces: useAA(), getTargetLowering()

[chandlerc]

I generally like the direction of the cleanup. A few high level questions:

1. You say that this is to distinguish targets that *do* use LLVM's lib/CodeGen from those that do not. Do you mean entire targets that do not? Or do you mean just *components* of targets that do not depend on it like the target's MC layer?

2. If in #1 you mean actual targets -- are there any left now that the C backend is gone? What are these targets? I wonder if we could simplify things by collapsing a no longer necessary layer.

3. If we can't eliminate the distinction here completely, are there better names than TargetMachine and LLVMTargetMachine that we could give these? I'm guessing a good name will be informed by the answers to the above two questions and the reason we're keeping the distinction in place.

4. Any ideas how we could improve comments (or the design) to avoid regressing this (again) in the future?

[echristo]

Hi Matthias,

Similar to Chandler's comments I think we should look at folding these two together rather than keeping them split apart. I started working a little bit in this direction at one point, but admittedly got distracted by other things. A more concrete thought here is that we could either move all of the bits over into the TargetMachine and for something that doesn't need it then that target could simply just not initialize or define those initialization routines (I don't recall anything that doesn't currently need). It might end up being a bit more verbose in a couple of targets, but seems like a reasonable start.

Thoughts?

-eric

[MatzeB]

In D38482#886520, @chandlerc wrote:

I generally like the direction of the cleanup. A few high level questions:

1. You say that this is to distinguish targets that *do* use LLVM's lib/CodeGen from those that do not. Do you mean entire targets that do not? Or do you mean just *components* of targets that do not depend on it like the target's MC layer?

Yes I mean entire targets.

2. If in #1 you mean actual targets -- are there any left now that the C backend is gone? What are these targets? I wonder if we could simplify things by collapsing a no longer necessary layer.

• There is none in open source, and I don't know of any internal ones at my company.
• According to the mailing list this may be good for SPIR-V (http://lists.llvm.org/pipermail/llvm-dev/2017-June/114593.html) which doesn't really need any of the CodeGen infrastructure.
• Indeed collapsing the two classes would slightly simplify the code, and I'd be perfectly fine with that.
• On the other hand it's kinda neat to have a CodeGen internal interface with LLVMTargetMachine and an outside interface with TargetMachine

3. If we can't eliminate the distinction here completely, are there better names than TargetMachine and LLVMTargetMachine that we could give these? I'm guessing a good name will be informed by the answers to the above two questions and the reason we're keeping the distinction in place.

I guess CodeGenTarget instead of LLVMTarget would be in line with this being for lib/CodeGen.

4. Any ideas how we could improve comments (or the design) to avoid regressing this (again) in the future?

I think if we think about this as CodeGen internal and external interfaces or if people actually start using it for SPIR-V it may be fine... But again if you rather feel to merge the two and get rid of the distinction that's fine with me too.

[MatzeB]

In D38482#886603, @echristo wrote:

Hi Matthias,

Similar to Chandler's comments I think we should look at folding these two together rather than keeping them split apart. I started working a little bit in this direction at one point, but admittedly got distracted by other things. A more concrete thought here is that we could either move all of the bits over into the TargetMachine and for something that doesn't need it then that target could simply just not initialize or define those initialization routines (I don't recall anything that doesn't currently need). It might end up being a bit more verbose in a couple of targets, but seems like a reasonable start.

Thoughts?

See my response to Chandler. Right now it feels neat to have an internal/external interface. But that's probably because I spent the time preparing the patch :) Merging the two together to have one less concept/class doesn't sound too bad either (and needs less changes). Let me sleep over it.

[MatzeB]

And for what it's worth for some of the methods I moved around here:

• usesPhysRegsForPEI() this one should be possible to eliminate with some refactoring where we factor out register scavenging into a separate pass from PEI. (That's somewhere on my TODO list not very high up though).
• useIPRA() this one could just as well be a know in TargetPassConfig.

[chandlerc]

In D38482#886613, @MatzeB wrote:

In D38482#886520, @chandlerc wrote:

2. If in #1 you mean actual targets -- are there any left now that the C backend is gone? What are these targets? I wonder if we could simplify things by collapsing a no longer necessary layer.

• There is none in open source, and I don't know of any internal ones at my company.
• According to the mailing list this may be good for SPIR-V (http://lists.llvm.org/pipermail/llvm-dev/2017-June/114593.html) which doesn't really need any of the CodeGen infrastructure.
• Indeed collapsing the two classes would slightly simplify the code, and I'd be perfectly fine with that.
• On the other hand it's kinda neat to have a CodeGen internal interface with LLVMTargetMachine and an outside interface with TargetMachine

I think we should probably just merge these.

My understanding is that the consensus from the entire community was that SPIR-V really should be leveraging the same common legalization infrastructure as the rest of the targets. Notably, other highly abstract targets like WebAssembly seem to be succeeding with that model.

If we want to introduce a target that doesn't share the core LLVM code generation layer, I'm actually still open to that, but I don't think we should maintain unnecessary abstractions waiting for that day to arrive. I think that sets up the right incentives: if we're going to go down the path of splitting out interfaces in this way, that comes with a cost and we should evaluate that cost against the benefit it provides to those actual use cases. Otherwise it seems too easy to endlessly invent arguments on one side or the other because they are all hypothetical.

But this is always a judgement call, so of course I'm interested in where others see this. It seems like Eric is largely agreeing. Quentin? Craig? Hal? Others?

[hfinkel]

In D38482#886622, @chandlerc wrote:

In D38482#886613, @MatzeB wrote:

In D38482#886520, @chandlerc wrote:

2. If in #1 you mean actual targets -- are there any left now that the C backend is gone? What are these targets? I wonder if we could simplify things by collapsing a no longer necessary layer.

• There is none in open source, and I don't know of any internal ones at my company.
• According to the mailing list this may be good for SPIR-V (http://lists.llvm.org/pipermail/llvm-dev/2017-June/114593.html) which doesn't really need any of the CodeGen infrastructure.
• Indeed collapsing the two classes would slightly simplify the code, and I'd be perfectly fine with that.
• On the other hand it's kinda neat to have a CodeGen internal interface with LLVMTargetMachine and an outside interface with TargetMachine

I think we should probably just merge these.

My understanding is that the consensus from the entire community was that SPIR-V really should be leveraging the same common legalization infrastructure as the rest of the targets. Notably, other highly abstract targets like WebAssembly seem to be succeeding with that model.

If we want to introduce a target that doesn't share the core LLVM code generation layer, I'm actually still open to that, but I don't think we should maintain unnecessary abstractions waiting for that day to arrive. I think that sets up the right incentives: if we're going to go down the path of splitting out interfaces in this way, that comes with a cost and we should evaluate that cost against the benefit it provides to those actual use cases. Otherwise it seems too easy to endlessly invent arguments on one side or the other because they are all hypothetical.

But this is always a judgement call, so of course I'm interested in where others see this. It seems like Eric is largely agreeing. Quentin? Craig? Hal? Others?

I think we should ask about this on llvm-dev. Are there other out-of-tree targets where it's still useful to have direct lowering of the IR? Does Emscripten use this? We might check with the folks from Intel/Xilinx re: their FPGA backends. Another aspect of this is that the motivation for doing this may be going away: You used to need to do this in order to get lowering without legalization (or, perhaps register allocation). We now have virtual-register-only backends. With Global ISel, can we get lowering without legalization at all?

[MatzeB]

Merging the two isn't too hard either: D38489

[qcolombet]

I think we should probably just merge these.

Agreed.

include/llvm/CodeGen/Analysis.h

 #include "llvm/Support/CodeGen.h"
 
 namespace llvm {
 class GlobalValue;
 class MachineBasicBlock;
 class MachineFunction;
 class TargetLoweringBase;
 class TargetLowering;
-class TargetMachine;
+class LLVMTargetMachine;
 class SDNode;
 class SDValue;
 class SelectionDAG;
 struct EVT;
 
 /// \brief Compute the linearized index of a member in a nested
 /// aggregate/struct/array.
 ///

 ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred);
 
 /// Test if the given instruction is in a position to be optimized
 /// with a tail-call. This roughly means that it's in a block with
 /// a return and there's nothing that needs to be scheduled
 /// between it and the return.
 ///
 /// This function only tests target-independent requirements.
-bool isInTailCallPosition(ImmutableCallSite CS, const TargetMachine &TM);
+bool isInTailCallPosition(ImmutableCallSite CS, const LLVMTargetMachine &TM);
 
 /// Test if given that the input instruction is in the tail call position, if
 /// there is an attribute mismatch between the caller and the callee that will
 /// inhibit tail call optimizations.
 /// \p AllowDifferingSizes is an output parameter which, if forming a tail call
 /// is permitted, determines whether it's permitted only if the size of the
 /// caller's and callee's return types match exactly.
 bool attributesPermitTailCall(const Function *F, const Instruction *I,

include/llvm/CodeGen/AsmPrinter.h

 #include "llvm/ADT/StringRef.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/CodeGen/DwarfStringPoolEntry.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/IR/InlineAsm.h"
 #include "llvm/IR/LLVMContext.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/SourceMgr.h"
+#include "llvm/Support/TargetRegistry.h"
+#include "llvm/Target/TargetMachine.h"
 #include <cstdint>
 #include <memory>
 #include <utility>
 #include <vector>
 
 namespace llvm {
 
 class AsmPrinterHandler;
 class BasicBlock;
 class BlockAddress;
 class Constant;
 class ConstantArray;
 class DataLayout;
 class DIE;
 class DIEAbbrev;
 class DwarfDebug;
 class GCMetadataPrinter;
 class GlobalIndirectSymbol;
 class GlobalObject;
+class GCStrategy;
 class GlobalValue;
 class GlobalVariable;
-class GCStrategy;
+class LLVMTargetMachine;
 class MachineBasicBlock;
 class MachineConstantPoolValue;
 class MachineFunction;
 class MachineInstr;
 class MachineJumpTableInfo;
 class MachineLoopInfo;
 class MachineModuleInfo;
 class MachineOptimizationRemarkEmitter;
 class MCAsmInfo;
 class MCCFIInstruction;
 class MCContext;
 class MCExpr;
 class MCInst;
 class MCSection;
 class MCStreamer;
 class MCSubtargetInfo;
 class MCSymbol;
 class MCTargetOptions;
 class MDNode;
 class Module;
 class raw_ostream;
 class TargetLoweringObjectFile;
-class TargetMachine;
 
 /// This class is intended to be used as a driving class for all asm writers.
 class AsmPrinter : public MachineFunctionPass {
 public:
   /// Target machine description.
   ///
-  TargetMachine &TM;
+  LLVMTargetMachine &TM;
 
   /// Target Asm Printer information.
   ///
   const MCAsmInfo *MAI;
 
   /// This is the context for the output file that we are streaming. This owns
   /// all of the global MC-related objects for the generated translation unit.
   MCContext &OutContext;
private:
 
   /// If the target supports dwarf debug info, this pointer is non-null.
   DwarfDebug *DD = nullptr;
 
   /// If the current module uses dwarf CFI annotations strictly for debugging.
   bool isCFIMoveForDebugging = false;
 
 protected:
-  explicit AsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer);
+  explicit AsmPrinter(LLVMTargetMachine &TM,
+                      std::unique_ptr<MCStreamer> Streamer);
 
 public:
   ~AsmPrinter() override;
 
   DwarfDebug *getDwarfDebug() { return DD; }
   DwarfDebug *getDwarfDebug() const { return DD; }
 
   uint16_t getDwarfVersion() const;
public:
   MCSymbol *getCurExceptionSym();
 
   /// Return information about object file lowering.
   const TargetLoweringObjectFile &getObjFileLowering() const;
 
   /// Return information about data layout.
   const DataLayout &getDataLayout() const;
 
-  /// Return the pointer size from the TargetMachine
+  /// Return the pointer size from the LLVMTargetMachine
   unsigned getPointerSize() const;
 
   /// Return information about subtarget.
   const MCSubtargetInfo &getSubtargetInfo() const;
 
   void EmitToStreamer(MCStreamer &S, const MCInst &Inst);
 
   /// Return the current section we are emitting to.
private:
   void EmitXXStructorList(const DataLayout &DL, const Constant *List,
                           bool isCtor);
   GCMetadataPrinter *GetOrCreateGCPrinter(GCStrategy &C);
   /// Emit GlobalAlias or GlobalIFunc.
   void emitGlobalIndirectSymbol(Module &M,
                                 const GlobalIndirectSymbol& GIS);
 };
 
+/// Helper template for registering a target specific assembly printer, for use
+/// in the target machine initialization function. Usage:
+///
+/// extern "C" void LLVMInitializeFooAsmPrinter() {
+///   extern Target TheFooTarget;
+///   RegisterAsmPrinter<FooAsmPrinter> X(TheFooTarget);
+/// }
+template <class AsmPrinterImpl> struct RegisterAsmPrinter {
+  RegisterAsmPrinter(Target &T) {
+    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
+  }
+
+private:
+  static AsmPrinter *Allocator(TargetMachine &TM,
+                               std::unique_ptr<MCStreamer> &&Streamer) {
+    LLVMTargetMachine &LLVMTM = static_cast<LLVMTargetMachine&>(TM);
+    return new AsmPrinterImpl(LLVMTM, std::move(Streamer));
+  }
+};
+
 } // end namespace llvm
 
 #endif // LLVM_CODEGEN_ASMPRINTER_H

include/llvm/CodeGen/BasicTTIImpl.h

 #include "llvm/Analysis/TargetLibraryInfo.h"
 #include "llvm/Analysis/TargetTransformInfoImpl.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Target/TargetLowering.h"
 #include "llvm/Target/TargetSubtargetInfo.h"
 
 namespace llvm {
 
+class LLVMTargetMachine;
+
 extern cl::opt<unsigned> PartialUnrollingThreshold;
 
 /// \brief Base class which can be used to help build a TTI implementation.
 ///
 /// This class provides as much implementation of the TTI interface as is
 /// possible using the target independent parts of the code generator.
 ///
 /// In order to subclass it, your class must implement a getST() method to
private:
   }
 
   /// \brief Local query method delegates up to T which *must* implement this!
   const TargetLoweringBase *getTLI() const {
     return static_cast<const T *>(this)->getTLI();
   }
 
 protected:
-  explicit BasicTTIImplBase(const TargetMachine *TM, const DataLayout &DL)
+  explicit BasicTTIImplBase(const LLVMTargetMachine *TM, const DataLayout &DL)
       : BaseT(DL) {}
 
   using TargetTransformInfoImplBase::DL;
 
 public:
   /// \name Scalar TTI Implementations
   /// @{
   bool allowsMisalignedMemoryAccesses(LLVMContext &Context,
class BasicTTIImpl : public BasicTTIImplBase<BasicTTIImpl> {
 
   const TargetSubtargetInfo *ST;
   const TargetLoweringBase *TLI;
 
   const TargetSubtargetInfo *getST() const { return ST; }
   const TargetLoweringBase *getTLI() const { return TLI; }
 
 public:
-  explicit BasicTTIImpl(const TargetMachine *ST, const Function &F);
+  explicit BasicTTIImpl(const LLVMTargetMachine *ST, const Function &F);
 };
 
 }
 
 #endif

include/llvm/CodeGen/FastISel.h

 
 class AllocaInst;
 class BasicBlock;
 class CallInst;
 class Constant;
 class ConstantFP;
 class DataLayout;
 class FunctionLoweringInfo;
+class LLVMTargetMachine;
 class LoadInst;
 class MachineConstantPool;
 class MachineFrameInfo;
 class MachineFunction;
 class MachineInstr;
 class MachineMemOperand;
 class MachineOperand;
 class MachineRegisterInfo;
 class MCContext;
 class MCInstrDesc;
 class MCSymbol;
 class TargetInstrInfo;
 class TargetLibraryInfo;
-class TargetMachine;
 class TargetRegisterClass;
 class TargetRegisterInfo;
 class Type;
 class User;
 class Value;
 
 /// \brief This is a fast-path instruction selection class that generates poor
 /// code and doesn't support illegal types or non-trivial lowering, but runs

 protected:
   DenseMap<const Value *, unsigned> LocalValueMap;
   FunctionLoweringInfo &FuncInfo;
   MachineFunction *MF;
   MachineRegisterInfo &MRI;
   MachineFrameInfo &MFI;
   MachineConstantPool &MCP;
   DebugLoc DbgLoc;
-  const TargetMachine &TM;
+  const LLVMTargetMachine &TM;
   const DataLayout &DL;
   const TargetInstrInfo &TII;
   const TargetLowering &TLI;
   const TargetRegisterInfo &TRI;
   const TargetLibraryInfo *LibInfo;
   bool SkipTargetIndependentISel;
 
   /// \brief The position of the last instruction for materializing constants

include/llvm/CodeGen/MachineFunction.h

 class BasicBlock;
 class BlockAddress;
 class DataLayout;
 class DIExpression;
 class DILocalVariable;
 class DILocation;
 class Function;
 class GlobalValue;
+class LLVMTargetMachine;
 class MachineConstantPool;
 class MachineFrameInfo;
 class MachineFunction;
 class MachineJumpTableInfo;
 class MachineModuleInfo;
 class MachineRegisterInfo;
 class MCContext;
 class MCInstrDesc;
 class Pass;
 class PseudoSourceValueManager;
 class raw_ostream;
 class SlotIndexes;
-class TargetMachine;
 class TargetRegisterClass;
 class TargetSubtargetInfo;
 struct WinEHFuncInfo;
 
 template <> struct ilist_alloc_traits<MachineBasicBlock> {
   void deleteNode(MachineBasicBlock *MBB);
 };
 
struct LandingPadInfo {
   std::vector<int> TypeIds;                // List of type ids (filters negative).
 
   explicit LandingPadInfo(MachineBasicBlock *MBB)
       : LandingPadBlock(MBB) {}
 };
 
 class MachineFunction {
   const Function *Fn;
-  const TargetMachine &Target;
+  const LLVMTargetMachine &Target;
   const TargetSubtargetInfo *STI;
   MCContext &Ctx;
   MachineModuleInfo &MMI;
 
   // RegInfo - Information about each register in use in the function.
   MachineRegisterInfo *RegInfo;
 
   // Used to keep track of target-specific per-machine function information for
struct VariableDbgInfo {
 
     VariableDbgInfo(const DILocalVariable *Var, const DIExpression *Expr,
                     unsigned Slot, const DILocation *Loc)
         : Var(Var), Expr(Expr), Slot(Slot), Loc(Loc) {}
   };
   using VariableDbgInfoMapTy = SmallVector<VariableDbgInfo, 4>;
   VariableDbgInfoMapTy VariableDbgInfos;
 
-  MachineFunction(const Function *Fn, const TargetMachine &TM,
+  MachineFunction(const Function *Fn, const LLVMTargetMachine &TM,
                   unsigned FunctionNum, MachineModuleInfo &MMI);
   MachineFunction(const MachineFunction &) = delete;
   MachineFunction &operator=(const MachineFunction &) = delete;
   ~MachineFunction();
 
   /// Reset the instance as if it was just created.
   void reset() {
     clear();
public:
 
   /// getName - Return the name of the corresponding LLVM function.
   StringRef getName() const;
 
   /// getFunctionNumber - Return a unique ID for the current function.
   unsigned getFunctionNumber() const { return FunctionNumber; }
 
   /// getTarget - Return the target machine this machine code is compiled with
-  const TargetMachine &getTarget() const { return Target; }
+  const LLVMTargetMachine &getTarget() const { return Target; }
 
   /// getSubtarget - Return the subtarget for which this machine code is being
   /// compiled.
   const TargetSubtargetInfo &getSubtarget() const { return *STI; }
   void setSubtarget(const TargetSubtargetInfo *ST) { STI = ST; }
 
   /// getSubtarget - This method returns a pointer to the specified type of
   /// TargetSubtargetInfo.  In debug builds, it verifies that the object being

include/llvm/CodeGen/MachineModuleInfo.h

 #include <utility>
 #include <vector>
 
 namespace llvm {
 
 class BasicBlock;
 class CallInst;
 class Function;
-class MachineFunction;
+class LLVMTargetMachine;
 class MMIAddrLabelMap;
+class MachineFunction;
 class Module;
-class TargetMachine;
 
 //===----------------------------------------------------------------------===//
 /// This class can be derived from and used by targets to hold private
 /// target-specific information for each Module.  Objects of type are
 /// accessed/created with MMI::getInfo and destroyed when the MachineModuleInfo
 /// is destroyed.
 ///
 class MachineModuleInfoImpl {

 };
 
 //===----------------------------------------------------------------------===//
 /// This class contains meta information specific to a module.  Queries can be
 /// made by different debugging and exception handling schemes and reformated
 /// for specific use.
 ///
 class MachineModuleInfo : public ImmutablePass {
-  const TargetMachine &TM;
+  const LLVMTargetMachine &TM;
 
   /// This is the MCContext used for the entire code generator.
   MCContext Context;
 
   /// This is the LLVM Module being worked on.
   const Module *TheModule;
 
   /// This is the object-file-format-specific implementation of
class MachineModuleInfo : public ImmutablePass {
   /// Next unique number available for a MachineFunction.
   unsigned NextFnNum = 0;
   const Function *LastRequest = nullptr; ///< Used for shortcut/cache.
   MachineFunction *LastResult = nullptr; ///< Used for shortcut/cache.
 
 public:
   static char ID; // Pass identification, replacement for typeid
 
-  explicit MachineModuleInfo(const TargetMachine *TM = nullptr);
+  explicit MachineModuleInfo(const LLVMTargetMachine *TM = nullptr);
   ~MachineModuleInfo() override;
 
   // Initialization and Finalization
   bool doInitialization(Module &) override;
   bool doFinalization(Module &) override;
 
   const MCContext &getContext() const { return Context; }
   MCContext &getContext() { return Context; }

include/llvm/CodeGen/RegisterUsageInfo.h

 #include "llvm/ADT/DenseMap.h"
 #include "llvm/Pass.h"
 #include <cstdint>
 #include <vector>
 
 namespace llvm {
 
 class Function;
-class TargetMachine;
+class LLVMTargetMachine;
 
 class PhysicalRegisterUsageInfo : public ImmutablePass {
   virtual void anchor();
 
 public:
   static char ID;
 
   PhysicalRegisterUsageInfo() : ImmutablePass(ID) {
     PassRegistry &Registry = *PassRegistry::getPassRegistry();
     initializePhysicalRegisterUsageInfoPass(Registry);
   }
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesAll();
   }
 
-  /// To set TargetMachine *, which is used to print
+  /// To set LLVMTargetMachine *, which is used to print
   /// analysis when command line option -print-regusage is used.
-  void setTargetMachine(const TargetMachine *TM_) { TM = TM_; }
+  void setTargetMachine(const LLVMTargetMachine *TM_) { TM = TM_; }
 
   bool doInitialization(Module &M) override;
 
   bool doFinalization(Module &M) override;
 
   /// To store RegMask for given Function *.
   void storeUpdateRegUsageInfo(const Function *FP,
                                std::vector<uint32_t> RegMask);
 
   /// To query stored RegMask for given Function *, it will return nullptr if
   /// function is not known.
   const std::vector<uint32_t> *getRegUsageInfo(const Function *FP);
 
   void print(raw_ostream &OS, const Module *M = nullptr) const override;
 
 private:
   /// A Dense map from Function * to RegMask.
   /// In RegMask 0 means register used (clobbered) by function.
   /// and 1 means content of register will be preserved around function call.
   DenseMap<const Function *, std::vector<uint32_t>> RegMasks;
 
-  const TargetMachine *TM;
+  const LLVMTargetMachine *TM;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_CODEGEN_PHYSICALREGISTERUSAGEINFO_H

include/llvm/CodeGen/SelectionDAG.h

 class Constant;
 class ConstantFP;
 class ConstantInt;
 class DataLayout;
 struct fltSemantics;
 class GlobalValue;
 struct KnownBits;
 class LLVMContext;
+class LLVMTargetMachine;
 class MachineBasicBlock;
 class MachineConstantPoolValue;
 class MCSymbol;
 class OptimizationRemarkEmitter;
 class SDDbgValue;
 class SelectionDAG;
 class SelectionDAGTargetInfo;
 class TargetLowering;
-class TargetMachine;
 class TargetSubtargetInfo;
 class Value;
 
 class SDVTListNode : public FoldingSetNode {
   friend struct FoldingSetTrait<SDVTListNode>;
 
   /// A reference to an Interned FoldingSetNodeID for this node.
   /// The Allocator in SelectionDAG holds the data.

 /// and code simplifications.
 ///
 /// The representation used by the SelectionDAG is a target-independent
 /// representation, which has some similarities to the GCC RTL representation,
 /// but is significantly more simple, powerful, and is a graph form instead of a
 /// linear form.
 ///
 class SelectionDAG {
-  const TargetMachine &TM;
+  const LLVMTargetMachine &TM;
   const SelectionDAGTargetInfo *TSI = nullptr;
   const TargetLowering *TLI = nullptr;
   MachineFunction *MF;
   Pass *SDAGISelPass = nullptr;
   LLVMContext *Context;
   CodeGenOpt::Level OptLevel;
 
   /// The function-level optimization remark emitter.  Used to emit remarks
void removeOperands(SDNode *Node) {
     OperandRecycler.deallocate(
         ArrayRecycler<SDUse>::Capacity::get(Node->NumOperands),
         Node->OperandList);
     Node->NumOperands = 0;
     Node->OperandList = nullptr;
   }
 
 public:
-  explicit SelectionDAG(const TargetMachine &TM, CodeGenOpt::Level);
+  explicit SelectionDAG(const LLVMTargetMachine &TM, CodeGenOpt::Level);
   SelectionDAG(const SelectionDAG &) = delete;
   SelectionDAG &operator=(const SelectionDAG &) = delete;
   ~SelectionDAG();
 
   /// Prepare this SelectionDAG to process code in the given MachineFunction.
   void init(MachineFunction &NewMF, OptimizationRemarkEmitter &NewORE,
             Pass *PassPtr);
 
   /// Clear state and free memory necessary to make this
   /// SelectionDAG ready to process a new block.
   void clear();
 
   MachineFunction &getMachineFunction() const { return *MF; }
   const Pass *getPass() const { return SDAGISelPass; }
 
   const DataLayout &getDataLayout() const { return MF->getDataLayout(); }
-  const TargetMachine &getTarget() const { return TM; }
+  const LLVMTargetMachine &getTarget() const { return TM; }
   const TargetSubtargetInfo &getSubtarget() const { return MF->getSubtarget(); }
   const TargetLowering &getTargetLoweringInfo() const { return *TLI; }
   const SelectionDAGTargetInfo &getSelectionDAGInfo() const { return *TSI; }
   LLVMContext *getContext() const {return Context; }
   OptimizationRemarkEmitter &getORE() const { return *ORE; }
 
   /// Pop up a GraphViz/gv window with the DAG rendered using 'dot'.
   void viewGraph(const std::string &Title);

include/llvm/CodeGen/SelectionDAGISel.h

namespace llvm {
   class GCFunctionInfo;
   class ScheduleDAGSDNodes;
   class LoadInst;
 
 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
 /// pattern-matching instruction selectors.
 class SelectionDAGISel : public MachineFunctionPass {
 public:
-  TargetMachine &TM;
+  LLVMTargetMachine &TM;
   const TargetLibraryInfo *LibInfo;
   FunctionLoweringInfo *FuncInfo;
   MachineFunction *MF;
   MachineRegisterInfo *RegInfo;
   SelectionDAG *CurDAG;
   SelectionDAGBuilder *SDB;
   AliasAnalysis *AA;
   GCFunctionInfo *GFI;
   CodeGenOpt::Level OptLevel;
   const TargetInstrInfo *TII;
   const TargetLowering *TLI;
   bool FastISelFailed;
   SmallPtrSet<const Instruction *, 4> ElidedArgCopyInstrs;
 
   /// Current optimization remark emitter.
   /// Used to report things like combines and FastISel failures.
   std::unique_ptr<OptimizationRemarkEmitter> ORE;
 
   static char ID;
 
-  explicit SelectionDAGISel(TargetMachine &tm,
+  explicit SelectionDAGISel(LLVMTargetMachine &tm,
                             CodeGenOpt::Level OL = CodeGenOpt::Default);
   ~SelectionDAGISel() override;
 
   const TargetLowering *getTargetLowering() const { return TLI; }
 
   void getAnalysisUsage(AnalysisUsage &AU) const override;
 
   bool runOnMachineFunction(MachineFunction &MF) override;

include/llvm/CodeGen/StackProtector.h

 #include "llvm/Pass.h"
 
 namespace llvm {
 
 class BasicBlock;
 class DominatorTree;
 class Function;
 class Instruction;
+class LLVMTargetMachine;
 class Module;
 class TargetLoweringBase;
-class TargetMachine;
 class Type;
 
 class StackProtector : public FunctionPass {
 public:
   /// SSPLayoutKind.  Stack Smashing Protection (SSP) rules require that
   /// vulnerable stack allocations are located close the stack protector.
   enum SSPLayoutKind {
     SSPLK_None,       ///< Did not trigger a stack protector.  No effect on data
                       ///< layout.
     SSPLK_LargeArray, ///< Array or nested array >= SSP-buffer-size.  Closest
                       ///< to the stack protector.
     SSPLK_SmallArray, ///< Array or nested array < SSP-buffer-size. 2nd closest
                       ///< to the stack protector.
     SSPLK_AddrOf      ///< The address of this allocation is exposed and
                       ///< triggered protection.  3rd closest to the protector.
   };
 
   /// A mapping of AllocaInsts to their required SSP layout.
   using SSPLayoutMap = ValueMap<const AllocaInst *, SSPLayoutKind>;
 
 private:
-  const TargetMachine *TM = nullptr;
+  const LLVMTargetMachine *TM = nullptr;
 
   /// TLI - Keep a pointer of a TargetLowering to consult for determining
   /// target type sizes.
   const TargetLoweringBase *TLI = nullptr;
   Triple Trip;
 
   Function *F;
   Module *M;

include/llvm/Support/TargetRegistry.h

 #include <cstddef>
 #include <iterator>
 #include <memory>
 #include <string>
 
 namespace llvm {
 
 class AsmPrinter;
+class LLVMTargetMachine;
 class MCAsmBackend;
 class MCAsmInfo;
 class MCAsmParser;
 class MCCodeEmitter;
 class MCContext;
 class MCDisassembler;
 class MCInstPrinter;
 class MCInstrAnalysis;

 private:
   static MCTargetAsmParser *Allocator(const MCSubtargetInfo &STI,
                                       MCAsmParser &P, const MCInstrInfo &MII,
                                       const MCTargetOptions &Options) {
     return new MCAsmParserImpl(STI, P, MII, Options);
   }
 };
 
-/// RegisterAsmPrinter - Helper template for registering a target specific
-/// assembly printer, for use in the target machine initialization
-/// function. Usage:
-///
-/// extern "C" void LLVMInitializeFooAsmPrinter() {
-///   extern Target TheFooTarget;
-///   RegisterAsmPrinter<FooAsmPrinter> X(TheFooTarget);
-/// }
-template <class AsmPrinterImpl> struct RegisterAsmPrinter {
-  RegisterAsmPrinter(Target &T) {
-    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
-  }
-
-private:
-  static AsmPrinter *Allocator(TargetMachine &TM,
-                               std::unique_ptr<MCStreamer> &&Streamer) {
-    return new AsmPrinterImpl(TM, std::move(Streamer));
-  }
-};
-
 /// RegisterMCCodeEmitter - Helper template for registering a target specific
 /// machine code emitter, for use in the target initialization
 /// function. Usage:
 ///
 /// extern "C" void LLVMInitializeFooMCCodeEmitter() {
 ///   extern Target TheFooTarget;
 ///   RegisterMCCodeEmitter<FooCodeEmitter> X(TheFooTarget);
 /// }

include/llvm/Target/TargetLowering.h

case ZeroOrOneBooleanContent:
       return ISD::ZERO_EXTEND;
     case ZeroOrNegativeOneBooleanContent:
       // Extend by copying the sign bit.
       return ISD::SIGN_EXTEND;
     }
     llvm_unreachable("Invalid content kind");
   }
 
-  /// NOTE: The TargetMachine owns TLOF.
-  explicit TargetLoweringBase(const TargetMachine &TM);
+  /// NOTE: The LLVMTargetMachine owns TLOF.
+  explicit TargetLoweringBase(const LLVMTargetMachine &TM);
   TargetLoweringBase(const TargetLoweringBase &) = delete;
   TargetLoweringBase &operator=(const TargetLoweringBase &) = delete;
   virtual ~TargetLoweringBase() = default;
 
 protected:
   /// \brief Initialize all of the actions to default values.
   void initActions();
 
 public:
-  const TargetMachine &getTargetMachine() const { return TM; }
+  const LLVMTargetMachine &getTargetMachine() const { return TM; }
 
   virtual bool useSoftFloat() const { return false; }
 
   /// Return the pointer type for the given address space, defaults to
   /// the pointer type from the data layout.
   /// FIXME: The default needs to be removed once all the code is updated.
   MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const {
     return MVT::getIntegerVT(DL.getPointerSizeInBits(AS));
public:
 
   /// Execute target specific actions to finalize target lowering.
   /// This is used to set extra flags in MachineFrameInformation and freezing
   /// the set of reserved registers.
   /// The default implementation just freezes the set of reserved registers.
   virtual void finalizeLowering(MachineFunction &MF) const;
 
 private:
-  const TargetMachine &TM;
+  const LLVMTargetMachine &TM;
 
   /// Tells the code generator that the target has multiple (allocatable)
   /// condition registers that can be used to store the results of comparisons
   /// for use by selects and conditional branches. With multiple condition
   /// registers, the code generator will not aggressively sink comparisons into
   /// the blocks of their users.
   bool HasMultipleConditionRegisters;
 

 /// target-specific constructs to SelectionDAG operators.
 class TargetLowering : public TargetLoweringBase {
 public:
   struct DAGCombinerInfo;
 
   TargetLowering(const TargetLowering &) = delete;
   TargetLowering &operator=(const TargetLowering &) = delete;
 
-  /// NOTE: The TargetMachine owns TLOF.
-  explicit TargetLowering(const TargetMachine &TM);
+  /// NOTE: The LLVMTargetMachine owns TLOF.
+  explicit TargetLowering(const LLVMTargetMachine &TM);
 
   bool isPositionIndependent() const;
 
   /// Returns true by value, base pointer and offset pointer and addressing mode
   /// by reference if the node's address can be legally represented as
   /// pre-indexed load / store address.
   virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
                                          SDValue &/*Offset*/,

include/llvm/Target/TargetMachine.h

 class MCRegisterInfo;
 class MCSubtargetInfo;
 class MCSymbol;
 class raw_pwrite_stream;
 class PassManagerBuilder;
 class Target;
 class TargetIntrinsicInfo;
 class TargetIRAnalysis;
+class TargetLowering;
 class TargetLoweringObjectFile;
 class TargetPassConfig;
 class TargetSubtargetInfo;
 
 // The old pass manager infrastructure is hidden in a legacy namespace now.
 namespace legacy {
 class PassManagerBase;
 }
public:
   virtual ~TargetMachine();
 
   const Target &getTarget() const { return TheTarget; }
 
   const Triple &getTargetTriple() const { return TargetTriple; }
   StringRef getTargetCPU() const { return TargetCPU; }
   StringRef getTargetFeatureString() const { return TargetFS; }
 
-  /// Virtual method implemented by subclasses that returns a reference to that
-  /// target's TargetSubtargetInfo-derived member variable.
-  virtual const TargetSubtargetInfo *getSubtargetImpl(const Function &) const {
-    return nullptr;
-  }
   virtual TargetLoweringObjectFile *getObjFileLowering() const {
     return nullptr;
   }
 
-  /// This method returns a pointer to the specified type of
-  /// TargetSubtargetInfo.  In debug builds, it verifies that the object being
-  /// returned is of the correct type.
-  template <typename STC> const STC &getSubtarget(const Function &F) const {
-    return *static_cast<const STC*>(getSubtargetImpl(F));
-  }
-
   /// Create a DataLayout.
   const DataLayout createDataLayout() const { return DL; }
 
   /// Test if a DataLayout if compatible with the CodeGen for this target.
   ///
   /// The LLVM Module owns a DataLayout that is used for the target independent
   /// optimizations and code generation. This hook provides a target specific
   /// check on the validity of this DataLayout.
public:
   /// MCStreamer.
   ///
   virtual bool addPassesToEmitMC(PassManagerBase &, MCContext *&,
                                  raw_pwrite_stream &,
                                  bool /*DisableVerify*/ = true) {
     return true;
   }
 
-  /// True if subtarget inserts the final scheduling pass on its own.
-  ///
-  /// Branch relaxation, which must happen after block placement, can
-  /// on some targets (e.g. SystemZ) expose additional post-RA
-  /// scheduling opportunities.
-  virtual bool targetSchedulesPostRAScheduling() const { return false; };
-
   void getNameWithPrefix(SmallVectorImpl<char> &Name, const GlobalValue *GV,
                          Mangler &Mang, bool MayAlwaysUsePrivate = false) const;
   MCSymbol *getSymbol(const GlobalValue *GV) const;
 
-  /// True if the target uses physical regs at Prolog/Epilog insertion
-  /// time. If true (most machines), all vregs must be allocated before
-  /// PEI. If false (virtual-register machines), then callee-save register
-  /// spilling and scavenging are not needed or used.
-  virtual bool usesPhysRegsForPEI() const { return true; }
+  virtual bool useAA(const Function &F) const { return false; }
 
-  /// True if the target wants to use interprocedural register allocation by
-  /// default. The -enable-ipra flag can be used to override this.
-  virtual bool useIPRA() const {
-    return false;
+  virtual const TargetLowering *getTargetLowering(const Function &F) const {
+    return nullptr;
   }
 };
 
 /// This class describes a target machine that is implemented with the LLVM
 /// target-independent code generator.
 ///
 class LLVMTargetMachine : public TargetMachine {
 protected: // Can only create subclasses.
public:
   /// Add passes to the specified pass manager to get machine code emitted with
   /// the MCJIT. This method returns true if machine code is not supported. It
   /// fills the MCContext Ctx pointer which can be used to build custom
   /// MCStreamer.
   bool addPassesToEmitMC(PassManagerBase &PM, MCContext *&Ctx,
                          raw_pwrite_stream &OS,
                          bool DisableVerify = true) override;
 
+  /// \brief Adds an AsmPrinter pass to the pipeline that prints assembly or
+  /// machine code from the MI representation.
+  bool addAsmPrinter(PassManagerBase &PM, raw_pwrite_stream &Out,
+                     CodeGenFileType FileTYpe, MCContext &Context);
+
+  /// Virtual method implemented by subclasses that returns a reference to that
+  /// target's TargetSubtargetInfo-derived member variable.
+  virtual const TargetSubtargetInfo *getSubtargetImpl(const Function &) const
+    = 0;
+
+  /// This method returns a pointer to the specified type of
+  /// TargetSubtargetInfo.  In debug builds, it verifies that the object being
+  /// returned is of the correct type.
+  template <typename STC> const STC &getSubtarget(const Function &F) const {
+    return *static_cast<const STC*>(getSubtargetImpl(F));
+  }
+
+  /// True if subtarget inserts the final scheduling pass on its own.
+  ///
+  /// Branch relaxation, which must happen after block placement, can
+  /// on some targets (e.g. SystemZ) expose additional post-RA
+  /// scheduling opportunities.
+  virtual bool targetSchedulesPostRAScheduling() const { return false; };
+
+  /// True if the target uses physical regs at Prolog/Epilog insertion
+  /// time. If true (most machines), all vregs must be allocated before
+  /// PEI. If false (virtual-register machines), then callee-save register
+  /// spilling and scavenging are not needed or used.
+  virtual bool usesPhysRegsForPEI() const { return true; }
+
+  /// True if the target wants to use interprocedural register allocation by
+  /// default. The -enable-ipra flag can be used to override this.
+  virtual bool useIPRA() const {
+    return false;
+  }
+
   /// Returns true if the target is expected to pass all machine verifier
   /// checks. This is a stopgap measure to fix targets one by one. We will
   /// remove this at some point and always enable the verifier when
   /// EXPENSIVE_CHECKS is enabled.
   virtual bool isMachineVerifierClean() const { return true; }
 
-  /// \brief Adds an AsmPrinter pass to the pipeline that prints assembly or
-  /// machine code from the MI representation.
-  bool addAsmPrinter(PassManagerBase &PM, raw_pwrite_stream &Out,
-                     CodeGenFileType FileTYpe, MCContext &Context);
+  bool useAA(const Function &F) const override;
+
+  const TargetLowering *getTargetLowering(const Function &F) const override;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_TARGET_TARGETMACHINE_H

lib/CodeGen/Analysis.cpp

 
 
 /// Test if the given instruction is in a position to be optimized
 /// with a tail-call. This roughly means that it's in a block with
 /// a return and there's nothing that needs to be scheduled
 /// between it and the return.
 ///
 /// This function only tests target-independent requirements.
-bool llvm::isInTailCallPosition(ImmutableCallSite CS, const TargetMachine &TM) {
+bool llvm::isInTailCallPosition(ImmutableCallSite CS,
+                                const LLVMTargetMachine &TM) {
   const Instruction *I = CS.getInstruction();
   const BasicBlock *ExitBB = I->getParent();
   const TerminatorInst *Term = ExitBB->getTerminator();
   const ReturnInst *Ret = dyn_cast<ReturnInst>(Term);
 
   // The block must end in a return statement or unreachable.
   //
   // FIXME: Decline tailcall if it's not guaranteed and if the block ends in

lib/CodeGen/AsmPrinter/AsmPrinter.cpp

static unsigned getGVAlignmentLog2(const GlobalValue *GV, const DataLayout &DL,
 
   // If the GVAlign is larger than NumBits, or if we are required to obey
   // NumBits because the GV has an assigned section, obey it.
   if (GVAlign > NumBits || GV->hasSection())
     NumBits = GVAlign;
   return NumBits;
 }
 
-AsmPrinter::AsmPrinter(TargetMachine &tm, std::unique_ptr<MCStreamer> Streamer)
+AsmPrinter::AsmPrinter(LLVMTargetMachine &tm,
+                       std::unique_ptr<MCStreamer> Streamer)
     : MachineFunctionPass(ID), TM(tm), MAI(tm.getMCAsmInfo()),
       OutContext(Streamer->getContext()), OutStreamer(std::move(Streamer)) {
   VerboseAsm = OutStreamer->isVerboseAsm();
 }
 
 AsmPrinter::~AsmPrinter() {
   assert(!DD && Handlers.empty() && "Debug/EH info didn't get finalized");
 

lib/CodeGen/AtomicExpandPass.cpp

static bool atomicSizeSupported(const TargetLowering *TLI, Inst *I) {
   return Align >= Size && Size <= TLI->getMaxAtomicSizeInBitsSupported() / 8;
 }
 
 bool AtomicExpand::runOnFunction(Function &F) {
   auto *TPC = getAnalysisIfAvailable<TargetPassConfig>();
   if (!TPC)
     return false;
 
-  auto &TM = TPC->getTM<TargetMachine>();
+  auto &TM = TPC->getTM<LLVMTargetMachine>();
   if (!TM.getSubtargetImpl(F)->enableAtomicExpand())
     return false;
   TLI = TM.getSubtargetImpl(F)->getTargetLowering();
 
   SmallVector<Instruction *, 1> AtomicInsts;
 
   // Changing control-flow while iterating through it is a bad idea, so gather a
   // list of all atomic instructions before we start.

lib/CodeGen/BasicTargetTransformInfo.cpp

 
 // This flag is used by the template base class for BasicTTIImpl, and here to
 // provide a definition.
 cl::opt<unsigned>
     llvm::PartialUnrollingThreshold("partial-unrolling-threshold", cl::init(0),
                                     cl::desc("Threshold for partial unrolling"),
                                     cl::Hidden);
 
-BasicTTIImpl::BasicTTIImpl(const TargetMachine *TM, const Function &F)
+BasicTTIImpl::BasicTTIImpl(const LLVMTargetMachine *TM, const Function &F)
     : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
       TLI(ST->getTargetLowering()) {}

lib/CodeGen/CodeGenPrepare.cpp

 using TypeIsSExt = PointerIntPair<Type *, 1, bool>;
 using InstrToOrigTy = DenseMap<Instruction *, TypeIsSExt>;
 using SExts = SmallVector<Instruction *, 16>;
 using ValueToSExts = DenseMap<Value *, SExts>;
 
 class TypePromotionTransaction;
 
   class CodeGenPrepare : public FunctionPass {
-    const TargetMachine *TM = nullptr;
+    const LLVMTargetMachine *TM = nullptr;
     const TargetSubtargetInfo *SubtargetInfo;
     const TargetLowering *TLI = nullptr;
     const TargetRegisterInfo *TRI;
     const TargetTransformInfo *TTI = nullptr;
     const TargetLibraryInfo *TLInfo;
     const LoopInfo *LI;
     std::unique_ptr<BlockFrequencyInfo> BFI;
     std::unique_ptr<BranchProbabilityInfo> BPI;
bool CodeGenPrepare::runOnFunction(Function &F) {
   // Clear per function information.
   InsertedInsts.clear();
   PromotedInsts.clear();
   BFI.reset();
   BPI.reset();
 
   ModifiedDT = false;
   if (auto *TPC = getAnalysisIfAvailable<TargetPassConfig>()) {
-    TM = &TPC->getTM<TargetMachine>();
+    TM = &TPC->getTM<LLVMTargetMachine>();
     SubtargetInfo = TM->getSubtargetImpl(F);
     TLI = SubtargetInfo->getTargetLowering();
     TRI = SubtargetInfo->getRegisterInfo();
   }
   TLInfo = &getAnalysis<TargetLibraryInfoWrapperPass>().getTLI();
   TTI = &getAnalysis<TargetTransformInfoWrapperPass>().getTTI(F);
   LI = &getAnalysis<LoopInfoWrapperPass>().getLoopInfo();
   OptSize = F.optForSize();

lib/CodeGen/DwarfEHPrepare.cpp

bool DwarfEHPrepare::InsertUnwindResumeCalls(Function &Fn) {
   CI->setCallingConv(TLI->getLibcallCallingConv(RTLIB::UNWIND_RESUME));
 
   // We never expect _Unwind_Resume to return.
   new UnreachableInst(Ctx, UnwindBB);
   return true;
 }
 
 bool DwarfEHPrepare::runOnFunction(Function &Fn) {
-  const TargetMachine &TM =
-      getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
+  const LLVMTargetMachine &TM =
+      getAnalysis<TargetPassConfig>().getTM<LLVMTargetMachine>();
   DT = &getAnalysis<DominatorTreeWrapperPass>().getDomTree();
   TLI = TM.getSubtargetImpl(Fn)->getTargetLowering();
   bool Changed = InsertUnwindResumeCalls(Fn);
   DT = nullptr;
   TLI = nullptr;
   return Changed;
 }

lib/CodeGen/InterleavedAccessPass.cpp

 bool InterleavedAccess::runOnFunction(Function &F) {
   auto *TPC = getAnalysisIfAvailable<TargetPassConfig>();
   if (!TPC || !LowerInterleavedAccesses)
     return false;
 
   DEBUG(dbgs() << "*** " << getPassName() << ": " << F.getName() << "\n");
 
   DT = &getAnalysis<DominatorTreeWrapperPass>().getDomTree();
-  auto &TM = TPC->getTM<TargetMachine>();
+  auto &TM = TPC->getTM<LLVMTargetMachine>();
   TLI = TM.getSubtargetImpl(F)->getTargetLowering();
   MaxFactor = TLI->getMaxSupportedInterleaveFactor();
 
   // Holds dead instructions that will be erased later.
   SmallVector<Instruction *, 32> DeadInsts;
   bool Changed = false;
 
   for (auto &I : instructions(F)) {

lib/CodeGen/LLVMTargetMachine.cpp

bool LLVMTargetMachine::addPassesToEmitMC(PassManagerBase &PM, MCContext *&Ctx,
   if (!Printer)
     return true;
 
   PM.add(Printer);
   PM.add(createFreeMachineFunctionPass());
 
   return false; // success!
 }
+
+bool LLVMTargetMachine::useAA(const Function &F) const {
+  return getSubtargetImpl(F)->useAA();
+}
+
+const TargetLowering *
+LLVMTargetMachine::getTargetLowering(const Function &F) const {
+  return getSubtargetImpl(F)->getTargetLowering();
+}

lib/CodeGen/MachineFunction.cpp

 
 static inline unsigned getFnStackAlignment(const TargetSubtargetInfo *STI,
                                            const Function *Fn) {
   if (Fn->hasFnAttribute(Attribute::StackAlignment))
     return Fn->getFnStackAlignment();
   return STI->getFrameLowering()->getStackAlignment();
 }
 
-MachineFunction::MachineFunction(const Function *F, const TargetMachine &TM,
+MachineFunction::MachineFunction(const Function *F, const LLVMTargetMachine &TM,
                                  unsigned FunctionNum, MachineModuleInfo &mmi)
     : Fn(F), Target(TM), STI(TM.getSubtargetImpl(*F)), Ctx(mmi.getContext()),
       MMI(mmi) {
   FunctionNumber = FunctionNum;
   init();
 }
 
 void MachineFunction::init() {

lib/CodeGen/MachineModuleInfo.cpp

 void MMIAddrLabelMapCallbackPtr::deleted() {
   Map->UpdateForDeletedBlock(cast<BasicBlock>(getValPtr()));
 }
 
 void MMIAddrLabelMapCallbackPtr::allUsesReplacedWith(Value *V2) {
   Map->UpdateForRAUWBlock(cast<BasicBlock>(getValPtr()), cast<BasicBlock>(V2));
 }
 
-MachineModuleInfo::MachineModuleInfo(const TargetMachine *TM)
+MachineModuleInfo::MachineModuleInfo(const LLVMTargetMachine *TM)
   : ImmutablePass(ID), TM(*TM),
     Context(TM->getMCAsmInfo(), TM->getMCRegisterInfo(),
             TM->getObjFileLowering(), nullptr, false) {
   initializeMachineModuleInfoPass(*PassRegistry::getPassRegistry());
 }
 
 MachineModuleInfo::~MachineModuleInfo() = default;
 

lib/CodeGen/PrologEpilogInserter.cpp

 /// StackObjSet - A set of stack object indexes
 typedef SmallSetVector<int, 8> StackObjSet;
 
 /// runOnMachineFunction - Insert prolog/epilog code and replace abstract
 /// frame indexes with appropriate references.
 ///
 bool PEI::runOnMachineFunction(MachineFunction &Fn) {
   if (!SpillCalleeSavedRegisters) {
-    const TargetMachine &TM = Fn.getTarget();
+    const LLVMTargetMachine &TM = Fn.getTarget();
     if (!TM.usesPhysRegsForPEI()) {
       SpillCalleeSavedRegisters = [](MachineFunction &, RegScavenger *,
                                      unsigned &, unsigned &, const MBBVector &,
                                      const MBBVector &) {};
       ScavengeFrameVirtualRegs = [](MachineFunction &, RegScavenger &) {};
     } else {
       SpillCalleeSavedRegisters = doSpillCalleeSavedRegs;
       ScavengeFrameVirtualRegs = scavengeFrameVirtualRegs;

lib/CodeGen/RegUsageInfoCollector.cpp

void RegUsageInfoCollector::getAnalysisUsage(AnalysisUsage &AU) const {
   AU.addRequired<PhysicalRegisterUsageInfo>();
   AU.setPreservesAll();
   MachineFunctionPass::getAnalysisUsage(AU);
 }
 
 bool RegUsageInfoCollector::runOnMachineFunction(MachineFunction &MF) {
   MachineRegisterInfo *MRI = &MF.getRegInfo();
   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
-  const TargetMachine &TM = MF.getTarget();
+  const LLVMTargetMachine &TM = MF.getTarget();
 
   DEBUG(dbgs() << " -------------------- " << getPassName()
                << " -------------------- \n");
   DEBUG(dbgs() << "Function Name : " << MF.getName() << "\n");
 
   std::vector<uint32_t> RegMask;
 
   // Compute the size of the bit vector to represent all the registers.

lib/CodeGen/SafeStack.cpp

for (ReturnInst *RI : Returns) {
     IRB.CreateStore(BasePointer, UnsafeStackPtr);
   }
 
   DEBUG(dbgs() << "[SafeStack]     safestack applied\n");
   return true;
 }
 
 class SafeStackLegacyPass : public FunctionPass {
-  const TargetMachine *TM = nullptr;
-
 public:
   static char ID; // Pass identification, replacement for typeid..
 
   SafeStackLegacyPass() : FunctionPass(ID) {
     initializeSafeStackLegacyPassPass(*PassRegistry::getPassRegistry());
   }
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
bool runOnFunction(Function &F) override {
     }
 
     if (F.isDeclaration()) {
       DEBUG(dbgs() << "[SafeStack]     function definition"
                       " is not available\n");
       return false;
     }
 
-    TM = &getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
-    auto *TL = TM->getSubtargetImpl(F)->getTargetLowering();
+    const LLVMTargetMachine &TM =
+      getAnalysis<TargetPassConfig>().getTM<LLVMTargetMachine>();
+    auto *TL = TM.getSubtargetImpl(F)->getTargetLowering();
     if (!TL)
       report_fatal_error("TargetLowering instance is required");
 
     auto *DL = &F.getParent()->getDataLayout();
     auto &TLI = getAnalysis<TargetLibraryInfoWrapperPass>().getTLI();
     auto &ACT = getAnalysis<AssumptionCacheTracker>().getAssumptionCache(F);
 
     // Compute DT and LI only for functions that have the attribute.

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

unsigned SelectionDAG::getEVTAlignment(EVT VT) const {
   Type *Ty = VT == MVT::iPTR ?
                    PointerType::get(Type::getInt8Ty(*getContext()), 0) :
                    VT.getTypeForEVT(*getContext());
 
   return getDataLayout().getABITypeAlignment(Ty);
 }
 
 // EntryNode could meaningfully have debug info if we can find it...
-SelectionDAG::SelectionDAG(const TargetMachine &tm, CodeGenOpt::Level OL)
+SelectionDAG::SelectionDAG(const LLVMTargetMachine &tm, CodeGenOpt::Level OL)
     : TM(tm), OptLevel(OL),
       EntryNode(ISD::EntryToken, 0, DebugLoc(), getVTList(MVT::Other)),
       Root(getEntryNode()) {
   InsertNode(&EntryNode);
   DbgInfo = new SDDbgInfo();
 }
 
 void SelectionDAG::init(MachineFunction &NewMF,

lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

assert(!MI.hasPostISelHook() &&
          "If a target marks an instruction with 'hasPostISelHook', "
          "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
 }
 
 //===----------------------------------------------------------------------===//
 // SelectionDAGISel code
 //===----------------------------------------------------------------------===//
 
-SelectionDAGISel::SelectionDAGISel(TargetMachine &tm,
+SelectionDAGISel::SelectionDAGISel(LLVMTargetMachine &tm,
                                    CodeGenOpt::Level OL) :
   MachineFunctionPass(ID), TM(tm),
   FuncInfo(new FunctionLoweringInfo()),
   CurDAG(new SelectionDAG(tm, OL)),
   SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
   AA(), GFI(),
   OptLevel(OL),
   DAGSize(0) {

lib/CodeGen/SelectionDAG/TargetLowering.cpp

 #include "llvm/Support/MathExtras.h"
 #include "llvm/Target/TargetLoweringObjectFile.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetRegisterInfo.h"
 #include "llvm/Target/TargetSubtargetInfo.h"
 #include <cctype>
 using namespace llvm;
 
-/// NOTE: The TargetMachine owns TLOF.
-TargetLowering::TargetLowering(const TargetMachine &tm)
+/// NOTE: The LLVMTargetMachine owns TLOF.
+TargetLowering::TargetLowering(const LLVMTargetMachine &tm)
   : TargetLoweringBase(tm) {}
 
 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
   return nullptr;
 }
 
 bool TargetLowering::isPositionIndependent() const {
   return getTargetMachine().isPositionIndependent();

 /// getPICJumpTableRelocBase, but as an MCExpr.
 const MCExpr *
 TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
                                              unsigned JTI,MCContext &Ctx) const{
   // The normal PIC reloc base is the label at the start of the jump table.
   return MCSymbolRefExpr::create(MF->getJTISymbol(JTI, Ctx), Ctx);
 }
 
-bool
-TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
-  const TargetMachine &TM = getTargetMachine();
+bool TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
+  const LLVMTargetMachine &TM = getTargetMachine();
   const GlobalValue *GV = GA->getGlobal();
 
   // If the address is not even local to this DSO we will have to load it from
   // a got and then add the offset.
   if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
     return false;
 
   // If the code is position independent we will have to add a base register.

lib/CodeGen/StackProtector.cpp

 }
 
 bool StackProtector::runOnFunction(Function &Fn) {
   F = &Fn;
   M = F->getParent();
   DominatorTreeWrapperPass *DTWP =
       getAnalysisIfAvailable<DominatorTreeWrapperPass>();
   DT = DTWP ? &DTWP->getDomTree() : nullptr;
-  TM = &getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
+  TM = &getAnalysis<TargetPassConfig>().getTM<LLVMTargetMachine>();
   Trip = TM->getTargetTriple();
   TLI = TM->getSubtargetImpl(Fn)->getTargetLowering();
   HasPrologue = false;
   HasIRCheck = false;
 
   Attribute Attr = Fn.getFnAttribute("stack-protector-buffer-size");
   if (Attr.isStringAttribute() &&
       Attr.getValueAsString().getAsInteger(10, SSPBufferSize))

lib/CodeGen/TargetLoweringBase.cpp

static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
   CCs[RTLIB::UO_F128] = ISD::SETNE;
   CCs[RTLIB::UO_PPCF128] = ISD::SETNE;
   CCs[RTLIB::O_F32] = ISD::SETEQ;
   CCs[RTLIB::O_F64] = ISD::SETEQ;
   CCs[RTLIB::O_F128] = ISD::SETEQ;
   CCs[RTLIB::O_PPCF128] = ISD::SETEQ;
 }
 
-/// NOTE: The TargetMachine owns TLOF.
-TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm) : TM(tm) {
+/// NOTE: The LLVMTargetMachine owns TLOF.
+TargetLoweringBase::TargetLoweringBase(const LLVMTargetMachine &tm) : TM(tm) {
   initActions();
 
   // Perform these initializations only once.
   MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove =
       MaxLoadsPerMemcmp = 8;
   MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize =
       MaxStoresPerMemmoveOptSize = MaxLoadsPerMemcmpOptSize = 4;
   UseUnderscoreSetJmp = false;

lib/LTO/UpdateCompilerUsed.cpp

for (unsigned I = 0, E = static_cast<unsigned>(LibFunc::NumLibFuncs);
       LibFunc F = static_cast<LibFunc>(I);
       if (TLI.has(F))
         Libcalls.insert(TLI.getName(F));
     }
 
     SmallPtrSet<const TargetLowering *, 1> TLSet;
 
     for (const Function &F : TheModule) {
-      const TargetLowering *Lowering =
-          TM.getSubtargetImpl(F)->getTargetLowering();
-
+      const TargetLowering *Lowering = TM.getTargetLowering(F);
       if (Lowering && TLSet.insert(Lowering).second)
         // TargetLowering has info on library calls that CodeGen expects to be
         // available, both from the C runtime and compiler-rt.
         for (unsigned I = 0, E = static_cast<unsigned>(RTLIB::UNKNOWN_LIBCALL);
              I != E; ++I)
           if (const char *Name =
                   Lowering->getLibcallName(static_cast<RTLIB::Libcall>(I)))
             Libcalls.insert(Name);

lib/Target/AArch64/AArch64AsmPrinter.cpp

 namespace {
 
 class AArch64AsmPrinter : public AsmPrinter {
   AArch64MCInstLower MCInstLowering;
   StackMaps SM;
   const AArch64Subtarget *STI;
 
 public:
-  AArch64AsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer)
+  AArch64AsmPrinter(LLVMTargetMachine &TM, std::unique_ptr<MCStreamer> Streamer)
       : AsmPrinter(TM, std::move(Streamer)), MCInstLowering(OutContext, *this),
         SM(*this) {}
 
   StringRef getPassName() const override { return "AArch64 Assembly Printer"; }
 
   /// \brief Wrapper for MCInstLowering.lowerOperand() for the
   /// tblgen'erated pseudo lowering.
   bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const {

lib/Target/AArch64/AArch64ISelLowering.h

 
 } // end anonymous namespace
 
 class AArch64Subtarget;
 class AArch64TargetMachine;
 
 class AArch64TargetLowering : public TargetLowering {
 public:
-  explicit AArch64TargetLowering(const TargetMachine &TM,
+  explicit AArch64TargetLowering(const LLVMTargetMachine &TM,
                                  const AArch64Subtarget &STI);
 
   /// Selects the correct CCAssignFn for a given CallingConvention value.
   CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const;
 
   /// Selects the correct CCAssignFn for a given CallingConvention value.
   CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC) const;
 

lib/Target/AArch64/AArch64ISelLowering.cpp

 EnableOptimizeLogicalImm("aarch64-enable-logical-imm", cl::Hidden,
                          cl::desc("Enable AArch64 logical imm instruction "
                                   "optimization"),
                          cl::init(true));
 
 /// Value type used for condition codes.
 static const MVT MVT_CC = MVT::i32;
 
-AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
+AArch64TargetLowering::AArch64TargetLowering(const LLVMTargetMachine &TM,
                                              const AArch64Subtarget &STI)
     : TargetLowering(TM), Subtarget(&STI) {
   // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
   // we have to make something up. Arbitrarily, choose ZeroOrOne.
   setBooleanContents(ZeroOrOneBooleanContent);
   // When comparing vectors the result sets the different elements in the
   // vector to all-one or all-zero.
   setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);

lib/Target/AArch64/AArch64Subtarget.h

private:
 
   /// Initialize properties based on the selected processor family.
   void initializeProperties();
 
 public:
   /// This constructor initializes the data members to match that
   /// of the specified triple.
   AArch64Subtarget(const Triple &TT, const std::string &CPU,
-                   const std::string &FS, const TargetMachine &TM,
+                   const std::string &FS, const LLVMTargetMachine &TM,
                    bool LittleEndian);
 
   const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override {
     return &TSInfo;
   }
   const AArch64FrameLowering *getFrameLowering() const override {
     return &FrameLowering;
   }

lib/Target/AArch64/AArch64Subtarget.cpp

case CortexA75:
     PrefFunctionAlignment = 4;
     break;
   case Others: break;
   }
 }
 
 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
                                    const std::string &FS,
-                                   const TargetMachine &TM, bool LittleEndian)
+                                   const LLVMTargetMachine &TM,
+                                   bool LittleEndian)
     : AArch64GenSubtargetInfo(TT, CPU, FS),
       ReserveX18(TT.isOSDarwin() || TT.isOSWindows()), IsLittle(LittleEndian),
       TargetTriple(TT), FrameLowering(),
       InstrInfo(initializeSubtargetDependencies(FS, CPU)), TSInfo(),
       TLInfo(TM, *this) {
   CallLoweringInfo.reset(new AArch64CallLowering(*getTargetLowering()));
   Legalizer.reset(new AArch64LegalizerInfo());
 

lib/Target/AArch64/AArch64TargetTransformInfo.cpp

 
 #define DEBUG_TYPE "aarch64tti"
 
 static cl::opt<bool> EnableFalkorHWPFUnrollFix("enable-falkor-hwpf-unroll-fix",
                                                cl::init(true), cl::Hidden);
 
 bool AArch64TTIImpl::areInlineCompatible(const Function *Caller,
                                          const Function *Callee) const {
-  const TargetMachine &TM = getTLI()->getTargetMachine();
+  const LLVMTargetMachine &TM = getTLI()->getTargetMachine();
 
   const FeatureBitset &CallerBits =
       TM.getSubtargetImpl(*Caller)->getFeatureBits();
   const FeatureBitset &CalleeBits =
       TM.getSubtargetImpl(*Callee)->getFeatureBits();
 
   // Inline a callee if its target-features are a subset of the callers
   // target-features.

lib/Target/AMDGPU/AMDGPU.h

 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
 #include "llvm/Target/TargetMachine.h"
 
 namespace llvm {
 
 class AMDGPUTargetMachine;
 class FunctionPass;
 class GCNTargetMachine;
+class LLVMTargetMachine;
+class Module;
 class ModulePass;
 class Pass;
-class Target;
-class TargetMachine;
 class PassRegistry;
-class Module;
+class Target;
 
 // R600 Passes
 FunctionPass *createR600VectorRegMerger();
 FunctionPass *createR600ExpandSpecialInstrsPass();
 FunctionPass *createR600EmitClauseMarkers();
 FunctionPass *createR600ClauseMergePass();
 FunctionPass *createR600Packetizer();
 FunctionPass *createR600ControlFlowFinalizer();
 FunctionPass *createAMDGPUCFGStructurizerPass();
-FunctionPass *createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel);
+FunctionPass *createR600ISelDag(LLVMTargetMachine *TM,
+                                CodeGenOpt::Level OptLevel);
 
 // SI Passes
 FunctionPass *createSIAnnotateControlFlowPass();
 FunctionPass *createSIFoldOperandsPass();
 FunctionPass *createSIPeepholeSDWAPass();
 FunctionPass *createSILowerI1CopiesPass();
 FunctionPass *createSIShrinkInstructionsPass();
 FunctionPass *createSILoadStoreOptimizerPass();

 
 // Passes common to R600 and SI
 FunctionPass *createAMDGPUPromoteAlloca();
 void initializeAMDGPUPromoteAllocaPass(PassRegistry&);
 extern char &AMDGPUPromoteAllocaID;
 
 Pass *createAMDGPUStructurizeCFGPass();
 FunctionPass *createAMDGPUISelDag(
-  TargetMachine *TM = nullptr,
+  LLVMTargetMachine *TM = nullptr,
   CodeGenOpt::Level OptLevel = CodeGenOpt::Default);
 ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true);
 ModulePass *createAMDGPUOpenCLImageTypeLoweringPass();
 FunctionPass *createAMDGPUAnnotateUniformValues();
 
 ModulePass* createAMDGPUUnifyMetadataPass();
 void initializeAMDGPUUnifyMetadataPass(PassRegistry&);
 extern char &AMDGPUUnifyMetadataID;
struct AMDGPUAS {
 
   // Some places use this if the address space can't be determined.
   const static unsigned UNKNOWN_ADDRESS_SPACE = ~0u;
 };
 
 namespace llvm {
 namespace AMDGPU {
 AMDGPUAS getAMDGPUAS(const Module &M);
-AMDGPUAS getAMDGPUAS(const TargetMachine &TM);
+AMDGPUAS getAMDGPUAS(const LLVMTargetMachine &TM);
 AMDGPUAS getAMDGPUAS(Triple T);
 } // namespace AMDGPU
 } // namespace llvm
 
 #endif

lib/Target/AMDGPU/AMDGPUAnnotateKernelFeatures.cpp

 #define DEBUG_TYPE "amdgpu-annotate-kernel-features"
 
 using namespace llvm;
 
 namespace {
 
 class AMDGPUAnnotateKernelFeatures : public CallGraphSCCPass {
 private:
-  const TargetMachine *TM = nullptr;
+  const LLVMTargetMachine *TM = nullptr;
   AMDGPUAS AS;
 
   bool addFeatureAttributes(Function &F);
 
 public:
   static char ID;
 
   AMDGPUAnnotateKernelFeatures() : CallGraphSCCPass(ID) {}

 }
 
 bool AMDGPUAnnotateKernelFeatures::doInitialization(CallGraph &CG) {
   auto *TPC = getAnalysisIfAvailable<TargetPassConfig>();
   if (!TPC)
     report_fatal_error("TargetMachine is required");
 
   AS = AMDGPU::getAMDGPUAS(CG.getModule());
-  TM = &TPC->getTM<TargetMachine>();
+  TM = &TPC->getTM<LLVMTargetMachine>();
   return false;
 }
 
 Pass *llvm::createAMDGPUAnnotateKernelFeaturesPass() {
   return new AMDGPUAnnotateKernelFeatures();
 }

lib/Target/AMDGPU/AMDGPUAsmPrinter.h

private:
   void EmitProgramInfoR600(const MachineFunction &MF);
   void EmitProgramInfoSI(const MachineFunction &MF, const SIProgramInfo &KernelInfo);
   void emitCommonFunctionComments(uint32_t NumVGPR,
                                   uint32_t NumSGPR,
                                   uint32_t ScratchSize,
                                   uint64_t CodeSize);
 
 public:
-  explicit AMDGPUAsmPrinter(TargetMachine &TM,
+  explicit AMDGPUAsmPrinter(LLVMTargetMachine &TM,
                             std::unique_ptr<MCStreamer> Streamer);
 
   StringRef getPassName() const override;
 
   const MCSubtargetInfo* getSTI() const;
 
   AMDGPUTargetStreamer& getTargetStreamer() const;
 

lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

static uint32_t getFPMode(const MachineFunction &F) {
 
   return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
          FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
          FP_DENORM_MODE_SP(FP32Denormals) |
          FP_DENORM_MODE_DP(FP64Denormals);
 }
 
 static AsmPrinter *
-createAMDGPUAsmPrinterPass(TargetMachine &tm,
+createAMDGPUAsmPrinterPass(TargetMachine &TM,
                            std::unique_ptr<MCStreamer> &&Streamer) {
-  return new AMDGPUAsmPrinter(tm, std::move(Streamer));
+  LLVMTargetMachine &LLVMTM = static_cast<LLVMTargetMachine&>(TM);
+  return new AMDGPUAsmPrinter(LLVMTM, std::move(Streamer));
 }
 
 extern "C" void LLVMInitializeAMDGPUAsmPrinter() {
   TargetRegistry::RegisterAsmPrinter(getTheAMDGPUTarget(),
                                      createAMDGPUAsmPrinterPass);
   TargetRegistry::RegisterAsmPrinter(getTheGCNTarget(),
                                      createAMDGPUAsmPrinterPass);
 }
 
-AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
+AMDGPUAsmPrinter::AMDGPUAsmPrinter(LLVMTargetMachine &TM,
                                    std::unique_ptr<MCStreamer> Streamer)
   : AsmPrinter(TM, std::move(Streamer)) {
     AMDGPUASI = static_cast<AMDGPUTargetMachine*>(&TM)->getAMDGPUAS();
   }
 
 StringRef AMDGPUAsmPrinter::getPassName() const {
   return "AMDGPU Assembly Printer";
 }

lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp

 bool AMDGPUCodeGenPrepare::runOnFunction(Function &F) {
   if (skipFunction(F))
     return false;
 
   auto *TPC = getAnalysisIfAvailable<TargetPassConfig>();
   if (!TPC)
     return false;
 
-  const TargetMachine &TM = TPC->getTM<TargetMachine>();
+  const LLVMTargetMachine &TM = TPC->getTM<LLVMTargetMachine>();
   ST = &TM.getSubtarget<SISubtarget>(F);
   DA = &getAnalysis<DivergenceAnalysis>();
   HasUnsafeFPMath = hasUnsafeFPMath(F);
 
   bool MadeChange = false;
 
   for (BasicBlock &BB : F) {
     BasicBlock::iterator Next;

lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

 /// SelectionDAG operations.
 class AMDGPUDAGToDAGISel : public SelectionDAGISel {
   // Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
   // make the right decision when generating code for different targets.
   const AMDGPUSubtarget *Subtarget;
   AMDGPUAS AMDGPUASI;
 
 public:
-  explicit AMDGPUDAGToDAGISel(TargetMachine *TM = nullptr,
+  explicit AMDGPUDAGToDAGISel(LLVMTargetMachine *TM = nullptr,
                               CodeGenOpt::Level OptLevel = CodeGenOpt::Default)
     : SelectionDAGISel(*TM, OptLevel) {
     AMDGPUASI = AMDGPU::getAMDGPUAS(*TM);
   }
   ~AMDGPUDAGToDAGISel() override = default;
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.addRequired<AMDGPUArgumentUsageInfo>();

 
 protected:
   // Include the pieces autogenerated from the target description.
 #include "AMDGPUGenDAGISel.inc"
 };
 
 class R600DAGToDAGISel : public AMDGPUDAGToDAGISel {
 public:
-  explicit R600DAGToDAGISel(TargetMachine *TM, CodeGenOpt::Level OptLevel) :
+  explicit R600DAGToDAGISel(LLVMTargetMachine *TM, CodeGenOpt::Level OptLevel) :
       AMDGPUDAGToDAGISel(TM, OptLevel) {}
 
   void Select(SDNode *N) override;
 
   bool SelectADDRIndirect(SDValue Addr, SDValue &Base,
                           SDValue &Offset) override;
   bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
                           SDValue &Offset) override;
 };
 
 }  // end anonymous namespace
 
 INITIALIZE_PASS_BEGIN(AMDGPUDAGToDAGISel, "isel",
                       "AMDGPU DAG->DAG Pattern Instruction Selection", false, false)
 INITIALIZE_PASS_DEPENDENCY(AMDGPUArgumentUsageInfo)
 INITIALIZE_PASS_END(AMDGPUDAGToDAGISel, "isel",
                     "AMDGPU DAG->DAG Pattern Instruction Selection", false, false)
 
 /// \brief This pass converts a legalized DAG into a AMDGPU-specific
 // DAG, ready for instruction scheduling.
-FunctionPass *llvm::createAMDGPUISelDag(TargetMachine *TM,
+FunctionPass *llvm::createAMDGPUISelDag(LLVMTargetMachine *TM,
                                         CodeGenOpt::Level OptLevel) {
   return new AMDGPUDAGToDAGISel(TM, OptLevel);
 }
 
 /// \brief This pass converts a legalized DAG into a R600-specific
 // DAG, ready for instruction scheduling.
-FunctionPass *llvm::createR600ISelDag(TargetMachine *TM,
+FunctionPass *llvm::createR600ISelDag(LLVMTargetMachine *TM,
                                       CodeGenOpt::Level OptLevel) {
   return new R600DAGToDAGISel(TM, OptLevel);
 }
 
 bool AMDGPUDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
   Subtarget = &MF.getSubtarget<AMDGPUSubtarget>();
   return SelectionDAGISel::runOnMachineFunction(MF);
 }

lib/Target/AMDGPU/AMDGPUISelLowering.h

protected:
   SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
   void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
                                     SmallVectorImpl<SDValue> &Results) const;
   void analyzeFormalArgumentsCompute(CCState &State,
                               const SmallVectorImpl<ISD::InputArg> &Ins) const;
 public:
-  AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI);
+  AMDGPUTargetLowering(const LLVMTargetMachine &TM, const AMDGPUSubtarget &STI);
 
   bool mayIgnoreSignedZero(SDValue Op) const {
     if (getTargetMachine().Options.NoSignedZerosFPMath)
       return true;
 
     const auto Flags = Op.getNode()->getFlags();
     if (Flags.isDefined())
       return Flags.hasNoSignedZeros();

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

if (LHSKnown.Zero.getBoolValue()) {
       if (!(~RHSKnown.Zero & ~LHSKnown.Zero))
         return true;
     }
   }
 
   return false;
 }
 
-AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
+AMDGPUTargetLowering::AMDGPUTargetLowering(const LLVMTargetMachine &TM,
                                            const AMDGPUSubtarget &STI)
     : TargetLowering(TM), Subtarget(&STI) {
   AMDGPUASI = AMDGPU::getAMDGPUAS(TM);
   // Lower floating point store/load to integer store/load to reduce the number
   // of patterns in tablegen.
   setOperationAction(ISD::LOAD, MVT::f32, Promote);
   AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
 

lib/Target/AMDGPU/AMDGPULowerIntrinsics.cpp

bool AMDGPULowerIntrinsics::expandMemIntrinsicUses(Function &F) {
   return Changed;
 }
 
 bool AMDGPULowerIntrinsics::makeLIDRangeMetadata(Function &F) const {
   auto *TPC = getAnalysisIfAvailable<TargetPassConfig>();
   if (!TPC)
     return false;
 
-  const TargetMachine &TM = TPC->getTM<TargetMachine>();
+  const LLVMTargetMachine &TM = TPC->getTM<LLVMTargetMachine>();
   const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>(F);
   bool Changed = false;
 
   for (auto *U : F.users()) {
     auto *CI = dyn_cast<CallInst>(U);
     if (!CI)
       continue;
 

lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp

 
 using namespace llvm;
 
 namespace {
 
 // FIXME: This can create globals so should be a module pass.
 class AMDGPUPromoteAlloca : public FunctionPass {
 private:
-  const TargetMachine *TM;
+  const LLVMTargetMachine *TM;
   Module *Mod = nullptr;
   const DataLayout *DL = nullptr;
   AMDGPUAS AS;
 
   // FIXME: This should be per-kernel.
   uint32_t LocalMemLimit = 0;
   uint32_t CurrentLocalMemUsage = 0;
 
bool AMDGPUPromoteAlloca::doInitialization(Module &M) {
   return false;
 }
 
 bool AMDGPUPromoteAlloca::runOnFunction(Function &F) {
   if (skipFunction(F))
     return false;
 
   if (auto *TPC = getAnalysisIfAvailable<TargetPassConfig>())
-    TM = &TPC->getTM<TargetMachine>();
+    TM = &TPC->getTM<LLVMTargetMachine>();
   else
     return false;
 
   const Triple &TT = TM->getTargetTriple();
   IsAMDGCN = TT.getArch() == Triple::amdgcn;
   IsAMDHSA = TT.getOS() == Triple::AMDHSA;
 
   const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>(F);

lib/Target/AMDGPU/AMDGPUSubtarget.h

protected:
   bool FeatureDisable;
 
   InstrItineraryData InstrItins;
   SelectionDAGTargetInfo TSInfo;
   AMDGPUAS AS;
 
 public:
   AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
-                  const TargetMachine &TM);
+                  const LLVMTargetMachine &TM);
   ~AMDGPUSubtarget() override;
 
   AMDGPUSubtarget &initializeSubtargetDependencies(const Triple &TT,
                                                    StringRef GPU, StringRef FS);
 
   const AMDGPUInstrInfo *getInstrInfo() const override = 0;
   const AMDGPUFrameLowering *getFrameLowering() const override = 0;
   const AMDGPUTargetLowering *getTargetLowering() const override = 0;

 class R600Subtarget final : public AMDGPUSubtarget {
 private:
   R600InstrInfo InstrInfo;
   R600FrameLowering FrameLowering;
   R600TargetLowering TLInfo;
 
 public:
   R600Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
-                const TargetMachine &TM);
+                const LLVMTargetMachine &TM);
 
   const R600InstrInfo *getInstrInfo() const override {
     return &InstrInfo;
   }
 
   const R600FrameLowering *getFrameLowering() const override {
     return &FrameLowering;
   }
private:
   /// GlobalISel related APIs.
   std::unique_ptr<AMDGPUCallLowering> CallLoweringInfo;
   std::unique_ptr<InstructionSelector> InstSelector;
   std::unique_ptr<LegalizerInfo> Legalizer;
   std::unique_ptr<RegisterBankInfo> RegBankInfo;
 
 public:
   SISubtarget(const Triple &TT, StringRef CPU, StringRef FS,
-              const TargetMachine &TM);
+              const LLVMTargetMachine &TM);
 
   const SIInstrInfo *getInstrInfo() const override {
     return &InstrInfo;
   }
 
   const SIFrameLowering *getFrameLowering() const override {
     return &FrameLowering;
   }

lib/Target/AMDGPU/AMDGPUSubtarget.cpp

if (TT.getArch() == Triple::amdgcn) {
     if (!HasMovrel && !HasVGPRIndexMode)
       HasMovrel = true;
   }
 
   return *this;
 }
 
 AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
-                                 const TargetMachine &TM)
+                                 const LLVMTargetMachine &TM)
   : AMDGPUGenSubtargetInfo(TT, GPU, FS),
     TargetTriple(TT),
     Gen(TT.getArch() == Triple::amdgcn ? SOUTHERN_ISLANDS : R600),
     IsaVersion(ISAVersion0_0_0),
     WavefrontSize(64),
     LocalMemorySize(0),
     LDSBankCount(0),
     MaxPrivateElementSize(0),
bool AMDGPUSubtarget::makeLIDRangeMetadata(Instruction *I) const {
   MDBuilder MDB(I->getContext());
   MDNode *MaxWorkGroupSizeRange = MDB.createRange(APInt(32, MinSize),
                                                   APInt(32, MaxSize));
   I->setMetadata(LLVMContext::MD_range, MaxWorkGroupSizeRange);
   return true;
 }
 
 R600Subtarget::R600Subtarget(const Triple &TT, StringRef GPU, StringRef FS,
-                             const TargetMachine &TM) :
+                             const LLVMTargetMachine &TM) :
   AMDGPUSubtarget(TT, GPU, FS, TM),
   InstrInfo(*this),
   FrameLowering(TargetFrameLowering::StackGrowsUp, getStackAlignment(), 0),
   TLInfo(TM, *this) {}
 
 SISubtarget::SISubtarget(const Triple &TT, StringRef GPU, StringRef FS,
-                         const TargetMachine &TM)
+                         const LLVMTargetMachine &TM)
     : AMDGPUSubtarget(TT, GPU, FS, TM), InstrInfo(*this),
       FrameLowering(TargetFrameLowering::StackGrowsUp, getStackAlignment(), 0),
       TLInfo(TM, *this) {
   CallLoweringInfo.reset(new AMDGPUCallLowering(*getTargetLowering()));
   Legalizer.reset(new AMDGPULegalizerInfo());
 
   RegBankInfo.reset(new AMDGPURegisterBankInfo(*getRegisterInfo()));
   InstSelector.reset(new AMDGPUInstructionSelector(

lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp

if (ST->hasVOP3PInsts()) {
     }
   }
 
   return BaseT::getShuffleCost(Kind, Tp, Index, SubTp);
 }
 
 bool AMDGPUTTIImpl::areInlineCompatible(const Function *Caller,
                                         const Function *Callee) const {
-  const TargetMachine &TM = getTLI()->getTargetMachine();
+  const LLVMTargetMachine &TM = getTLI()->getTargetMachine();
   const FeatureBitset &CallerBits =
     TM.getSubtargetImpl(*Caller)->getFeatureBits();
   const FeatureBitset &CalleeBits =
     TM.getSubtargetImpl(*Callee)->getFeatureBits();
 
   FeatureBitset RealCallerBits = CallerBits & ~InlineFeatureIgnoreList;
   FeatureBitset RealCalleeBits = CalleeBits & ~InlineFeatureIgnoreList;
   return ((RealCallerBits & RealCalleeBits) == RealCalleeBits);
 }

lib/Target/AMDGPU/R600ISelLowering.h

 
 namespace llvm {
 
 class R600InstrInfo;
 class R600Subtarget;
 
 class R600TargetLowering final : public AMDGPUTargetLowering {
 public:
-  R600TargetLowering(const TargetMachine &TM, const R600Subtarget &STI);
+  R600TargetLowering(const LLVMTargetMachine &TM, const R600Subtarget &STI);
 
   const R600Subtarget *getSubtarget() const;
 
   MachineBasicBlock *
   EmitInstrWithCustomInserter(MachineInstr &MI,
                               MachineBasicBlock *BB) const override;
   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
   SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;

lib/Target/AMDGPU/R600ISelLowering.cpp

 #include <cassert>
 #include <cstdint>
 #include <iterator>
 #include <utility>
 #include <vector>
 
 using namespace llvm;
 
-R600TargetLowering::R600TargetLowering(const TargetMachine &TM,
+R600TargetLowering::R600TargetLowering(const LLVMTargetMachine &TM,
                                        const R600Subtarget &STI)
     : AMDGPUTargetLowering(TM, STI), Gen(STI.getGeneration()) {
   addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
   addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
   addRegisterClass(MVT::v2f32, &AMDGPU::R600_Reg64RegClass);
   addRegisterClass(MVT::v2i32, &AMDGPU::R600_Reg64RegClass);
   addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
   addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);

lib/Target/AMDGPU/SIISelLowering.h

class SITargetLowering final : public AMDGPUTargetLowering {
   /// \p GV, false otherwise.
   bool shouldEmitGOTReloc(const GlobalValue *GV) const;
 
   /// \returns True if PC-relative relocation needs to be emitted for given
   /// global value \p GV, false otherwise.
   bool shouldEmitPCReloc(const GlobalValue *GV) const;
 
 public:
-  SITargetLowering(const TargetMachine &tm, const SISubtarget &STI);
+  SITargetLowering(const LLVMTargetMachine &tm, const SISubtarget &STI);
 
   const SISubtarget *getSubtarget() const;
 
   bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override;
 
   bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
                           unsigned IntrinsicID) const override;
 

lib/Target/AMDGPU/SIISelLowering.cpp

static unsigned findFirstFreeSGPR(CCState &CCInfo) {
   for (unsigned Reg = 0; Reg < NumSGPRs; ++Reg) {
     if (!CCInfo.isAllocated(AMDGPU::SGPR0 + Reg)) {
       return AMDGPU::SGPR0 + Reg;
     }
   }
   llvm_unreachable("Cannot allocate sgpr");
 }
 
-SITargetLowering::SITargetLowering(const TargetMachine &TM,
+SITargetLowering::SITargetLowering(const LLVMTargetMachine &TM,
                                    const SISubtarget &STI)
     : AMDGPUTargetLowering(TM, STI) {
   addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
   addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
 
   addRegisterClass(MVT::i32, &AMDGPU::SReg_32_XM0RegClass);
   addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass);
 

lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

AMDGPUAS getAMDGPUAS(Triple T) {
   else {
     AS.FLAT_ADDRESS     = 4;
     AS.PRIVATE_ADDRESS  = 0;
     AS.REGION_ADDRESS   = 5;
    }
   return AS;
 }
 
-AMDGPUAS getAMDGPUAS(const TargetMachine &M) {
+AMDGPUAS getAMDGPUAS(const LLVMTargetMachine &M) {
   return getAMDGPUAS(M.getTargetTriple());
 }
 
 AMDGPUAS getAMDGPUAS(const Module &M) {
   return getAMDGPUAS(Triple(M.getTargetTriple()));
 }
 } // namespace AMDGPU
 } // namespace llvm

lib/Target/ARM/ARMAsmPrinter.h

class LLVM_LIBRARY_VISIBILITY ARMAsmPrinter : public AsmPrinter {
   /// when all non-function globals are emitted.
   SmallPtrSet<const GlobalVariable*,2> PromotedGlobals;
   /// Set of globals in PromotedGlobals that we've emitted labels for.
   /// We need to emit labels even for promoted globals so that DWARF
   /// debug info can link properly.
   SmallPtrSet<const GlobalVariable*,2> EmittedPromotedGlobalLabels;
 
 public:
-  explicit ARMAsmPrinter(TargetMachine &TM,
+  explicit ARMAsmPrinter(LLVMTargetMachine &TM,
                          std::unique_ptr<MCStreamer> Streamer);
 
   StringRef getPassName() const override {
     return "ARM Assembly Printer";
   }
 
   void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O);
 

lib/Target/ARM/ARMAsmPrinter.cpp

 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Target/TargetMachine.h"
 #include <cctype>
 using namespace llvm;
 
 #define DEBUG_TYPE "asm-printer"
 
-ARMAsmPrinter::ARMAsmPrinter(TargetMachine &TM,
+ARMAsmPrinter::ARMAsmPrinter(LLVMTargetMachine &TM,
                              std::unique_ptr<MCStreamer> Streamer)
     : AsmPrinter(TM, std::move(Streamer)), AFI(nullptr), MCP(nullptr),
       InConstantPool(false), OptimizationGoals(-1) {}
 
 void ARMAsmPrinter::EmitFunctionBodyEnd() {
   // Make sure to terminate any constant pools that were at the end
   // of the function.
   if (!InConstantPool)

lib/Target/ARM/ARMISelLowering.h

 
 class ARMSubtarget;
 class DataLayout;
 class FastISel;
 class FunctionLoweringInfo;
 class GlobalValue;
 class InstrItineraryData;
 class Instruction;
+class LLVMTargetMachine;
 class MachineBasicBlock;
 class MachineInstr;
 class SelectionDAG;
 class TargetLibraryInfo;
-class TargetMachine;
 class TargetRegisterInfo;
 class VectorType;
 
   namespace ARMISD {
 
     // ARM Specific DAG Nodes
     enum NodeType : unsigned {
       // Start the numbering where the builtin ops and target ops leave off.
class VectorType;
 
   } // end namespace ARM
 
   //===--------------------------------------------------------------------===//
   //  ARMTargetLowering - ARM Implementation of the TargetLowering interface
 
   class ARMTargetLowering : public TargetLowering {
   public:
-    explicit ARMTargetLowering(const TargetMachine &TM,
+    explicit ARMTargetLowering(const LLVMTargetMachine &TM,
                                const ARMSubtarget &STI);
 
     unsigned getJumpTableEncoding() const override;
     bool useSoftFloat() const override;
 
     SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
 
     /// ReplaceNodeResults - Replace the results of node with an illegal result

lib/Target/ARM/ARMISelLowering.cpp

void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
   addTypeForNEON(VT, MVT::f64, MVT::v2i32);
 }
 
 void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
   addRegisterClass(VT, &ARM::DPairRegClass);
   addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
 }
 
-ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
+ARMTargetLowering::ARMTargetLowering(const LLVMTargetMachine &TM,
                                      const ARMSubtarget &STI)
     : TargetLowering(TM), Subtarget(&STI) {
   RegInfo = Subtarget->getRegisterInfo();
   Itins = Subtarget->getInstrItineraryData();
 
   setBooleanContents(ZeroOrOneBooleanContent);
   setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
 

lib/Target/ARM/ARMTargetObjectFile.cpp

 const MCExpr *ARMElfTargetObjectFile::
 getDebugThreadLocalSymbol(const MCSymbol *Sym) const {
   return MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_ARM_TLSLDO,
                                  getContext());
 }
 
 static bool isExecuteOnlyFunction(const GlobalObject *GO, SectionKind SK,
                                   const TargetMachine &TM) {
-  if (const Function *F = dyn_cast<Function>(GO))
-    if (TM.getSubtarget<ARMSubtarget>(*F).genExecuteOnly() && SK.isText())
+  if (const Function *F = dyn_cast<Function>(GO)) {
+    const ARMBaseTargetMachine &ARM_TM =
+      static_cast<const ARMBaseTargetMachine &>(TM);
+    if (ARM_TM.getSubtarget<ARMSubtarget>(*F).genExecuteOnly() && SK.isText())
       return true;
+  }
   return false;
 }
 
 MCSection *ARMElfTargetObjectFile::getExplicitSectionGlobal(
     const GlobalObject *GO, SectionKind SK, const TargetMachine &TM) const {
   // Set execute-only access for the explicit section
   if (isExecuteOnlyFunction(GO, SK, TM))
     SK = SectionKind::getExecuteOnly();

lib/Target/ARM/ARMTargetTransformInfo.cpp

 #include <utility>
 
 using namespace llvm;
 
 #define DEBUG_TYPE "armtti"
 
 bool ARMTTIImpl::areInlineCompatible(const Function *Caller,
                                      const Function *Callee) const {
-  const TargetMachine &TM = getTLI()->getTargetMachine();
+  const LLVMTargetMachine &TM = getTLI()->getTargetMachine();
   const FeatureBitset &CallerBits =
       TM.getSubtargetImpl(*Caller)->getFeatureBits();
   const FeatureBitset &CalleeBits =
       TM.getSubtargetImpl(*Callee)->getFeatureBits();
 
   // To inline a callee, all features not in the whitelist must match exactly.
   bool MatchExact = (CallerBits & ~InlineFeatureWhitelist) ==
                     (CalleeBits & ~InlineFeatureWhitelist);

lib/Target/BPF/BPFAsmPrinter.cpp

 #include "llvm/Support/raw_ostream.h"
 using namespace llvm;
 
 #define DEBUG_TYPE "asm-printer"
 
 namespace {
 class BPFAsmPrinter : public AsmPrinter {
 public:
-  explicit BPFAsmPrinter(TargetMachine &TM,
+  explicit BPFAsmPrinter(LLVMTargetMachine &TM,
                          std::unique_ptr<MCStreamer> Streamer)
       : AsmPrinter(TM, std::move(Streamer)) {}
 
   StringRef getPassName() const override { return "BPF Assembly Printer"; }
   void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O);
   bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                        unsigned AsmVariant, const char *ExtraCode,
                        raw_ostream &O) override;

lib/Target/BPF/BPFISelLowering.h

enum NodeType : unsigned {
   SELECT_CC,
   BR_CC,
   Wrapper
 };
 }
 
 class BPFTargetLowering : public TargetLowering {
 public:
-  explicit BPFTargetLowering(const TargetMachine &TM, const BPFSubtarget &STI);
+  explicit BPFTargetLowering(const LLVMTargetMachine &TM,
+                             const BPFSubtarget &STI);
 
   // Provide custom lowering hooks for some operations.
   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
 
   // This method returns the name of a target specific DAG node.
   const char *getTargetNodeName(unsigned Opcode) const override;
 
   // This method decides whether folding a constant offset

lib/Target/BPF/BPFISelLowering.cpp

static void fail(const SDLoc &DL, SelectionDAG &DAG, const char *Msg,
   raw_string_ostream OS(Str);
   OS << Msg;
   Val->print(OS);
   OS.flush();
   DAG.getContext()->diagnose(
       DiagnosticInfoUnsupported(*MF.getFunction(), Str, DL.getDebugLoc()));
 }
 
-BPFTargetLowering::BPFTargetLowering(const TargetMachine &TM,
+BPFTargetLowering::BPFTargetLowering(const LLVMTargetMachine &TM,
                                      const BPFSubtarget &STI)
     : TargetLowering(TM) {
 
   // Set up the register classes.
   addRegisterClass(MVT::i64, &BPF::GPRRegClass);
 
   // Compute derived properties from the register classes
   computeRegisterProperties(STI.getRegisterInfo());

lib/Target/BPF/BPFSubtarget.h

protected:
 
   // whether the cpu supports jmp ext
   bool HasJmpExt;
 
 public:
   // This constructor initializes the data members to match that
   // of the specified triple.
   BPFSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
-               const TargetMachine &TM);
+               const LLVMTargetMachine &TM);
 
   BPFSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
 
   // ParseSubtargetFeatures - Parses features string setting specified
   // subtarget options.  Definition of function is auto generated by tblgen.
   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
   bool getHasJmpExt() const { return HasJmpExt; }
 

lib/Target/BPF/BPFSubtarget.cpp

if (CPU == "generic" || CPU == "v1")
     return;
   if (CPU == "v2") {
     HasJmpExt = true;
     return;
   }
 }
 
 BPFSubtarget::BPFSubtarget(const Triple &TT, const std::string &CPU,
-                           const std::string &FS, const TargetMachine &TM)
+                           const std::string &FS, const LLVMTargetMachine &TM)
     : BPFGenSubtargetInfo(TT, CPU, FS), InstrInfo(),
       FrameLowering(initializeSubtargetDependencies(CPU, FS)),
       TLInfo(TM, *this) {}

lib/Target/Hexagon/HexagonAsmPrinter.h

 #include "llvm/CodeGen/MachineFunction.h"
 #include <memory>
 
 namespace llvm {
 
 class MachineInstr;
 class MCInst;
 class raw_ostream;
-class TargetMachine;
+class LLVMTargetMachine;
 
   class HexagonAsmPrinter : public AsmPrinter {
     const HexagonSubtarget *Subtarget = nullptr;
 
   public:
-    explicit HexagonAsmPrinter(TargetMachine &TM,
+    explicit HexagonAsmPrinter(LLVMTargetMachine &TM,
                                std::unique_ptr<MCStreamer> Streamer);
 
     bool runOnMachineFunction(MachineFunction &Fn) override {
       Subtarget = &Fn.getSubtarget<HexagonSubtarget>();
       return AsmPrinter::runOnMachineFunction(Fn);
     }
 
     StringRef getPassName() const override {

lib/Target/Hexagon/HexagonAsmPrinter.cpp

inline static unsigned getHexagonRegisterPair(unsigned Reg,
       const MCRegisterInfo *RI) {
   assert(Hexagon::IntRegsRegClass.contains(Reg));
   MCSuperRegIterator SR(Reg, RI, false);
   unsigned Pair = *SR;
   assert(Hexagon::DoubleRegsRegClass.contains(Pair));
   return Pair;
 }
 
-HexagonAsmPrinter::HexagonAsmPrinter(TargetMachine &TM,
+HexagonAsmPrinter::HexagonAsmPrinter(LLVMTargetMachine &TM,
                                      std::unique_ptr<MCStreamer> Streamer)
     : AsmPrinter(TM, std::move(Streamer)) {}
 
 void HexagonAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
                                      raw_ostream &O) {
   const MachineOperand &MO = MI->getOperand(OpNo);
 
   switch (MO.getType()) {

lib/Target/Hexagon/HexagonISelLowering.h

class HexagonTargetLowering : public TargetLowering {
     const HexagonTargetMachine &HTM;
     const HexagonSubtarget &Subtarget;
 
     bool CanReturnSmallStruct(const Function* CalleeFn, unsigned& RetSize)
         const;
     void promoteLdStType(MVT VT, MVT PromotedLdStVT);
 
   public:
-    explicit HexagonTargetLowering(const TargetMachine &TM,
+    explicit HexagonTargetLowering(const LLVMTargetMachine &TM,
                                    const HexagonSubtarget &ST);
 
     /// IsEligibleForTailCallOptimization - Check whether the call is eligible
     /// for tail call optimization. Targets which want to do tail call
     /// optimization should implement this function.
     bool IsEligibleForTailCallOptimization(SDValue Callee,
         CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet,
         bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs,

lib/Target/Hexagon/HexagonISelLowering.cpp

HexagonTargetLowering::LowerGlobalTLSAddress(SDValue Op,
   }
   llvm_unreachable("Bogus TLS model");
 }
 
 //===----------------------------------------------------------------------===//
 // TargetLowering Implementation
 //===----------------------------------------------------------------------===//
 
-HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
+HexagonTargetLowering::HexagonTargetLowering(const LLVMTargetMachine &TM,
                                              const HexagonSubtarget &ST)
     : TargetLowering(TM), HTM(static_cast<const HexagonTargetMachine&>(TM)),
       Subtarget(ST) {
   bool IsV4 = !Subtarget.hasV5TOps();
   auto &HRI = *Subtarget.getRegisterInfo();
   bool UseHVX = Subtarget.useHVXOps();
   bool UseHVXSgl = Subtarget.useHVXSglOps();
   bool UseHVXDbl = Subtarget.useHVXDblOps();

lib/Target/Hexagon/HexagonSubtarget.h

 #define GET_SUBTARGETINFO_HEADER
 #include "HexagonGenSubtargetInfo.inc"
 
 #define Hexagon_SMALL_DATA_THRESHOLD 8
 #define Hexagon_SLOTS 4
 
 namespace llvm {
 
+class LLVMTargetMachine;
 class MachineInstr;
 class SDep;
 class SUnit;
-class TargetMachine;
 class Triple;
 
 class HexagonSubtarget : public HexagonGenSubtargetInfo {
   virtual void anchor();
 
   bool UseMemOps, UseHVXOps, UseHVXDblOps;
   bool UseLongCalls;
   bool ModeIEEERndNear;
private:
   HexagonRegisterInfo RegInfo;
   HexagonTargetLowering TLInfo;
   HexagonSelectionDAGInfo TSInfo;
   HexagonFrameLowering FrameLowering;
   InstrItineraryData InstrItins;
 
 public:
   HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
-                   const TargetMachine &TM);
+                   const LLVMTargetMachine &TM);
 
   /// getInstrItins - Return the instruction itineraries based on subtarget
   /// selection.
   const InstrItineraryData *getInstrItineraryData() const override {
     return &InstrItins;
   }
   const HexagonInstrInfo *getInstrInfo() const override { return &InstrInfo; }
   const HexagonRegisterInfo *getRegisterInfo() const override {

lib/Target/Hexagon/HexagonSubtarget.cpp

static cl::opt<bool> SchedRetvalOptimization("sched-retval-optimization",
   cl::Hidden, cl::ZeroOrMore, cl::init(true));
 
 static cl::opt<bool> EnableCheckBankConflict("hexagon-check-bank-conflict",
   cl::Hidden, cl::ZeroOrMore, cl::init(true),
   cl::desc("Enable checking for cache bank conflicts"));
 
 
 HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU,
-                                   StringRef FS, const TargetMachine &TM)
+                                   StringRef FS, const LLVMTargetMachine &TM)
     : HexagonGenSubtargetInfo(TT, CPU, FS),
       CPUString(Hexagon_MC::selectHexagonCPU(TT, CPU)),
       InstrInfo(initializeSubtargetDependencies(CPU, FS)),
       RegInfo(getHwMode()), TLInfo(TM, *this),
       InstrItins(getInstrItineraryForCPU(CPUString)) {
   // Beware of the default constructor of InstrItineraryData: it will
   // reset all members to 0.
   assert(InstrItins.Itineraries != nullptr && "InstrItins not initialized");

lib/Target/Lanai/LanaiAsmPrinter.cpp

 
 #define DEBUG_TYPE "asm-printer"
 
 using namespace llvm;
 
 namespace {
 class LanaiAsmPrinter : public AsmPrinter {
 public:
-  explicit LanaiAsmPrinter(TargetMachine &TM,
+  explicit LanaiAsmPrinter(LLVMTargetMachine &TM,
                            std::unique_ptr<MCStreamer> Streamer)
       : AsmPrinter(TM, std::move(Streamer)) {}
 
   StringRef getPassName() const override { return "Lanai Assembly Printer"; }
 
   void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O);
   bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                        unsigned AsmVariant, const char *ExtraCode,

lib/Target/Lanai/LanaiISelLowering.h

enum {
   SMALL
 };
 } // namespace LanaiISD
 
 class LanaiSubtarget;
 
 class LanaiTargetLowering : public TargetLowering {
 public:
-  LanaiTargetLowering(const TargetMachine &TM, const LanaiSubtarget &STI);
+  LanaiTargetLowering(const LLVMTargetMachine &TM, const LanaiSubtarget &STI);
 
   // LowerOperation - Provide custom lowering hooks for some operations.
   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
 
   // getTargetNodeName - This method returns the name of a target specific
   // DAG node.
   const char *getTargetNodeName(unsigned Opcode) const override;
 

lib/Target/Lanai/LanaiISelLowering.cpp

 // at call site). Until we can inline mulsi3, generating at most 14 instructions
 // will be faster than invoking mulsi3.
 static cl::opt<int> LanaiLowerConstantMulThreshold(
     "lanai-constant-mul-threshold", cl::Hidden,
     cl::desc("Maximum number of instruction to generate when lowering constant "
              "multiplication instead of calling library function [default=14]"),
     cl::init(14));
 
-LanaiTargetLowering::LanaiTargetLowering(const TargetMachine &TM,
+LanaiTargetLowering::LanaiTargetLowering(const LLVMTargetMachine &TM,
                                          const LanaiSubtarget &STI)
     : TargetLowering(TM) {
   // Set up the register classes.
   addRegisterClass(MVT::i32, &Lanai::GPRRegClass);
 
   // Compute derived properties from the register classes
   TRI = STI.getRegisterInfo();
   computeRegisterProperties(TRI);

lib/Target/Lanai/LanaiSubtarget.h

 
 namespace llvm {
 
 class LanaiSubtarget : public LanaiGenSubtargetInfo {
 public:
   // This constructor initializes the data members to match that
   // of the specified triple.
   LanaiSubtarget(const Triple &TargetTriple, StringRef Cpu,
-                 StringRef FeatureString, const TargetMachine &TM,
+                 StringRef FeatureString, const LLVMTargetMachine &TM,
                  const TargetOptions &Options, CodeModel::Model CodeModel,
                  CodeGenOpt::Level OptLevel);
 
   // ParseSubtargetFeatures - Parses features string setting specified
   // subtarget options.  Definition of function is auto generated by tblgen.
   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
 
   LanaiSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);

lib/Target/Lanai/LanaiSubtarget.cpp

 
 LanaiSubtarget &LanaiSubtarget::initializeSubtargetDependencies(StringRef CPU,
                                                                 StringRef FS) {
   initSubtargetFeatures(CPU, FS);
   return *this;
 }
 
 LanaiSubtarget::LanaiSubtarget(const Triple &TargetTriple, StringRef Cpu,
-                               StringRef FeatureString, const TargetMachine &TM,
+                               StringRef FeatureString,
+                               const LLVMTargetMachine &TM,
                                const TargetOptions & /*Options*/,
                                CodeModel::Model /*CodeModel*/,
                                CodeGenOpt::Level /*OptLevel*/)
     : LanaiGenSubtargetInfo(TargetTriple, Cpu, FeatureString),
       FrameLowering(initializeSubtargetDependencies(Cpu, FeatureString)),
       InstrInfo(), TLInfo(TM, *this), TSInfo() {}

lib/Target/MSP430/MSP430AsmPrinter.cpp

 #include "llvm/Support/raw_ostream.h"
 using namespace llvm;
 
 #define DEBUG_TYPE "asm-printer"
 
 namespace {
   class MSP430AsmPrinter : public AsmPrinter {
   public:
-    MSP430AsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer)
+    MSP430AsmPrinter(LLVMTargetMachine &TM,
+                     std::unique_ptr<MCStreamer> Streamer)
         : AsmPrinter(TM, std::move(Streamer)) {}
 
     StringRef getPassName() const override { return "MSP430 Assembly Printer"; }
 
     void printOperand(const MachineInstr *MI, int OpNum,
                       raw_ostream &O, const char* Modifier = nullptr);
     void printSrcMemOperand(const MachineInstr *MI, int OpNum,
                             raw_ostream &O);

lib/Target/MSP430/MSP430ISelLowering.h

enum NodeType : unsigned {
       /// SHL, SRA, SRL - Non-constant shifts.
       SHL, SRA, SRL
     };
   }
 
   class MSP430Subtarget;
   class MSP430TargetLowering : public TargetLowering {
   public:
-    explicit MSP430TargetLowering(const TargetMachine &TM,
+    explicit MSP430TargetLowering(const LLVMTargetMachine &TM,
                                   const MSP430Subtarget &STI);
 
     MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
       return MVT::i8;
     }
 
     /// LowerOperation - Provide custom lowering hooks for some operations.
     SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;

lib/Target/MSP430/MSP430ISelLowering.cpp

 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/raw_ostream.h"
 using namespace llvm;
 
 #define DEBUG_TYPE "msp430-lower"
 
-MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM,
+MSP430TargetLowering::MSP430TargetLowering(const LLVMTargetMachine &TM,
                                            const MSP430Subtarget &STI)
     : TargetLowering(TM) {
 
   // Set up the register classes.
   addRegisterClass(MVT::i8,  &MSP430::GR8RegClass);
   addRegisterClass(MVT::i16, &MSP430::GR16RegClass);
 
   // Compute derived properties from the register classes

lib/Target/MSP430/MSP430Subtarget.h

private:
   MSP430TargetLowering TLInfo;
   SelectionDAGTargetInfo TSInfo;
 
 public:
   /// This constructor initializes the data members to match that
   /// of the specified triple.
   ///
   MSP430Subtarget(const Triple &TT, const std::string &CPU,
-                  const std::string &FS, const TargetMachine &TM);
+                  const std::string &FS, const LLVMTargetMachine &TM);
 
   MSP430Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
 
   /// ParseSubtargetFeatures - Parses features string setting specified
   /// subtarget options.  Definition of function is auto generated by tblgen.
   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
 
   bool hasHWMult16() const { return HWMultMode == HWMult16; }

lib/Target/MSP430/MSP430Subtarget.cpp

MSP430Subtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
 
   if (HWMultModeOption != NoHWMult)
     HWMultMode = HWMultModeOption;
 
   return *this;
 }
 
 MSP430Subtarget::MSP430Subtarget(const Triple &TT, const std::string &CPU,
-                                 const std::string &FS, const TargetMachine &TM)
+                                 const std::string &FS,
+                                 const LLVMTargetMachine &TM)
     : MSP430GenSubtargetInfo(TT, CPU, FS), FrameLowering(),
       InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this) {}

lib/Target/Mips/MipsAsmPrinter.h

private:
 
   bool isLongBranchPseudo(int Opcode) const;
 
 public:
   const MipsSubtarget *Subtarget;
   const MipsFunctionInfo *MipsFI;
   MipsMCInstLower MCInstLowering;
 
-  explicit MipsAsmPrinter(TargetMachine &TM,
+  explicit MipsAsmPrinter(LLVMTargetMachine &TM,
                           std::unique_ptr<MCStreamer> Streamer)
       : AsmPrinter(TM, std::move(Streamer)), MCInstLowering(*this) {}
 
   StringRef getPassName() const override { return "Mips Assembly Printer"; }
 
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   void EmitConstantPool() override {

lib/Target/NVPTX/NVPTXAsmPrinter.h

private:
   // we have difficulty representing the difference in the NVVM IR.
   //
   // Since the address value should always be generic in CUDA C and always
   // be specific in OpenCL, we use this simple control here.
   //
   bool EmitGeneric;
 
 public:
-  NVPTXAsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer)
+  NVPTXAsmPrinter(LLVMTargetMachine &TM, std::unique_ptr<MCStreamer> Streamer)
       : AsmPrinter(TM, std::move(Streamer)),
         EmitGeneric(static_cast<NVPTXTargetMachine &>(TM).getDrvInterface() ==
                     NVPTX::CUDA) {}
 
   ~NVPTXAsmPrinter() override {
     delete reader;
   }
 

lib/Target/NVPTX/NVPTXAsmPrinter.cpp

if (MCID.TSFlags & NVPTXII::IsTexFlag) {
     return false;
   }
 
   return false;
 }
 
 void NVPTXAsmPrinter::lowerImageHandleSymbol(unsigned Index, MCOperand &MCOp) {
   // Ewwww
-  TargetMachine &TM = const_cast<TargetMachine&>(MF->getTarget());
+  LLVMTargetMachine &TM = const_cast<LLVMTargetMachine&>(MF->getTarget());
   NVPTXTargetMachine &nvTM = static_cast<NVPTXTargetMachine&>(TM);
   const NVPTXMachineFunctionInfo *MFI = MF->getInfo<NVPTXMachineFunctionInfo>();
   const char *Sym = MFI->getImageHandleSymbol(Index);
   std::string *SymNamePtr =
     nvTM.getManagedStrPool()->getManagedString(Sym);
   MCOp = GetSymbolRef(OutContext.getOrCreateSymbol(StringRef(*SymNamePtr)));
 }
 

lib/Target/PowerPC/PPCAsmPrinter.cpp

 
 class PPCAsmPrinter : public AsmPrinter {
 protected:
   MapVector<MCSymbol *, MCSymbol *> TOC;
   const PPCSubtarget *Subtarget;
   StackMaps SM;
 
 public:
-  explicit PPCAsmPrinter(TargetMachine &TM,
+  explicit PPCAsmPrinter(LLVMTargetMachine &TM,
                          std::unique_ptr<MCStreamer> Streamer)
       : AsmPrinter(TM, std::move(Streamer)), SM(*this) {}
 
   StringRef getPassName() const override { return "PowerPC Assembly Printer"; }
 
   MCSymbol *lookUpOrCreateTOCEntry(MCSymbol *Sym);
 
   bool doInitialization(Module &M) override {
bool runOnMachineFunction(MachineFunction &MF) override {
       emitXRayTable();
       return Changed;
     }
   };
 
   /// PPCLinuxAsmPrinter - PowerPC assembly printer, customized for Linux
   class PPCLinuxAsmPrinter : public PPCAsmPrinter {
   public:
-    explicit PPCLinuxAsmPrinter(TargetMachine &TM,
+    explicit PPCLinuxAsmPrinter(LLVMTargetMachine &TM,
                                 std::unique_ptr<MCStreamer> Streamer)
         : PPCAsmPrinter(TM, std::move(Streamer)) {}
 
     StringRef getPassName() const override {
       return "Linux PPC Assembly Printer";
     }
 
     bool doFinalization(Module &M) override;
     void EmitStartOfAsmFile(Module &M) override;
 
     void EmitFunctionEntryLabel() override;
 
     void EmitFunctionBodyStart() override;
     void EmitFunctionBodyEnd() override;
     void EmitInstruction(const MachineInstr *MI) override;
   };
 
   /// PPCDarwinAsmPrinter - PowerPC assembly printer, customized for Darwin/Mac
   /// OS X
   class PPCDarwinAsmPrinter : public PPCAsmPrinter {
   public:
-    explicit PPCDarwinAsmPrinter(TargetMachine &TM,
+    explicit PPCDarwinAsmPrinter(LLVMTargetMachine &TM,
                                  std::unique_ptr<MCStreamer> Streamer)
         : PPCAsmPrinter(TM, std::move(Streamer)) {}
 
     StringRef getPassName() const override {
       return "Darwin PPC Assembly Printer";
     }
 
     bool doFinalization(Module &M) override;
bool PPCDarwinAsmPrinter::doFinalization(Module &M) {
   return AsmPrinter::doFinalization(M);
 }
 
 /// createPPCAsmPrinterPass - Returns a pass that prints the PPC assembly code
 /// for a MachineFunction to the given output stream, in a format that the
 /// Darwin assembler can deal with.
 ///
 static AsmPrinter *
-createPPCAsmPrinterPass(TargetMachine &tm,
+createPPCAsmPrinterPass(TargetMachine &TM,
                         std::unique_ptr<MCStreamer> &&Streamer) {
-  if (tm.getTargetTriple().isMacOSX())
-    return new PPCDarwinAsmPrinter(tm, std::move(Streamer));
-  return new PPCLinuxAsmPrinter(tm, std::move(Streamer));
+  LLVMTargetMachine &LLVMTM = static_cast<LLVMTargetMachine&>(TM);
+  if (LLVMTM.getTargetTriple().isMacOSX())
+    return new PPCDarwinAsmPrinter(LLVMTM, std::move(Streamer));
+  return new PPCLinuxAsmPrinter(LLVMTM, std::move(Streamer));
 }
 
 // Force static initialization.
 extern "C" void LLVMInitializePowerPCAsmPrinter() {
   TargetRegistry::RegisterAsmPrinter(getThePPC32Target(),
                                      createPPCAsmPrinterPass);
   TargetRegistry::RegisterAsmPrinter(getThePPC64Target(),
                                      createPPCAsmPrinterPass);
   TargetRegistry::RegisterAsmPrinter(getThePPC64LETarget(),
                                      createPPCAsmPrinterPass);
 }

lib/Target/Sparc/SparcAsmPrinter.cpp

 
 namespace {
   class SparcAsmPrinter : public AsmPrinter {
     SparcTargetStreamer &getTargetStreamer() {
       return static_cast<SparcTargetStreamer &>(
           *OutStreamer->getTargetStreamer());
     }
   public:
-    explicit SparcAsmPrinter(TargetMachine &TM,
+    explicit SparcAsmPrinter(LLVMTargetMachine &TM,
                              std::unique_ptr<MCStreamer> Streamer)
         : AsmPrinter(TM, std::move(Streamer)) {}
 
     StringRef getPassName() const override { return "Sparc Assembly Printer"; }
 
     void printOperand(const MachineInstr *MI, int opNum, raw_ostream &OS);
     void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &OS,
                          const char *Modifier = nullptr);

lib/Target/Sparc/SparcISelLowering.h

enum NodeType : unsigned {
       TLS_LD,
       TLS_CALL
     };
   }
 
   class SparcTargetLowering : public TargetLowering {
     const SparcSubtarget *Subtarget;
   public:
-    SparcTargetLowering(const TargetMachine &TM, const SparcSubtarget &STI);
+    SparcTargetLowering(const LLVMTargetMachine &TM, const SparcSubtarget &STI);
     SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
     
     bool useSoftFloat() const override;
     
     /// computeKnownBitsForTargetNode - Determine which of the bits specified
     /// in Mask are known to be either zero or one and return them in the
     /// KnownZero/KnownOne bitsets.
     void computeKnownBitsForTargetNode(const SDValue Op,

lib/Target/Sparc/SparcISelLowering.cpp

static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
   case ISD::SETUGE: return SPCC::FCC_UGE;
   case ISD::SETUO:  return SPCC::FCC_U;
   case ISD::SETO:   return SPCC::FCC_O;
   case ISD::SETONE: return SPCC::FCC_LG;
   case ISD::SETUEQ: return SPCC::FCC_UE;
   }
 }
 
-SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
+SparcTargetLowering::SparcTargetLowering(const LLVMTargetMachine &TM,
                                          const SparcSubtarget &STI)
     : TargetLowering(TM), Subtarget(&STI) {
   MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
 
   // Instructions which use registers as conditionals examine all the
   // bits (as does the pseudo SELECT_CC expansion). I don't think it
   // matters much whether it's ZeroOrOneBooleanContent, or
   // ZeroOrNegativeOneBooleanContent, so, arbitrarily choose the

lib/Target/Sparc/SparcSubtarget.h

class SparcSubtarget : public SparcGenSubtargetInfo {
 
   SparcInstrInfo InstrInfo;
   SparcTargetLowering TLInfo;
   SelectionDAGTargetInfo TSInfo;
   SparcFrameLowering FrameLowering;
 
 public:
   SparcSubtarget(const Triple &TT, const std::string &CPU,
-                 const std::string &FS, const TargetMachine &TM, bool is64bit);
+                 const std::string &FS, const LLVMTargetMachine &TM,
+                 bool is64bit);
 
   const SparcInstrInfo *getInstrInfo() const override { return &InstrInfo; }
   const TargetFrameLowering *getFrameLowering() const override {
     return &FrameLowering;
   }
   const SparcRegisterInfo *getRegisterInfo() const override {
     return &InstrInfo.getRegisterInfo();
   }

lib/Target/Sparc/SparcSubtarget.cpp

SparcSubtarget &SparcSubtarget::initializeSubtargetDependencies(StringRef CPU,
   // Popc is a v9-only instruction.
   if (!IsV9)
     UsePopc = false;
 
   return *this;
 }
 
 SparcSubtarget::SparcSubtarget(const Triple &TT, const std::string &CPU,
-                               const std::string &FS, const TargetMachine &TM,
-                               bool is64Bit)
+                               const std::string &FS,
+                               const LLVMTargetMachine &TM, bool is64Bit)
     : SparcGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT), Is64Bit(is64Bit),
       InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
       FrameLowering(*this) {}
 
 int SparcSubtarget::getAdjustedFrameSize(int frameSize) const {
 
   if (is64Bit()) {
     // All 64-bit stack frames must be 16-byte aligned, and must reserve space

lib/Target/SystemZ/SystemZAsmPrinter.h

 class MCStreamer;
 class MachineBasicBlock;
 class MachineInstr;
 class Module;
 class raw_ostream;
 
 class LLVM_LIBRARY_VISIBILITY SystemZAsmPrinter : public AsmPrinter {
 public:
-  SystemZAsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer)
+  SystemZAsmPrinter(LLVMTargetMachine &TM, std::unique_ptr<MCStreamer> Streamer)
       : AsmPrinter(TM, std::move(Streamer)) {}
 
   // Override AsmPrinter.
   StringRef getPassName() const override { return "SystemZ Assembly Printer"; }
   void EmitInstruction(const MachineInstr *MI) override;
   void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) override;
   bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                        unsigned AsmVariant, const char *ExtraCode,
                        raw_ostream &OS) override;
   bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
                              unsigned AsmVariant, const char *ExtraCode,
                              raw_ostream &OS) override;
 };
 } // end namespace llvm
 
 #endif

lib/Target/SystemZ/SystemZISelLowering.h

 };
 } // end namespace SystemZICMP
 
 class SystemZSubtarget;
 class SystemZTargetMachine;
 
 class SystemZTargetLowering : public TargetLowering {
 public:
-  explicit SystemZTargetLowering(const TargetMachine &TM,
+  explicit SystemZTargetLowering(const LLVMTargetMachine &TM,
                                  const SystemZSubtarget &STI);
 
   // Override TargetLowering.
   MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
     return MVT::i32;
   }
   MVT getVectorIdxTy(const DataLayout &DL) const override {
     // Only the lower 12 bits of an element index are used, so we don't

lib/Target/SystemZ/SystemZISelLowering.cpp

 // Return a version of MachineOperand that can be safely used before the
 // final use.
 static MachineOperand earlyUseOperand(MachineOperand Op) {
   if (Op.isReg())
     Op.setIsKill(false);
   return Op;
 }
 
-SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
+SystemZTargetLowering::SystemZTargetLowering(const LLVMTargetMachine &TM,
                                              const SystemZSubtarget &STI)
     : TargetLowering(TM), Subtarget(STI) {
   MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
 
   // Set up the register classes.
   if (Subtarget.hasHighWord())
     addRegisterClass(MVT::i32, &SystemZ::GRX32BitRegClass);
   else

lib/Target/SystemZ/SystemZSubtarget.h

private:
   SystemZTargetLowering TLInfo;
   SystemZSelectionDAGInfo TSInfo;
   SystemZFrameLowering FrameLowering;
 
   SystemZSubtarget &initializeSubtargetDependencies(StringRef CPU,
                                                     StringRef FS);
 public:
   SystemZSubtarget(const Triple &TT, const std::string &CPU,
-                   const std::string &FS, const TargetMachine &TM);
+                   const std::string &FS, const LLVMTargetMachine &TM);
 
   const TargetFrameLowering *getFrameLowering() const override {
     return &FrameLowering;
   }
   const SystemZInstrInfo *getInstrInfo() const override { return &InstrInfo; }
   const SystemZRegisterInfo *getRegisterInfo() const override {
     return &InstrInfo.getRegisterInfo();
   }

lib/Target/SystemZ/SystemZSubtarget.cpp

if (CPUName.empty())
     CPUName = "generic";
   // Parse features string.
   ParseSubtargetFeatures(CPUName, FS);
   return *this;
 }
 
 SystemZSubtarget::SystemZSubtarget(const Triple &TT, const std::string &CPU,
                                    const std::string &FS,
-                                   const TargetMachine &TM)
+                                   const LLVMTargetMachine &TM)
     : SystemZGenSubtargetInfo(TT, CPU, FS), HasDistinctOps(false),
       HasLoadStoreOnCond(false), HasHighWord(false), HasFPExtension(false),
       HasPopulationCount(false), HasMessageSecurityAssist3(false),
       HasMessageSecurityAssist4(false), HasResetReferenceBitsMultiple(false),
       HasFastSerialization(false), HasInterlockedAccess1(false),
       HasMiscellaneousExtensions(false),
       HasExecutionHint(false), HasLoadAndTrap(false),
       HasTransactionalExecution(false), HasProcessorAssist(false),

lib/Target/X86/X86AsmPrinter.h

class LLVM_LIBRARY_VISIBILITY X86AsmPrinter : public AsmPrinter {
 
   void LowerFENTRY_CALL(const MachineInstr &MI, X86MCInstLower &MCIL);
 
   // Helper function that emits the XRay sleds we've collected for a particular
   // function.
   void EmitXRayTable();
 
 public:
-  explicit X86AsmPrinter(TargetMachine &TM,
+  explicit X86AsmPrinter(LLVMTargetMachine &TM,
                          std::unique_ptr<MCStreamer> Streamer)
       : AsmPrinter(TM, std::move(Streamer)), SM(*this), FM(*this) {}
 
   StringRef getPassName() const override {
     return "X86 Assembly Printer";
   }
 
   const X86Subtarget &getSubtarget() const { return *Subtarget; }

lib/Target/X86/X86Subtarget.h

protected:
   };
 
   /// X86 processor family: Intel Atom, and others
   X86ProcFamilyEnum X86ProcFamily;
 
   /// Which PIC style to use
   PICStyles::Style PICStyle;
 
-  const TargetMachine &TM;
+  const LLVMTargetMachine &TM;
 
   /// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
   X86SSEEnum X86SSELevel;
 
   /// MMX, 3DNow, 3DNow Athlon, or none supported.
   X863DNowEnum X863DNowLevel;
 
   /// True if the processor supports X87 instructions.

lib/Target/X86/X86TargetTransformInfo.cpp

 
 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) {
   EVT VT = TLI->getValueType(DL, DataType);
   return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT);
 }
 
 bool X86TTIImpl::areInlineCompatible(const Function *Caller,
                                      const Function *Callee) const {
-  const TargetMachine &TM = getTLI()->getTargetMachine();
+  const LLVMTargetMachine &TM = getTLI()->getTargetMachine();
 
   // Work this as a subsetting of subtarget features.
   const FeatureBitset &CallerBits =
       TM.getSubtargetImpl(*Caller)->getFeatureBits();
   const FeatureBitset &CalleeBits =
       TM.getSubtargetImpl(*Callee)->getFeatureBits();
 
   // FIXME: This is likely too limiting as it will include subtarget features

lib/Target/XCore/XCoreAsmPrinter.cpp

 #define DEBUG_TYPE "asm-printer"
 
 namespace {
   class XCoreAsmPrinter : public AsmPrinter {
     XCoreMCInstLower MCInstLowering;
     XCoreTargetStreamer &getTargetStreamer();
 
   public:
-    explicit XCoreAsmPrinter(TargetMachine &TM,
+    explicit XCoreAsmPrinter(LLVMTargetMachine &TM,
                              std::unique_ptr<MCStreamer> Streamer)
         : AsmPrinter(TM, std::move(Streamer)), MCInstLowering(*this) {}
 
     StringRef getPassName() const override { return "XCore Assembly Printer"; }
 
     void printInlineJT(const MachineInstr *MI, int opNum, raw_ostream &O,
                        const std::string &directive = ".jmptable");
     void printInlineJT32(const MachineInstr *MI, int opNum, raw_ostream &O) {

lib/Target/XCore/XCoreISelLowering.h

namespace llvm {
   }
 
   //===--------------------------------------------------------------------===//
   // TargetLowering Implementation
   //===--------------------------------------------------------------------===//
   class XCoreTargetLowering : public TargetLowering
   {
   public:
-    explicit XCoreTargetLowering(const TargetMachine &TM,
+    explicit XCoreTargetLowering(const LLVMTargetMachine &TM,
                                  const XCoreSubtarget &Subtarget);
 
     using TargetLowering::isZExtFree;
     bool isZExtFree(SDValue Val, EVT VT2) const override;
 
 
     unsigned getJumpTableEncoding() const override;
     MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override {
public:
     /// If a physical register, this returns the register that receives the
     /// exception typeid on entry to a landing pad.
     unsigned
     getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
       return XCore::R1;
     }
 
   private:
-    const TargetMachine &TM;
+    const LLVMTargetMachine &TM;
     const XCoreSubtarget &Subtarget;
 
     // Lower Operand helpers
     SDValue LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv,
                               bool isVarArg,
                               const SmallVectorImpl<ISD::InputArg> &Ins,
                               const SDLoc &dl, SelectionDAG &DAG,
                               SmallVectorImpl<SDValue> &InVals) const;

lib/Target/XCore/XCoreISelLowering.cpp

switch ((XCoreISD::NodeType)Opcode)
     case XCoreISD::BR_JT32           : return "XCoreISD::BR_JT32";
     case XCoreISD::FRAME_TO_ARGS_OFFSET : return "XCoreISD::FRAME_TO_ARGS_OFFSET";
     case XCoreISD::EH_RETURN         : return "XCoreISD::EH_RETURN";
     case XCoreISD::MEMBARRIER        : return "XCoreISD::MEMBARRIER";
   }
   return nullptr;
 }
 
-XCoreTargetLowering::XCoreTargetLowering(const TargetMachine &TM,
+XCoreTargetLowering::XCoreTargetLowering(const LLVMTargetMachine &TM,
                                          const XCoreSubtarget &Subtarget)
     : TargetLowering(TM), TM(TM), Subtarget(Subtarget) {
 
   // Set up the register classes.
   addRegisterClass(MVT::i32, &XCore::GRRegsRegClass);
 
   // Compute derived properties from the register classes
   computeRegisterProperties(Subtarget.getRegisterInfo());

lib/Target/XCore/XCoreSubtarget.h

class XCoreSubtarget : public XCoreGenSubtargetInfo {
   XCoreTargetLowering TLInfo;
   XCoreSelectionDAGInfo TSInfo;
 
 public:
   /// This constructor initializes the data members to match that
   /// of the specified triple.
   ///
   XCoreSubtarget(const Triple &TT, const std::string &CPU,
-                 const std::string &FS, const TargetMachine &TM);
+                 const std::string &FS, const LLVMTargetMachine &TM);
 
   /// ParseSubtargetFeatures - Parses features string setting specified 
   /// subtarget options.  Definition of function is auto generated by tblgen.
   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
 
   const XCoreInstrInfo *getInstrInfo() const override { return &InstrInfo; }
   const XCoreFrameLowering *getFrameLowering() const override {
     return &FrameLowering;

lib/Target/XCore/XCoreSubtarget.cpp

 
 #define GET_SUBTARGETINFO_TARGET_DESC
 #define GET_SUBTARGETINFO_CTOR
 #include "XCoreGenSubtargetInfo.inc"
 
 void XCoreSubtarget::anchor() { }
 
 XCoreSubtarget::XCoreSubtarget(const Triple &TT, const std::string &CPU,
-                               const std::string &FS, const TargetMachine &TM)
+                               const std::string &FS,
+                               const LLVMTargetMachine &TM)
     : XCoreGenSubtargetInfo(TT, CPU, FS), InstrInfo(), FrameLowering(*this),
       TLInfo(TM, *this), TSInfo() {}

lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp

bool SeparateConstOffsetFromGEP::splitGEP(GetElementPtrInst *GEP) {
   // possible. GEPs with inbounds are more friendly to alias analysis.
   bool GEPWasInBounds = GEP->isInBounds();
   GEP->setIsInBounds(false);
 
   // Lowers a GEP to either GEPs with a single index or arithmetic operations.
   if (LowerGEP) {
     // As currently BasicAA does not analyze ptrtoint/inttoptr, do not lower to
     // arithmetic operations if the target uses alias analysis in codegen.
-    if (TM && TM->getSubtargetImpl(*GEP->getParent()->getParent())->useAA())
+    if (TM && TM->useAA(*GEP->getParent()->getParent()))
       lowerToSingleIndexGEPs(GEP, AccumulativeByteOffset);
     else
       lowerToArithmetics(GEP, AccumulativeByteOffset);
     return true;
   }
 
   // No need to create another GEP if the accumulative byte offset is 0.
   if (AccumulativeByteOffset == 0)

unittests/MI/LiveIntervalTest.cpp

void initLLVM() {
   PassRegistry *Registry = PassRegistry::getPassRegistry();
   initializeCore(*Registry);
   initializeCodeGen(*Registry);
 }
 
 /// Create a TargetMachine. As we lack a dedicated always available target for
 /// unittests, we go for "AMDGPU" to be able to test normal and subregister
 /// liveranges.
-std::unique_ptr<TargetMachine> createTargetMachine() {
+std::unique_ptr<LLVMTargetMachine> createTargetMachine() {
   Triple TargetTriple("amdgcn--");
   std::string Error;
   const Target *T = TargetRegistry::lookupTarget("", TargetTriple, Error);
   if (!T)
     return nullptr;
 
   TargetOptions Options;
-  return std::unique_ptr<TargetMachine>(T->createTargetMachine(
-      "AMDGPU", "", "", Options, None, None, CodeGenOpt::Aggressive));
+  TargetMachine *TM = T->createTargetMachine("AMDGPU", "", "", Options, None,
+                                             None, CodeGenOpt::Aggressive);
+  return
+    std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine*>(TM));
 }
 
 std::unique_ptr<Module> parseMIR(LLVMContext &Context,
     legacy::PassManagerBase &PM, std::unique_ptr<MIRParser> &MIR,
-    const TargetMachine &TM, StringRef MIRCode, const char *FuncName) {
+    const LLVMTargetMachine &TM, StringRef MIRCode, const char *FuncName) {
   SMDiagnostic Diagnostic;
   std::unique_ptr<MemoryBuffer> MBuffer = MemoryBuffer::getMemBuffer(MIRCode);
   MIR = createMIRParser(std::move(MBuffer), Context);
   if (!MIR)
     return nullptr;
 
   std::unique_ptr<Module> M = MIR->parseIRModule();
   if (!M)
static void testHandleMove(MachineFunction &MF, LiveIntervals &LIS,
 
   MachineBasicBlock &MBB = *FromInstr.getParent();
   MBB.splice(ToInstr.getIterator(), &MBB, FromInstr.getIterator());
   LIS.handleMove(FromInstr, true);
 }
 
 static void liveIntervalTest(StringRef MIRFunc, LiveIntervalTest T) {
   LLVMContext Context;
-  std::unique_ptr<TargetMachine> TM = createTargetMachine();
+  std::unique_ptr<LLVMTargetMachine> TM = createTargetMachine();
   // This test is designed for the X86 backend; stop if it is not available.
   if (!TM)
     return;
 
   legacy::PassManager PM;
 
   SmallString<160> S;
   StringRef MIRString = (Twine(R"MIR(

unittests/Target/AArch64/InstSizes.cpp

 #include "AArch64Subtarget.h"
 #include "AArch64TargetMachine.h"
 #include "llvm/CodeGen/MIRParser/MIRParser.h"
 #include "llvm/CodeGen/MachineModuleInfo.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/TargetSelect.h"
 
 #include "gtest/gtest.h"
 
 using namespace llvm;
 
 namespace {
-std::unique_ptr<TargetMachine> createTargetMachine() {
+std::unique_ptr<LLVMTargetMachine> createTargetMachine() {
   auto TT(Triple::normalize("aarch64--"));
   std::string CPU("generic");
   std::string FS("");
 
   LLVMInitializeAArch64TargetInfo();
   LLVMInitializeAArch64Target();
   LLVMInitializeAArch64TargetMC();
 
   std::string Error;
   const Target *TheTarget = TargetRegistry::lookupTarget(TT, Error);
 
-  return std::unique_ptr<TargetMachine>(TheTarget->createTargetMachine(
-      TT, CPU, FS, TargetOptions(), None, None, CodeGenOpt::Default));
+  TargetMachine *TM = TheTarget->createTargetMachine(
+      TT, CPU, FS, TargetOptions(), None, None, CodeGenOpt::Default);
+  return
+    std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine*>(TM));
 }
 
-std::unique_ptr<AArch64InstrInfo> createInstrInfo(TargetMachine *TM) {
+std::unique_ptr<AArch64InstrInfo> createInstrInfo(LLVMTargetMachine *TM) {
   AArch64Subtarget ST(TM->getTargetTriple(), TM->getTargetCPU(),
                       TM->getTargetFeatureString(), *TM, /* isLittle */ false);
   return llvm::make_unique<AArch64InstrInfo>(ST);
 }
 
 /// The \p InputIRSnippet is only needed for things that can't be expressed in
 /// the \p InputMIRSnippet (global variables etc)
 /// TODO: Some of this might be useful for other architectures as well - extract
 ///       the platform-independent parts somewhere they can be reused.
 void runChecks(
-    TargetMachine *TM, AArch64InstrInfo *II, const StringRef InputIRSnippet,
+    LLVMTargetMachine *TM, AArch64InstrInfo *II, const StringRef InputIRSnippet,
     const StringRef InputMIRSnippet,
     std::function<void(AArch64InstrInfo &, MachineFunction &)> Checks) {
   LLVMContext Context;
 
   auto MIRString =
     "--- |\n"
     "  declare void @sizes()\n"
     + InputIRSnippet.str() +
void runChecks(
   auto &MF = MMI.getOrCreateMachineFunction(*F);
 
   Checks(*II, MF);
 }
 
 } // anonymous namespace
 
 TEST(InstSizes, STACKMAP) {
-  std::unique_ptr<TargetMachine> TM = createTargetMachine();
+  std::unique_ptr<LLVMTargetMachine> TM = createTargetMachine();
   ASSERT_TRUE(TM);
   std::unique_ptr<AArch64InstrInfo> II = createInstrInfo(TM.get());
 
   runChecks(TM.get(), II.get(), "", "    STACKMAP 0, 16\n"
                                     "    STACKMAP 1, 32\n",
             [](AArch64InstrInfo &II, MachineFunction &MF) {
               auto I = MF.begin()->begin();
               EXPECT_EQ(16u, II.getInstSizeInBytes(*I));
               ++I;
               EXPECT_EQ(32u, II.getInstSizeInBytes(*I));
             });
 }
 
 TEST(InstSizes, PATCHPOINT) {
-  std::unique_ptr<TargetMachine> TM = createTargetMachine();
+  std::unique_ptr<LLVMTargetMachine> TM = createTargetMachine();
   std::unique_ptr<AArch64InstrInfo> II = createInstrInfo(TM.get());
 
   runChecks(TM.get(), II.get(), "",
             "    PATCHPOINT 0, 16, 0, 0, 0, csr_aarch64_aapcs\n"
             "    PATCHPOINT 1, 32, 0, 0, 0, csr_aarch64_aapcs\n",
             [](AArch64InstrInfo &II, MachineFunction &MF) {
               auto I = MF.begin()->begin();
               EXPECT_EQ(16u, II.getInstSizeInBytes(*I));
               ++I;
               EXPECT_EQ(32u, II.getInstSizeInBytes(*I));
             });
 }
 
 TEST(InstSizes, TLSDESC_CALLSEQ) {
-  std::unique_ptr<TargetMachine> TM = createTargetMachine();
+  std::unique_ptr<LLVMTargetMachine> TM = createTargetMachine();
   std::unique_ptr<AArch64InstrInfo> II = createInstrInfo(TM.get());
 
   runChecks(
       TM.get(), II.get(),
       "  @ThreadLocalGlobal = external thread_local global i32, align 8\n",
       "    TLSDESC_CALLSEQ target-flags(aarch64-tls) @ThreadLocalGlobal\n",
       [](AArch64InstrInfo &II, MachineFunction &MF) {
         auto I = MF.begin()->begin();
         EXPECT_EQ(16u, II.getInstSizeInBytes(*I));
       });
 }