[XRay] support conditional return on PPC.

[timshen]

Summary

Conditional returns were not taken into consideration at all. Implement them by turning them into jumps and normal returns. This means there is a slightly higher performance penalty for conditional returns, but this is the best we can do, and it still disturbs little of the rest.

[dberris]

LGTM for the instrumentation pass side (with a couple of suggestions).

I'll let @echristo decide on the AsmPrinter and MCInstLower implementations.

llvm/lib/CodeGen/XRayInstrumentation.cpp

37

nit: Probably name this as InstrumentationOptions?

39

Please provide a default value here, say bool HandleTailCall = true;?

[timshen]

s/Option/InstrumentationOptions/

Also updated AsmPrinter, to print the original instruction if the opcode is not supported.

Also add isTerminator to PATCHABLE_RET, otherwise AsmPrinter may not print some of the jump labels.

[timshen]

Disable default ctor for InstrumentationOptions.

[timshen]

llvm/lib/CodeGen/XRayInstrumentation.cpp

37

Done.

39

I actually prefer not to, as the intention is to force the user to think about the choice to make. Providing default values make the user think less about the behaviors.

I disabled default constructor.

[timshen]

Format.

[dberris]

Still LGTM, with one last suggestion.

llvm/lib/CodeGen/XRayInstrumentation.cpp

202–205

Looking at this, I'm inclined to suggest that using an enum class for spelling out whether to handle tail calls might be more readable. Right now I have to see what the meaning of 'false' in the first position is. Something like:

prependRetWithPatchableExit(MF, TII, {InstrumentationOptions::TailCalls::IGNORE, InstrumentationOptions::Returns::HANDLE_ALL});

The enum class may or may not be nested in InstrumentationOptions, so I'll leave that up to you.

llvm/test/CodeGen/PowerPC/xray-ret-is-terminator.ll

4

nit: Opportunity here for "IllBeBack". 😛

[timshen]

Updated test.

llvm/lib/CodeGen/XRayInstrumentation.cpp

202–205

FYI designated initializer (http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2017/p0329r4.pdf) should be in C++20, so ultimately we'll have this:

prependRetWithPatchableExit(MF, TII, {.HandleTailCalls = false, .HandleAllReturns = true});

but not now. :)

As for your suggested solution, I feel like the callee side code will be much longer and confusing, so I'll keep it as is.

llvm/test/CodeGen/PowerPC/xray-ret-is-terminator.ll

4

GREAT CATCH! DONE! XD

[echristo]

Other than the readability issue, sgtm.

-eric

llvm/lib/CodeGen/XRayInstrumentation.cpp

45

How about an enum mask set?

202–205

Bools are pretty terrible and while I agree that designated initializers would be better, named constants are at least better than false, true.

llvm/include/llvm/Target/Target.td

def PATCHABLE_FUNCTION_ENTER : Instruction {
   let hasSideEffects = 0;
 }
 def PATCHABLE_RET : Instruction {
   let OutOperandList = (outs unknown:$dst);
   let InOperandList = (ins variable_ops);
   let AsmString = "# XRay Function Patchable RET.";
   let usesCustomInserter = 1;
   let hasSideEffects = 1;
+  let isTerminator = 1;
   let isReturn = 1;
 }
 def PATCHABLE_FUNCTION_EXIT : Instruction {
   let OutOperandList = (outs);
   let InOperandList = (ins);
   let AsmString = "# XRay Function Exit.";
   let usesCustomInserter = 1;
   let hasSideEffects = 0; // FIXME: is this correct?

llvm/lib/CodeGen/XRayInstrumentation.cpp

 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetSubtargetInfo.h"
 
 using namespace llvm;
 
 namespace {
 
+struct InstrumentationOptions {
+  // Whether to emit PATCHABLE_TAIL_CALL.
+  bool HandleTailcall;
+
+  // Whether to emit PATCHABLE_RET/PATCHABLE_FUNCTION_EXIT for all forms of
+  // return, e.g. conditional return.
+  bool HandleAllReturns;
+};
+
 struct XRayInstrumentation : public MachineFunctionPass {
   static char ID;
 
   XRayInstrumentation() : MachineFunctionPass(ID) {
     initializeXRayInstrumentationPass(*PassRegistry::getPassRegistry());
   }
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {

 private:
   // Replace the original RET instruction with the exit sled code ("patchable
   //   ret" pseudo-instruction), so that at runtime XRay can replace the sled
   //   with a code jumping to XRay trampoline, which calls the tracing handler
   //   and, in the end, issues the RET instruction.
   // This is the approach to go on CPUs which have a single RET instruction,
   //   like x86/x86_64.
   void replaceRetWithPatchableRet(MachineFunction &MF,
-                                  const TargetInstrInfo *TII);
+                                  const TargetInstrInfo *TII,
+                                  InstrumentationOptions);
 
   // Prepend the original return instruction with the exit sled code ("patchable
   //   function exit" pseudo-instruction), preserving the original return
   //   instruction just after the exit sled code.
   // This is the approach to go on CPUs which have multiple options for the
   //   return instruction, like ARM. For such CPUs we can't just jump into the
   //   XRay trampoline and issue a single return instruction there. We rather
   //   have to call the trampoline and return from it to the original return
   //   instruction of the function being instrumented.
   void prependRetWithPatchableExit(MachineFunction &MF,
-                                   const TargetInstrInfo *TII);
+                                   const TargetInstrInfo *TII,
+                                   InstrumentationOptions);
 };
 
 } // end anonymous namespace
 
 void XRayInstrumentation::replaceRetWithPatchableRet(
-    MachineFunction &MF, const TargetInstrInfo *TII) {
+    MachineFunction &MF, const TargetInstrInfo *TII,
+    InstrumentationOptions op) {
   // We look for *all* terminators and returns, then replace those with
   // PATCHABLE_RET instructions.
   SmallVector<MachineInstr *, 4> Terminators;
   for (auto &MBB : MF) {
     for (auto &T : MBB.terminators()) {
       unsigned Opc = 0;
-      if (T.isReturn() && T.getOpcode() == TII->getReturnOpcode()) {
+      if (T.isReturn() &&
+          (op.HandleAllReturns || T.getOpcode() == TII->getReturnOpcode())) {
         // Replace return instructions with:
         //   PATCHABLE_RET <Opcode>, <Operand>...
         Opc = TargetOpcode::PATCHABLE_RET;
       }
-      if (TII->isTailCall(T)) {
+      if (TII->isTailCall(T) && op.HandleTailcall) {
         // Treat the tail call as a return instruction, which has a
         // different-looking sled than the normal return case.
         Opc = TargetOpcode::PATCHABLE_TAIL_CALL;
       }
       if (Opc != 0) {
         auto MIB = BuildMI(MBB, T, T.getDebugLoc(), TII->get(Opc))
                        .addImm(T.getOpcode());
         for (auto &MO : T.operands())
           MIB.add(MO);
         Terminators.push_back(&T);
       }
     }
   }
 
   for (auto &I : Terminators)
     I->eraseFromParent();
 }
 
 void XRayInstrumentation::prependRetWithPatchableExit(
-    MachineFunction &MF, const TargetInstrInfo *TII) {
+    MachineFunction &MF, const TargetInstrInfo *TII,
+    InstrumentationOptions op) {
   for (auto &MBB : MF)
-    for (auto &T : MBB.terminators())
-      if (T.isReturn()) {
-        // Prepend the return instruction with PATCHABLE_FUNCTION_EXIT.
-        BuildMI(MBB, T, T.getDebugLoc(),
-                TII->get(TargetOpcode::PATCHABLE_FUNCTION_EXIT));
-      }
+    for (auto &T : MBB.terminators()) {
+      unsigned Opc = 0;
+      if (T.isReturn() &&
+          (op.HandleAllReturns || T.getOpcode() == TII->getReturnOpcode())) {
+        Opc = TargetOpcode::PATCHABLE_FUNCTION_EXIT;
+      }
+      if (TII->isTailCall(T) && op.HandleTailcall) {
+        Opc = TargetOpcode::PATCHABLE_TAIL_CALL;
+      }
+      if (Opc != 0) {
+        // Prepend the return instruction with PATCHABLE_FUNCTION_EXIT or
+        //   PATCHABLE_TAIL_CALL .
+        BuildMI(MBB, T, T.getDebugLoc(), TII->get(Opc));
+      }
 }
 
 bool XRayInstrumentation::runOnMachineFunction(MachineFunction &MF) {
   auto &F = *MF.getFunction();
   auto InstrAttr = F.getFnAttribute("function-instrument");
   bool AlwaysInstrument = !InstrAttr.hasAttribute(Attribute::None) &&
                           InstrAttr.isStringAttribute() &&
                           InstrAttr.getValueAsString() == "xray-always";
bool XRayInstrumentation::runOnMachineFunction(MachineFunction &MF) {
   // MachineFunction.
   BuildMI(FirstMBB, FirstMI, FirstMI.getDebugLoc(),
           TII->get(TargetOpcode::PATCHABLE_FUNCTION_ENTER));
 
   switch (MF.getTarget().getTargetTriple().getArch()) {
   case Triple::ArchType::arm:
   case Triple::ArchType::thumb:
   case Triple::ArchType::aarch64:
-  case Triple::ArchType::ppc64le:
   case Triple::ArchType::mips:
   case Triple::ArchType::mipsel:
   case Triple::ArchType::mips64:
-  case Triple::ArchType::mips64el:
+  case Triple::ArchType::mips64el: {
     // For the architectures which don't have a single return instruction
-    prependRetWithPatchableExit(MF, TII);
+    InstrumentationOptions op;
+    op.HandleTailcall = false;
+    op.HandleAllReturns = true;
+    prependRetWithPatchableExit(MF, TII, op);
+    break;
+  }
+  case Triple::ArchType::ppc64le: {
+    InstrumentationOptions op;
+    op.HandleTailcall = false;
+    op.HandleAllReturns = true;
+    replaceRetWithPatchableRet(MF, TII, op);
     break;
-  default:
+  }
+  default: {
     // For the architectures that have a single return instruction (such as
     //   RETQ on x86_64).
-    replaceRetWithPatchableRet(MF, TII);
+    InstrumentationOptions op;
+    op.HandleTailcall = true;
+    op.HandleAllReturns = false;
+    replaceRetWithPatchableRet(MF, TII, op);
     break;
   }
+  }
   return true;
 }
 
 char XRayInstrumentation::ID = 0;
 char &llvm::XRayInstrumentationID = XRayInstrumentation::ID;
 INITIALIZE_PASS_BEGIN(XRayInstrumentation, "xray-instrumentation",
                       "Insert XRay ops", false, false)
 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
 INITIALIZE_PASS_END(XRayInstrumentation, "xray-instrumentation",
                     "Insert XRay ops", false, false)

llvm/lib/Target/PowerPC/PPC.h

 // GCC #defines PPC on Linux but we use it as our namespace name
 #undef PPC
 
 namespace llvm {
   class PPCTargetMachine;
   class PassRegistry;
   class FunctionPass;
   class MachineInstr;
+  class MachineOperand;
   class AsmPrinter;
   class MCInst;
+  class MCOperand;
 
   FunctionPass *createPPCCTRLoops();
 #ifndef NDEBUG
   FunctionPass *createPPCCTRLoopsVerify();
 #endif
   FunctionPass *createPPCLoopPreIncPrepPass(PPCTargetMachine &TM);
   FunctionPass *createPPCTOCRegDepsPass();
   FunctionPass *createPPCEarlyReturnPass();
   FunctionPass *createPPCVSXCopyPass();
   FunctionPass *createPPCVSXFMAMutatePass();
   FunctionPass *createPPCVSXSwapRemovalPass();
   FunctionPass *createPPCMIPeepholePass();
   FunctionPass *createPPCBranchSelectionPass();
   FunctionPass *createPPCBranchCoalescingPass();
   FunctionPass *createPPCQPXLoadSplatPass();
   FunctionPass *createPPCISelDag(PPCTargetMachine &TM, CodeGenOpt::Level OL);
   FunctionPass *createPPCTLSDynamicCallPass();
   FunctionPass *createPPCBoolRetToIntPass();
   FunctionPass *createPPCExpandISELPass();
   void LowerPPCMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
                                     AsmPrinter &AP, bool isDarwin);
+  bool LowerPPCMachineOperandToMCOperand(const MachineOperand &MO,
+                                         MCOperand &OutMO, AsmPrinter &AP,
+                                         bool isDarwin);
 
   void initializePPCVSXFMAMutatePass(PassRegistry&);
   void initializePPCBoolRetToIntPass(PassRegistry&);
   void initializePPCExpandISELPass(PassRegistry &);
   void initializePPCTLSDynamicCallPass(PassRegistry &);
   extern char &PPCVSXFMAMutateID;
 
   namespace PPCII {

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

 // Documentation at http://developer.apple.com/documentation/DeveloperTools/
 // Reference/Assembler/ASMIntroduction/chapter_1_section_1.html
 //
 //===----------------------------------------------------------------------===//
 
 #include "InstPrinter/PPCInstPrinter.h"
 #include "MCTargetDesc/PPCMCExpr.h"
 #include "MCTargetDesc/PPCMCTargetDesc.h"
+#include "MCTargetDesc/PPCPredicates.h"
 #include "PPC.h"
 #include "PPCInstrInfo.h"
 #include "PPCMachineFunctionInfo.h"
 #include "PPCSubtarget.h"
 #include "PPCTargetMachine.h"
 #include "PPCTargetStreamer.h"
 #include "llvm/ADT/MapVector.h"
 #include "llvm/ADT/StringRef.h"
EmitToStreamer(*OutStreamer,
                        .addExpr(MCSymbolRefExpr::create(
                            OutContext.getOrCreateSymbol("__xray_FunctionEntry"),
                            OutContext)));
     EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::MTLR8).addReg(PPC::X0));
     OutStreamer->EmitLabel(EndOfSled);
     recordSled(BeginOfSled, *MI, SledKind::FUNCTION_ENTER);
     break;
   }
-  case TargetOpcode::PATCHABLE_FUNCTION_EXIT: {
+  case TargetOpcode::PATCHABLE_RET: {
+    unsigned RetOpcode = MI->getOperand(0).getImm();
+    MCInst RetInst;
+    RetInst.setOpcode(RetOpcode);
+    for (const auto &MO :
+         make_range(std::next(MI->operands_begin()), MI->operands_end())) {
+      MCOperand MCOp;
+      if (LowerPPCMachineOperandToMCOperand(MO, MCOp, *this, false))
+        RetInst.addOperand(MCOp);
+    }
+
+    bool IsConditional;
+    if (RetOpcode == PPC::BCCLR) {
+      IsConditional = true;
+    } else if (RetOpcode == PPC::TCRETURNdi8 || RetOpcode == PPC::TCRETURNri8 ||
+               RetOpcode == PPC::TCRETURNai8) {
+      break;
+    } else if (RetOpcode == PPC::BLR8 || RetOpcode == PPC::TAILB8) {
+      IsConditional = false;
+    } else {
+      EmitToStreamer(*OutStreamer, RetInst);
+      break;
+    }
+
+    MCSymbol *FallthroughLabel;
+    if (IsConditional) {
+      // Before:
+      //   bgtlr cr0
+      //
+      // After:
+      //   ble cr0, .end
       // .p2align 3
       // .begin:
-    //   b(lr)? # lis 0, FuncId[16..32]
+      //   blr    # lis 0, FuncId[16..32]
       //   nop    # li  0, FuncId[0..15]
       //   std 0, -8(1)
       //   mflr 0
       //   bl __xray_FunctionExit
       //   mtlr 0
+      //   blr
       // .end:
+      //
+      // Update compiler-rt/lib/xray/xray_powerpc64.cc accordingly when number
+      // of instructions change.
+      FallthroughLabel = OutContext.createTempSymbol();
+      EmitToStreamer(
+          *OutStreamer,
+          MCInstBuilder(PPC::BCC)
+              .addImm(PPC::InvertPredicate(
+                  static_cast<PPC::Predicate>(MI->getOperand(1).getImm())))
+              .addReg(MI->getOperand(2).getReg())
+              .addExpr(MCSymbolRefExpr::create(FallthroughLabel, OutContext)));
+      RetInst = MCInst();
+      RetInst.setOpcode(PPC::BLR8);
+    }
+    // .p2align 3
+    // .begin:
+    //   b(lr)? # lis 0, FuncId[16..32]
+    //   nop    # li  0, FuncId[0..15]
+    //   std 0, -8(1)
+    //   mflr 0
+    //   bl __xray_FunctionExit
+    //   mtlr 0
     //   b(lr)?
     //
     // Update compiler-rt/lib/xray/xray_powerpc64.cc accordingly when number
     // of instructions change.
-    const MachineInstr *Next = [&] {
-      MachineBasicBlock::const_iterator It(MI);
-      assert(It != MI->getParent()->end());
-      ++It;
-      assert(It->isReturn());
-      return &*It;
-    }();
     OutStreamer->EmitCodeAlignment(8);
     MCSymbol *BeginOfSled = OutContext.createTempSymbol();
     OutStreamer->EmitLabel(BeginOfSled);
-    MCInst TmpInst;
-    LowerPPCMachineInstrToMCInst(Next, TmpInst, *this, false);
-    EmitToStreamer(*OutStreamer, TmpInst);
+    EmitToStreamer(*OutStreamer, RetInst);
     EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::NOP));
     EmitToStreamer(
         *OutStreamer,
         MCInstBuilder(PPC::STD).addReg(PPC::X0).addImm(-8).addReg(PPC::X1));
     EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::MFLR8).addReg(PPC::X0));
     EmitToStreamer(*OutStreamer,
                    MCInstBuilder(PPC::BL8_NOP)
                        .addExpr(MCSymbolRefExpr::create(
                            OutContext.getOrCreateSymbol("__xray_FunctionExit"),
                            OutContext)));
     EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::MTLR8).addReg(PPC::X0));
+    EmitToStreamer(*OutStreamer, RetInst);
+    if (IsConditional)
+      OutStreamer->EmitLabel(FallthroughLabel);
     recordSled(BeginOfSled, *MI, SledKind::FUNCTION_EXIT);
     break;
   }
+  case TargetOpcode::PATCHABLE_FUNCTION_EXIT:
+    llvm_unreachable("PATCHABLE_FUNCTION_EXIT should never be emitted");
   case TargetOpcode::PATCHABLE_TAIL_CALL:
     // TODO: Define a trampoline `__xray_FunctionTailExit` and differentiate a
     // normal function exit from a tail exit.
-  case TargetOpcode::PATCHABLE_RET:
-    // PPC's tail call instruction, e.g. PPC::TCRETURNdi8, doesn't really
-    // lower to a PPC::B instruction. The PPC::B instruction is generated
-    // before it, and handled by the normal case.
-    llvm_unreachable("Tail call is handled in the normal case. See comments"
+    llvm_unreachable("Tail call is handled in the normal case. See comments "
                      "around this assert.");
   }
 }
 
 void PPCLinuxAsmPrinter::EmitStartOfAsmFile(Module &M) {
   if (static_cast<const PPCTargetMachine &>(TM).isELFv2ABI()) {
     PPCTargetStreamer *TS =
       static_cast<PPCTargetStreamer *>(OutStreamer->getTargetStreamer());

llvm/lib/Target/PowerPC/PPCMCInstLower.cpp

static MCOperand GetSymbolRef(const MachineOperand &MO, const MCSymbol *Symbol,
   return MCOperand::createExpr(Expr);
 }
 
 void llvm::LowerPPCMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
                                         AsmPrinter &AP, bool isDarwin) {
   OutMI.setOpcode(MI->getOpcode());
   
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
-    const MachineOperand &MO = MI->getOperand(i);
-    
     MCOperand MCOp;
-    switch (MO.getType()) {
-    default:
-      MI->print(errs());
-      llvm_unreachable("unknown operand type");
-    case MachineOperand::MO_Register:
-      assert(!MO.getSubReg() && "Subregs should be eliminated!");
-      assert(MO.getReg() > PPC::NoRegister &&
-             MO.getReg() < PPC::NUM_TARGET_REGS &&
-             "Invalid register for this target!");
-      MCOp = MCOperand::createReg(MO.getReg());
-      break;
-    case MachineOperand::MO_Immediate:
-      MCOp = MCOperand::createImm(MO.getImm());
-      break;
-    case MachineOperand::MO_MachineBasicBlock:
-      MCOp = MCOperand::createExpr(MCSymbolRefExpr::create(
-                                      MO.getMBB()->getSymbol(), AP.OutContext));
-      break;
-    case MachineOperand::MO_GlobalAddress:
-    case MachineOperand::MO_ExternalSymbol:
-      MCOp = GetSymbolRef(MO, GetSymbolFromOperand(MO, AP), AP, isDarwin);
-      break;
-    case MachineOperand::MO_JumpTableIndex:
-      MCOp = GetSymbolRef(MO, AP.GetJTISymbol(MO.getIndex()), AP, isDarwin);
-      break;
-    case MachineOperand::MO_ConstantPoolIndex:
-      MCOp = GetSymbolRef(MO, AP.GetCPISymbol(MO.getIndex()), AP, isDarwin);
-      break;
-    case MachineOperand::MO_BlockAddress:
-      MCOp = GetSymbolRef(MO,AP.GetBlockAddressSymbol(MO.getBlockAddress()),AP,
-                          isDarwin);
-      break;
-    case MachineOperand::MO_RegisterMask:
-      continue;
-    }
-    
-    OutMI.addOperand(MCOp);
+    if (LowerPPCMachineOperandToMCOperand(MI->getOperand(i), MCOp, AP,
+                                          isDarwin))
+      OutMI.addOperand(MCOp);
+  }
+}
+
+bool llvm::LowerPPCMachineOperandToMCOperand(const MachineOperand &MO,
+                                             MCOperand &OutMO, AsmPrinter &AP,
+                                             bool isDarwin) {
+    OutMO = MCOperand::createReg(MO.getReg());
+    return true;
+    OutMO = MCOperand::createImm(MO.getImm());
+    return true;
+    OutMO = MCOperand::createExpr(
+        MCSymbolRefExpr::create(MO.getMBB()->getSymbol(), AP.OutContext));
+    return true;
+    OutMO = GetSymbolRef(MO, GetSymbolFromOperand(MO, AP), AP, isDarwin);
+    return true;
+    OutMO = GetSymbolRef(MO, AP.GetJTISymbol(MO.getIndex()), AP, isDarwin);
+    return true;
+    OutMO = GetSymbolRef(MO, AP.GetCPISymbol(MO.getIndex()), AP, isDarwin);
+    return true;
+    OutMO = GetSymbolRef(MO, AP.GetBlockAddressSymbol(MO.getBlockAddress()), AP,
+    return true;
+    return false;
   }
 }

llvm/test/CodeGen/PowerPC/xray-conditional-return.ll

+; RUN: llc -filetype=asm -o - -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
+
+define void @Foo(i32 signext %a, i32 signext %b) #0 {
+; CHECK-LABEL: @Foo
+; CHECK:   cmpw [[CR:[0-9]+]]
+; CHECK-NEXT:   ble [[CR]], [[LABEL:\.[a-zA-Z0-9]+]]
+; CHECK-NEXT:   .p2align  3
+; CHECK-NEXT: {{\.[a-zA-Z0-9]+}}:
+; CHECK-NEXT:   blr
+; CHECK-NEXT:   nop
+; CHECK-NEXT:   std 0
+; CHECK-NEXT:   mflr 0
+; CHECK-NEXT:   bl __xray_FunctionExit
+; CHECK-NEXT:   nop
+; CHECK-NEXT:   mtlr 0
+; CHECK-NEXT:   blr
+; CHECK-NEXT: [[LABEL]]:
+entry:
+  %cmp = icmp sgt i32 %a, %b
+  br i1 %cmp, label %return, label %if.end
+
+; CHECK:      .p2align  3
+; CHECK-NEXT: {{\.[a-zA-Z0-9]+}}:
+; CHECK-NEXT:   blr
+; CHECK-NEXT:   nop
+; CHECK-NEXT:   std 0
+; CHECK-NEXT:   mflr 0
+; CHECK-NEXT:   bl __xray_FunctionExit
+; CHECK-NEXT:   nop
+; CHECK-NEXT:   mtlr 0
+; CHECK-NEXT:   blr
+if.end:
+  tail call void @Bar()
+  br label %return
+
+return:
+  ret void
+}
+
+define void @Foo2(i32 signext %a, i32 signext %b) #0 {
+; CHECK-LABEL: @Foo2
+; CHECK:   cmpw [[CR:[0-9]+]]
+; CHECK-NEXT:   bge [[CR]], [[LABEL:\.[a-zA-Z0-9]+]]
+; CHECK-NEXT:   .p2align  3
+; CHECK-NEXT: {{\.[a-zA-Z0-9]+}}:
+; CHECK-NEXT:   blr
+; CHECK-NEXT:   nop
+; CHECK-NEXT:   std 0
+; CHECK-NEXT:   mflr 0
+; CHECK-NEXT:   bl __xray_FunctionExit
+; CHECK-NEXT:   nop
+; CHECK-NEXT:   mtlr 0
+; CHECK-NEXT:   blr
+; CHECK-NEXT: [[LABEL]]:
+entry:
+  %cmp = icmp slt i32 %a, %b
+  br i1 %cmp, label %return, label %if.end
+
+; CHECK:      .p2align  3
+; CHECK-NEXT: {{\.[a-zA-Z0-9]+}}:
+; CHECK-NEXT:   blr
+; CHECK-NEXT:   nop
+; CHECK-NEXT:   std 0
+; CHECK-NEXT:   mflr 0
+; CHECK-NEXT:   bl __xray_FunctionExit
+; CHECK-NEXT:   nop
+; CHECK-NEXT:   mtlr 0
+; CHECK-NEXT:   blr
+if.end:
+  tail call void @Bar()
+  br label %return
+
+return:
+  ret void
+}
+
+declare void @Bar()
+
+attributes #0 = { "function-instrument"="xray-always" }

llvm/test/CodeGen/PowerPC/xray-ret-is-terminator.ll

+; RUN: llc -o - -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
+
+define void @RetIsTerminator() #0 {
+; CHECK-LABEL @RetIsTerminator
+; CHECK: beq {{[0-9]+}}, [[LABEL:\.[a-zA-Z0-9_]+]]
+; CHECK: bl __xray_FunctionExit
+; CHECK: [[LABEL]]:
+bb:
+  br i1 undef, label %bb1, label %bb8
+
+bb1:
+  %tmp = tail call i64 asm sideeffect "", "=&r,=*m,b,r,*m,~{cc}"(i64* nonnull undef, i64* nonnull undef, i64 1, i64* nonnull undef)
+  %tmp2 = icmp eq i64 %tmp, 0
+  br i1 %tmp2, label %bb3, label %bb8
+
+bb3:
+  %tmp4 = tail call i64 asm sideeffect "", "=&r,=*m,b,r,r,*m,~{cc}"(i64* undef, i64* undef, i64 0, i64 undef, i64* undef)
+  %tmp5 = icmp eq i64 0, %tmp4
+  br i1 %tmp5, label %bb6, label %bb3
+
+bb6:
+  br i1 undef, label %bb7, label %bb8
+
+bb7:
+  tail call void () undef()
+  ret void
+
+bb8:
+  ret void
+}
+
+attributes #0 = { "function-instrument"="xray-always" }