AMDGPU: Add tied operands to v_mad_mix{lo|hi}_f16

[arsenm]

Summary

These write to the low and high half of the destination
register and leave the other 16-bits unchanged. This is true
for most 16-bit instructions on gfx9, but we don't use that
now.

[rampitec]

LGTM

[arsenm]

r313812 (fixed to use !con)

lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands) {
   OptionalImmIndexMap OptionalIdx;
   cvtVOP3(Inst, Operands, OptionalIdx);
 }
 
 void AMDGPUAsmParser::cvtVOP3PImpl(MCInst &Inst,
                                    const OperandVector &Operands,
                                    bool IsPacked) {
   OptionalImmIndexMap OptIdx;
+  int Opc = Inst.getOpcode();
 
   cvtVOP3(Inst, Operands, OptIdx);
 
+  if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst_in) != -1) {
+    assert(!IsPacked);
+    Inst.addOperand(Inst.getOperand(0));
+  }
+
   // FIXME: This is messy. Parse the modifiers as if it was a normal VOP3
   // instruction, and then figure out where to actually put the modifiers
-  int Opc = Inst.getOpcode();
 
   addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSel);
 
   int OpSelHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel_hi);
   if (OpSelHiIdx != -1) {
     // TODO: Should we change the printing to match?
     int DefaultVal = IsPacked ? -1 : 0;
     addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSelHi,

lib/Target/AMDGPU/VOP3PInstructions.td

 
 class VOP3PInst<string OpName, VOPProfile P, SDPatternOperator node = null_frag> :
   VOP3P_Pseudo<OpName, P,
     !if(P.HasModifiers, getVOP3PModPat<P, node>.ret, getVOP3Pat<P, node>.ret)
 >;
 
 // Non-packed instructions that use the VOP3P encoding.
 // VOP3 neg/abs and VOP3P opsel/opsel_hi modifiers are allowed.
-class VOP3_VOP3PInst<string OpName, VOPProfile P, SDPatternOperator node = null_frag> :
+class VOP3_VOP3PInst<string OpName, VOPProfile P, bit UseTiedOutput = 0,
+                     SDPatternOperator node = null_frag> :
   VOP3P_Pseudo<OpName, P> {
   // These operands are only sort of f16 operands. Depending on
   // op_sel_hi, these may be interpreted as f32. The inline immediate
   // values are really f16 converted to f32, so we treat these as f16
   // operands.
   let InOperandList =
+    !if(UseTiedOutput,
       (ins
         FP16InputMods:$src0_modifiers, VCSrc_f16:$src0,
         FP16InputMods:$src1_modifiers, VCSrc_f16:$src1,
         FP16InputMods:$src2_modifiers, VCSrc_f16:$src2,
         clampmod:$clamp,
+        VGPR_32:$vdst_in,
         op_sel:$op_sel,
-      op_sel_hi:$op_sel_hi);
+        op_sel_hi:$op_sel_hi),
+      (ins
+        FP16InputMods:$src0_modifiers, VCSrc_f16:$src0,
+        FP16InputMods:$src1_modifiers, VCSrc_f16:$src1,
+        FP16InputMods:$src2_modifiers, VCSrc_f16:$src2,
+        clampmod:$clamp,
+        op_sel:$op_sel,
+        op_sel_hi:$op_sel_hi));
+
+  let Constraints = !if(UseTiedOutput, "$vdst = $vdst_in", "");
+  let DisableEncoding = !if(UseTiedOutput, "$vdst_in", "");
   let AsmOperands =
     " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$op_sel$op_sel_hi$clamp";
 }
 
 let isCommutable = 1 in {
 def V_PK_FMA_F16 : VOP3PInst<"v_pk_fma_f16", VOP3_Profile<VOP_V2F16_V2F16_V2F16_V2F16>, fma>;
 def V_PK_MAD_I16 : VOP3PInst<"v_pk_mad_i16", VOP3_Profile<VOP_V2I16_V2I16_V2I16_V2I16>>;
 def V_PK_MAD_U16 : VOP3PInst<"v_pk_mad_u16", VOP3_Profile<VOP_V2I16_V2I16_V2I16_V2I16>>;

 
 // These are VOP3a-like opcodes which accept no omod.
 // Size of src arguments (16/32) is controlled by op_sel.
 // For 16-bit src arguments their location (hi/lo) are controlled by op_sel_hi.
 let isCommutable = 1 in {
 def V_MAD_MIX_F32 : VOP3_VOP3PInst<"v_mad_mix_f32", VOP3_Profile<VOP_F32_F16_F16_F16, VOP3_OPSEL>>;
 
 // Clamp modifier is applied after conversion to f16.
-def V_MAD_MIXLO_F16 : VOP3_VOP3PInst<"v_mad_mixlo_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>>;
-def V_MAD_MIXHI_F16 : VOP3_VOP3PInst<"v_mad_mixhi_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>>;
+def V_MAD_MIXLO_F16 : VOP3_VOP3PInst<"v_mad_mixlo_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, 1>;
+def V_MAD_MIXHI_F16 : VOP3_VOP3PInst<"v_mad_mixhi_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, 1>;
 }
 
 let Predicates = [HasMadMix] in {
 
 def : Pat <
   (f16 (fpround (fmad (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_modifiers)),
                       (f32 (VOP3PMadMixMods f16:$src1, i32:$src1_modifiers)),
                       (f32 (VOP3PMadMixMods f16:$src2, i32:$src2_modifiers))))),
   (V_MAD_MIXLO_F16 $src0_modifiers, $src0,
                    $src1_modifiers, $src1,
                    $src2_modifiers, $src2,
-                   0)
+                   0,
+                   (i32 (IMPLICIT_DEF)))
 >;
 
 } // End Predicates = [HasMadMix]
 
 multiclass VOP3P_Real_vi<bits<10> op> {
   def _vi : VOP3P_Real<!cast<VOP3P_Pseudo>(NAME), SIEncodingFamily.VI>,
             VOP3Pe <op, !cast<VOP3P_Pseudo>(NAME).Pfl> {
     let AssemblerPredicates = [HasVOP3PInsts];