[ARM] Fix for indexed dot product instruction descriptions

[SjoerdMeijer]

Summary

The indexed dot product instructions only accept the lower 16 D-registers as
the indexed register, but we were e.g. incorrectly accepting:

vudot.u8 d16,d16,d18[0]

[rengolin]

The last ARMv8.2 manual I could find is from 31 March, but it says UDOT/SDOT will be documented later. Do you have an update on that?

It's really hard to review patches without official documentation out.

[SjoerdMeijer]

Hi, the full architecture specification is publicly available here:

https://developer.arm.com/products/architecture/a-profile/exploration-tools

which I also mentioned in the commit message of r310480, which introduced initial AArch64 assembler support.

Hope this helps.

[rengolin]

Interesting, the Aarch32 PDF doesn't have SDOT/UDOT, only the AArch64 one...

[rengolin]

Ignore me, that was VSDOT... :)

Where is the restriction that only the lower 16 registers are allowed? Can you test quad regs, too? Just to make it clear the lane issue.

[t.p.northover]

Where is the restriction that only the lower 16 registers are allowed? Can you test quad regs, too? Just to make it clear the lane issue.

It's in the pseudo-code:

integer m = UInt(Vm<3:0>);
integer index = UInt(M);

Normally that 'M' bit would be the high bit of Vm (as for Vd and Vn just above). Here it's used to encode the lane.

[SjoerdMeijer]

I was just replying, but yes, there are only 4 bits available to encode Vm, the other M bit is the index.

[rengolin]

In D37968#873710, @t.p.northover wrote:

It's in the pseudo-code:

D'oh! I was looking in the vector one.

LGTM. Thanks!

[SjoerdMeijer]

Thanks for checking!

llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

def VUDOTQ : N3Vnp<0b11000, 0b10, 0b1101, 0b1, 0b1,
                   N3RegFrm, IIC_VDOTPROD, "vudot", "u8", []>;
 def VSDOTQ : N3Vnp<0b11000, 0b10, 0b1101, 0b1, 0b0,
                   (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm),
                   N3RegFrm, IIC_VDOTPROD, "vsdot", "s8", []>;
 
 // Indexed dot product instructions:
 class DOTI<string opc, string dt, bit Q, bit U, RegisterClass Ty> :
   N3Vnp<0b11100, 0b10, 0b1101, Q, U,
-       (outs Ty:$Vd), (ins Ty:$Vn, DPR:$Vm, VectorIndex32:$lane),
+       (outs Ty:$Vd), (ins Ty:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
        N3RegFrm, IIC_VDOTPROD, opc, dt, []> {
   bit lane;
   let Inst{5} = lane;
   let AsmString = !strconcat(opc, ".", dt, "\t$Vd, $Vn, $Vm$lane");
 }
 
 def VUDOTDI : DOTI<"vudot", "u8", 0b0, 0b1, DPR>;
 def VSDOTDI : DOTI<"vsdot", "s8", 0b0, 0b0, DPR>;

llvm/trunk/test/MC/ARM/armv8.2a-dotprod-error.s

 // RUN: not llvm-mc -triple arm -mattr=+dotprod -show-encoding < %s 2> %t
 // RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
 // RUN: not llvm-mc -triple thumb -mattr=+dotprod -show-encoding < %s 2> %t
 // RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
 
+// Only indices 0 an 1 should be accepted:
+
 vudot.u8 d0, d1, d2[2]
 vsdot.s8 d0, d1, d2[2]
 vudot.u8 q0, q1, d4[2]
 vsdot.s8 q0, q1, d4[2]
 
 // CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: vudot.u8 d0, d1, d2[2]
+// CHECK-ERROR:                    ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: vsdot.s8 d0, d1, d2[2]
+// CHECK-ERROR:                    ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: vudot.u8 q0, q1, d4[2]
+// CHECK-ERROR:                    ^
 // CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: vsdot.s8 q0, q1, d4[2]
+// CHECK-ERROR:                    ^
+
+// Only the lower 16 D-registers should be accepted:
+
+vudot.u8 q0, q1, d16[0]
+vsdot.s8 q0, q1, d16[0]
+
 // CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: vudot.u8 q0, q1, d16[0]
+// CHECK-ERROR:                     ^
 // CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: vsdot.s8 q0, q1, d16[0]
+// CHECK-ERROR:                     ^