[mips] Correcting operand range for DINSM instruction

[abeserminji]

Summary

This patch corrects the definition of the DINSM instruction. Specification for DINSM instruction for Mips64 says that size operand should be 2 <= size <= 64, but it is defined as uimm5_inssize_plus1 which gives range of 1 .. 32.

[sdardis]

Can you add a test case along the lines of:

dinsm $4, $5, 31, 33

to test/MC/Mips/mips64r{2|6}/valid.s

I've noticed that the dext and dins family of instructions are not tested in those files.

[abeserminji]

Should I add tests for dext family of instructions to a new patch? Or is it ok to add them to this patch?

[sdardis]

Adding tests for the dext/dins family of instructions should be submitted as a separate patch. This patch just requires tests for dinsm.

[abeserminji]

Added test line for dinsm instruction to test/MC/Mips/mips64r{2|6}/valid.s

[sdardis]

LGTM with inline nit addressed.

test/MC/Mips/mips64r2/valid.s

109 ↗

(On Diff #114797)

This should be 34, as 32 is a valid operand for uimm5_inssize_plus1. 34 is not valid for uimm5_inssize_plus1 but is valid by the ISA description of the instruction.

test/MC/Mips/mips64r6/valid.s

117 ↗

(On Diff #114797)

See my previous comment.

[abeserminji]

Comment resolved.

llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td

def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5, uimm5_plus33, immZExt5,
                       immZExt5Plus33, MipsExt>, EXT_FM<1>, ISA_MIPS64R2;
   def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm5_plus32, uimm5_plus1,
                       immZExt5Plus32, immZExt5Plus1, MipsExt>, EXT_FM<2>,
                       ISA_MIPS64R2;
   def DINS : InsBase<"dins", GPR64Opnd, uimm6, uimm5_inssize_plus1, MipsIns>,
              EXT_FM<7>, ISA_MIPS64R2;
   def DINSU : InsBase<"dinsu", GPR64Opnd, uimm5_plus32, uimm5_inssize_plus1>,
               EXT_FM<6>, ISA_MIPS64R2;
-  def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5, uimm5_inssize_plus1>,
+  def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5, uimm_range_2_64>,
               EXT_FM<5>, ISA_MIPS64R2;
 }
 
 let isCodeGenOnly = 1, AdditionalPredicates = [NotInMicroMips] in {
   def DEXT64_32 : InstSE<(outs GPR64Opnd:$rt),
                          (ins GPR32Opnd:$rs, uimm5_report_uimm6:$pos,
                               uimm5_plus1:$size),
                          "dext $rt, $rs, $pos, $size", [], II_EXT, FrmR, "dext">,

llvm/trunk/test/MC/Mips/mips64r2/valid.s

a:
         daddu     $s3,$at,$ra
         daddu     $24,$2,18079         # CHECK: daddiu $24, $2, 18079  # encoding: [0x64,0x58,0x46,0x9f]
         daddu     $19,26943            # CHECK: daddiu $19, $19, 26943 # encoding: [0x66,0x73,0x69,0x3f]
         dclo      $s2,$a2              # CHECK: dclo $18, $6   # encoding: [0x70,0xd2,0x90,0x25]
         dclz      $s0,$25              # CHECK: dclz $16, $25  # encoding: [0x73,0x30,0x80,0x24]
         deret
         di        $s8                  # CHECK: di  $fp        # encoding: [0x41,0x7e,0x60,0x00]
         di                             # CHECK: di             # encoding: [0x41,0x60,0x60,0x00]
+        dinsm     $2,$3,4,34           # CHECK: dinsm $2, $3, 4, 34    # encoding: [0x7c,0x62,0x29,0x05]
         ddiv      $zero,$k0,$s3
         ddivu     $zero,$s0,$s1
         div       $zero,$25,$11
         div.d     $f29,$f20,$f27
         div.s     $f4,$f5,$f15
         divu      $zero,$25,$15
         dmfc0     $10,$16,2            # CHECK: dmfc0 $10, $16, 2           # encoding: [0x40,0x2a,0x80,0x02]
         dmfc1     $12,$f13

llvm/trunk/test/MC/Mips/mips64r6/valid.s

a:
         daui     $3, $2, 0x1234  # CHECK: daui $3, $2, 4660    # encoding: [0x74,0x43,0x12,0x34]
         dbitswap $4, $2          # CHECK: dbitswap $4, $2    # encoding: [0x7c,0x02,0x20,0x24]
         dclo    $s2,$a2          # CHECK: dclo $18, $6           # encoding: [0x00,0xc0,0x90,0x53]
         dclz    $s0,$25          # CHECK: dclz $16, $25          # encoding: [0x03,0x20,0x80,0x52]
         ddiv    $2,$3,$4         # CHECK: ddiv $2, $3, $4  # encoding: [0x00,0x64,0x10,0x9e]
         ddivu   $2,$3,$4         # CHECK: ddivu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9f]
         di                       # CHECK: di               # encoding: [0x41,0x60,0x60,0x00]
         di      $s8              # CHECK: di  $fp          # encoding: [0x41,0x7e,0x60,0x00]
+        dinsm   $2,$3,4,34       # CHECK: dinsm $2, $3, 4, 34    # encoding: [0x7c,0x62,0x29,0x05]
         div     $2,$3,$4         # CHECK: div $2, $3, $4   # encoding: [0x00,0x64,0x10,0x9a]
         divu    $2,$3,$4         # CHECK: divu $2, $3, $4  # encoding: [0x00,0x64,0x10,0x9b]
         dlsa    $2, $3, $4, 3    # CHECK: dlsa $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0x95]
         dmfc0   $10, $16, 2      # CHECK: dmfc0 $10, $16, 2  # encoding: [0x40,0x2a,0x80,0x02]
         dmod    $2,$3,$4         # CHECK: dmod $2, $3, $4  # encoding: [0x00,0x64,0x10,0xde]
         dmodu   $2,$3,$4         # CHECK: dmodu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdf]
         dmtc0   $4, $10, 0       # CHECK: dmtc0 $4, $10, 0 # encoding: [0x40,0xa4,0x50,0x00]
         dmuh    $2,$3,$4         # CHECK: dmuh $2, $3, $4  # encoding: [0x00,0x64,0x10,0xdc]