AMDGPU: Add ds_{read|write}_addtid_b32 definitions

[rampitec]

LGTM

[arsenm]

r312349

lib/Target/AMDGPU/AMDGPU.td

 
 def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
   AssemblerPredicate<"FeatureFlatGlobalInsts">;
 def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
   AssemblerPredicate<"FeatureFlatScratchInsts">;
 def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
   AssemblerPredicate<"FeatureGFX9Insts">;
 
+def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
+  AssemblerPredicate<"FeatureGFX9Insts">;
+
 def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarryInsts()">,
   AssemblerPredicate<"FeatureAddNoCarryInsts">;
 
 def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarryInsts()">,
   AssemblerPredicate<"!FeatureAddNoCarryInsts">;
 
 def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
   AssemblerPredicate<"Feature16BitInsts">;

lib/Target/AMDGPU/DSInstructions.td

 def DS_WRITE2_B32     : DS_1A2D_Off8_NORET<"ds_write2_b32">;
 def DS_WRITE2ST64_B32 : DS_1A2D_Off8_NORET<"ds_write2st64_b32">;
 
 let SubtargetPredicate = HasD16LoadStore in {
 def DS_WRITE_B8_D16_HI : DS_1A1D_NORET<"ds_write_b8_d16_hi">;
 def DS_WRITE_B16_D16_HI : DS_1A1D_NORET<"ds_write_b16_d16_hi">;
 }
 
+let SubtargetPredicate = HasDSAddTid in {
+def DS_WRITE_ADDTID_B32 : DS_1A1D_NORET<"ds_write_addtid_b32">;
+}
+
 }
 
 def DS_MSKOR_B32      : DS_1A2D_NORET<"ds_mskor_b32">;
 def DS_CMPST_B32      : DS_1A2D_NORET<"ds_cmpst_b32">;
 def DS_CMPST_F32      : DS_1A2D_NORET<"ds_cmpst_f32">;
 
 def DS_ADD_U64        : DS_1A1D_NORET<"ds_add_u64", VReg_64>;
 def DS_SUB_U64        : DS_1A1D_NORET<"ds_sub_u64", VReg_64>;

 let SubtargetPredicate = HasD16LoadStore in {
 def DS_READ_U8_D16 : DS_1A_RET<"ds_read_u8_d16">;
 def DS_READ_U8_D16_HI : DS_1A_RET<"ds_read_u8_d16_hi">;
 def DS_READ_I8_D16 : DS_1A_RET<"ds_read_i8_d16">;
 def DS_READ_I8_D16_HI : DS_1A_RET<"ds_read_i8_d16_hi">;
 def DS_READ_U16_D16 : DS_1A_RET<"ds_read_u16_d16">;
 def DS_READ_U16_D16_HI : DS_1A_RET<"ds_read_u16_d16_hi">;
 }
+
+let SubtargetPredicate = HasDSAddTid in {
+def DS_READ_ADDTID_B32 : DS_1A_RET<"ds_read_addtid_b32">;
+}
 }
 
 def DS_CONSUME       : DS_0A_RET<"ds_consume">;
 def DS_APPEND        : DS_0A_RET<"ds_append">;
 def DS_ORDERED_COUNT : DS_1A_RET_GDS<"ds_ordered_count">;
 
 //===----------------------------------------------------------------------===//
 // Instruction definitions for CI and newer.

 def DS_MAX_F32_vi         : DS_Real_vi<0x13, DS_MAX_F32>;
 def DS_NOP_vi             : DS_Real_vi<0x14, DS_NOP>;
 def DS_ADD_F32_vi         : DS_Real_vi<0x15, DS_ADD_F32>;
 def DS_GWS_INIT_vi        : DS_Real_vi<0x99, DS_GWS_INIT>;
 def DS_GWS_SEMA_V_vi      : DS_Real_vi<0x9a, DS_GWS_SEMA_V>;
 def DS_GWS_SEMA_BR_vi     : DS_Real_vi<0x9b, DS_GWS_SEMA_BR>;
 def DS_GWS_SEMA_P_vi      : DS_Real_vi<0x9c, DS_GWS_SEMA_P>;
 def DS_GWS_BARRIER_vi     : DS_Real_vi<0x9d, DS_GWS_BARRIER>;
+def DS_WRITE_ADDTID_B32_vi : DS_Real_vi<0x1d, DS_WRITE_ADDTID_B32>;
 def DS_WRITE_B8_vi        : DS_Real_vi<0x1e, DS_WRITE_B8>;
 def DS_WRITE_B16_vi       : DS_Real_vi<0x1f, DS_WRITE_B16>;
 def DS_ADD_RTN_U32_vi     : DS_Real_vi<0x20, DS_ADD_RTN_U32>;
 def DS_SUB_RTN_U32_vi     : DS_Real_vi<0x21, DS_SUB_RTN_U32>;
 def DS_RSUB_RTN_U32_vi    : DS_Real_vi<0x22, DS_RSUB_RTN_U32>;
 def DS_INC_RTN_U32_vi     : DS_Real_vi<0x23, DS_INC_RTN_U32>;
 def DS_DEC_RTN_U32_vi     : DS_Real_vi<0x24, DS_DEC_RTN_U32>;
 def DS_MIN_RTN_I32_vi     : DS_Real_vi<0x25, DS_MIN_RTN_I32>;

 def DS_ADD_RTN_F32_vi     : DS_Real_vi<0x35, DS_ADD_RTN_F32>;
 def DS_READ_B32_vi        : DS_Real_vi<0x36, DS_READ_B32>;
 def DS_READ2_B32_vi       : DS_Real_vi<0x37, DS_READ2_B32>;
 def DS_READ2ST64_B32_vi   : DS_Real_vi<0x38, DS_READ2ST64_B32>;
 def DS_READ_I8_vi         : DS_Real_vi<0x39, DS_READ_I8>;
 def DS_READ_U8_vi         : DS_Real_vi<0x3a, DS_READ_U8>;
 def DS_READ_I16_vi        : DS_Real_vi<0x3b, DS_READ_I16>;
 def DS_READ_U16_vi        : DS_Real_vi<0x3c, DS_READ_U16>;
+def DS_READ_ADDTID_B32_vi : DS_Real_vi<0xb6, DS_READ_ADDTID_B32>;
 def DS_CONSUME_vi         : DS_Real_vi<0xbd, DS_CONSUME>;
 def DS_APPEND_vi          : DS_Real_vi<0xbe, DS_APPEND>;
 def DS_ORDERED_COUNT_vi   : DS_Real_vi<0xbf, DS_ORDERED_COUNT>;
 def DS_SWIZZLE_B32_vi     : DS_Real_vi<0x3d, DS_SWIZZLE_B32>;
 def DS_PERMUTE_B32_vi     : DS_Real_vi<0x3e, DS_PERMUTE_B32>;
 def DS_BPERMUTE_B32_vi    : DS_Real_vi<0x3f, DS_BPERMUTE_B32>;
 
 def DS_ADD_U64_vi         : DS_Real_vi<0x40, DS_ADD_U64>;

test/MC/AMDGPU/ds-gfx9.s

 
 ds_write_b8_d16_hi v8, v2
 // VI-ERR: error: instruction not supported on this GPU
 // GFX9: ds_write_b8_d16_hi v8, v2       ; encoding: [0x00,0x00,0xa8,0xd8,0x08,0x02,0x00,0x00]
 
 ds_write_b16_d16_hi v8, v2
 // VI-ERR: error: instruction not supported on this GPU
 // GFX9: ds_write_b16_d16_hi v8, v2      ; encoding: [0x00,0x00,0xaa,0xd8,0x08,0x02,0x00,0x00]
+
+ds_write_addtid_b32 v8, v2
+// VI-ERR: error: instruction not supported on this GPU
+// GFX9: ds_write_addtid_b32 v8, v2      ; encoding: [0x00,0x00,0x3a,0xd8,0x08,0x02,0x00,0x00]
+
+ds_read_addtid_b32 v8, v2
+// VI-ERR: error: instruction not supported on this GPU
+// GFX9: ds_read_addtid_b32 v8, v2       ; encoding: [0x00,0x00,0x6c,0xd9,0x02,0x00,0x00,0x08]