[AArch64] Add FMOVH0: materialize 0 using zero register for f16 values

[SjoerdMeijer]

Summary

Instead of loading 0 from a constant pool, it's of course much better to materialize it using an fmov and the zero register.

Thanks to Ahmed Bougacha for the suggestion.

[olista01]

lib/Target/AArch64/AArch64AsmPrinter.cpp

504 ↗

(On Diff #112531)

This code path is not tested.

[SjoerdMeijer]

Added test case.

[olista01]

LGTM

llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.cpp

assert((NumBytes - EncodedBytes) % 4 == 0 &&
          "Invalid number of NOP bytes requested!");
   for (unsigned i = EncodedBytes; i < NumBytes; i += 4)
     EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
 }
 
 void AArch64AsmPrinter::EmitFMov0(const MachineInstr &MI) {
   unsigned DestReg = MI.getOperand(0).getReg();
   if (STI->hasZeroCycleZeroing()) {
-    // Convert S/D register to corresponding Q register
-    if (AArch64::S0 <= DestReg && DestReg <= AArch64::S31) {
+    // Convert H/S/D register to corresponding Q register
+    if (AArch64::H0 <= DestReg && DestReg <= AArch64::H31)
+      DestReg = AArch64::Q0 + (DestReg - AArch64::H0);
+    else if (AArch64::S0 <= DestReg && DestReg <= AArch64::S31)
       DestReg = AArch64::Q0 + (DestReg - AArch64::S0);
-    } else {
+    else {
       assert(AArch64::D0 <= DestReg && DestReg <= AArch64::D31);
       DestReg = AArch64::Q0 + (DestReg - AArch64::D0);
     }
     MCInst MOVI;
     MOVI.setOpcode(AArch64::MOVIv2d_ns);
     MOVI.addOperand(MCOperand::createReg(DestReg));
     MOVI.addOperand(MCOperand::createImm(0));
     EmitToStreamer(*OutStreamer, MOVI);
   } else {
     MCInst FMov;
     switch (MI.getOpcode()) {
     default: llvm_unreachable("Unexpected opcode");
+    case AArch64::FMOVH0:
+      FMov.setOpcode(AArch64::FMOVWHr);
+      FMov.addOperand(MCOperand::createReg(DestReg));
+      FMov.addOperand(MCOperand::createReg(AArch64::WZR));
+      break;
     case AArch64::FMOVS0:
       FMov.setOpcode(AArch64::FMOVWSr);
       FMov.addOperand(MCOperand::createReg(DestReg));
       FMov.addOperand(MCOperand::createReg(AArch64::WZR));
       break;
     case AArch64::FMOVD0:
       FMov.setOpcode(AArch64::FMOVXDr);
       FMov.addOperand(MCOperand::createReg(DestReg));
case AArch64::TLSDESC_CALLSEQ: {
     MCInst Blr;
     Blr.setOpcode(AArch64::BLR);
     Blr.addOperand(MCOperand::createReg(AArch64::X1));
     EmitToStreamer(*OutStreamer, Blr);
 
     return;
   }
 
+  case AArch64::FMOVH0:
   case AArch64::FMOVS0:
   case AArch64::FMOVD0:
     EmitFMov0(*MI);
     return;
 
   case TargetOpcode::STACKMAP:
     return LowerSTACKMAP(*OutStreamer, SM, *MI);
 

llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp

bool AArch64TargetLowering::isOffsetFoldingLegal(
   DEBUG(dbgs() << "AArch64 doesn't support folding offsets into global "
         "addresses\n");
   return false;
 }
 
 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
   // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases.
   // FIXME: We should be able to handle f128 as well with a clever lowering.
-  if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32)) {
+  if (Imm.isPosZero() && (VT == MVT::f16 || VT == MVT::f64 || VT == MVT::f32)) {
     DEBUG(dbgs() << "Legal fp imm: materialize 0 using the zero register\n");
     return true;
   }
 
   StringRef FPType;
   bool IsLegal = false;
+  SmallString<128> ImmStrVal;
+  Imm.toString(ImmStrVal);
 
   if (VT == MVT::f64) {
     FPType = "f64";
     IsLegal = AArch64_AM::getFP64Imm(Imm) != -1;
   } else if (VT == MVT::f32) {
     FPType = "f32";
     IsLegal = AArch64_AM::getFP32Imm(Imm) != -1;
   } else if (VT == MVT::f16 && Subtarget->hasFullFP16()) {
     FPType = "f16";
     IsLegal = AArch64_AM::getFP16Imm(Imm) != -1;
   }
 
   if (IsLegal) {
-    DEBUG(dbgs() << "Is legal " << FPType << " imm value: yes\n");
+    DEBUG(dbgs() << "Legal " << FPType << " imm value: " << ImmStrVal << "\n");
     return true;
   }
 
   if (!FPType.empty())
-    DEBUG(dbgs() << "Is legal " << FPType << " imm value: no\n");
+    DEBUG(dbgs() << "Illegal " << FPType << " imm value: " << ImmStrVal << "\n");
   else
-    DEBUG(dbgs() << "Is legal " << "fp imm: no, unsupported fp type\n");
+    DEBUG(dbgs() << "Illegal fp imm " << ImmStrVal << ": unsupported fp type\n");
 
   return false;
 }
 
 //===----------------------------------------------------------------------===//
 //                          AArch64 Optimization Hooks
 //===----------------------------------------------------------------------===//
 

llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp

bool AArch64InstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
   // ORRXri, it is as cheap as MOV
   case AArch64::MOVi32imm:
     return canBeExpandedToORR(MI, 32);
   case AArch64::MOVi64imm:
     return canBeExpandedToORR(MI, 64);
 
   // It is cheap to zero out registers if the subtarget has ZeroCycleZeroing
   // feature.
+  case AArch64::FMOVH0:
   case AArch64::FMOVS0:
   case AArch64::FMOVD0:
     return Subtarget.hasZeroCycleZeroing();
   case TargetOpcode::COPY:
     return (Subtarget.hasZeroCycleZeroing() &&
             (MI.getOperand(1).getReg() == AArch64::WZR ||
              MI.getOperand(1).getReg() == AArch64::XZR));
   }

llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td

 //===----------------------------------------------------------------------===//
 // Unscaled integer to floating point conversion instruction.
 //===----------------------------------------------------------------------===//
 
 defm FMOV : UnscaledConversion<"fmov">;
 
 // Add pseudo ops for FMOV 0 so we can mark them as isReMaterializable
 let isReMaterializable = 1, isCodeGenOnly = 1, isAsCheapAsAMove = 1 in {
+def FMOVH0 : Pseudo<(outs FPR16:$Rd), (ins), [(set f16:$Rd, (fpimm0))]>,
+    Sched<[WriteF]>;
 def FMOVS0 : Pseudo<(outs FPR32:$Rd), (ins), [(set f32:$Rd, (fpimm0))]>,
     Sched<[WriteF]>;
 def FMOVD0 : Pseudo<(outs FPR64:$Rd), (ins), [(set f64:$Rd, (fpimm0))]>,
     Sched<[WriteF]>;
 }
 // Similarly add aliases
 def : InstAlias<"fmov $Rd, #0.0", (FMOVWHr FPR16:$Rd, WZR), 0>,
     Requires<[HasFullFP16]>;

llvm/trunk/test/CodeGen/AArch64/f16-imm.ll

 ; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=+fullfp16 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ILLEGAL
+; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=+fullfp16,+zcz | FileCheck %s --check-prefix=CHECK-ZCZ
 ; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=-fullfp16 | FileCheck %s --check-prefix=CHECK-NOFP16 --check-prefix=CHECK-ILLEGAL
 
 define half @Const0() {
 entry:
   ret half 0xH0000
 }
-; CHECK-ILLEGAL:        .[[LBL0:LCPI0_[0-9]]]:
-; CHECK-ILLEGAL-NEXT:   .hword  0 // half 0
-; CHECK-ILLEGAL-LABEL:  Const0:
-; CHECK-ILLEGAL:        adrp x[[NUM:[0-9]+]], .[[LBL0]]
-; CHECK-ILLEGAL-NEXT:   ldr h0, [x[[NUM]], :lo12:.[[LBL0]]]
+; CHECK-DAG-ILLEGAL-LABEL:  Const0:
+; CHECK-DAG-ILLEGAL-NEXT:   fmov  h0, wzr
+; CHECK-DAG-ILLEGAL-NEXT:   ret
+
+; CHECK-ZCZ-LABEL:  Const0:
+; CHECK-ZCZ:        movi  v0.2d, #0000000000000000
+; CHECK-ZCZ-NEXT:   ret
 
 define half @Const1() {
 entry:
   ret half 0xH3C00
 }
 ; CHECK-DAG-LABEL: Const1:
 ; CHECK-DAG-NEXT:   fmov h0, #1.00000000
 ; CHECK-DAG-NEXT:   ret