[ARM] Add PostRAScheduling option

[samparker]

Summary

D35935 added an option for selecting the machine scheduler for ARM. This patch adds the option to allow also using the post ra scheduler, which brings the ARM backend inline with AArch64 targets. The SchedModel can also set 'PostRAScheduler', as the R52 does, so also query this property in the overridden function.

[fhahn]

I think this change makes sense and will be convenient when we move ARM codegen to the MachineScheduler. I just have a quick question about adding FeaturePostRAScheduler to some processors.

lib/Target/ARM/ARM.td

876 ↗

(On Diff #111642)

What's the reason for adding FeaturePostRAScheduler to some processors but not others?

It seems to be a nonfunctional change, because all changed processors seem to have FeatureThumb2, so enablePostRAScheduler would return true anyways.

[fhahn]

Please clarify the question about adding FeaturePostRAScheduler to some processors and maybe hold off a bit with committing, in case @t.p.northover has any comments

[samparker]

lib/Target/ARM/ARM.td

876 ↗

(On Diff #111642)

I've added them to the processors that my team is currently tracking the performance of. If we want to develop some downstream schedulers and use the machine scheduler, it easily allows us to use post RA as well. Even though this can be defined in the SchedModel, I wanted to keep some consistency with your previous patch and the approach of AArch64.

[fhahn]

Thanks for clarifying that! Sounds and looks good to me.

[MatzeB]

llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp

360–368

We now have 3 different ways in which the PostRA scheduler could be enabled on ARM:

• A subtarget feature.
• In the scheduling model.
• With the if (!useMachineSched) && (!Thumb || Thumb2) criterion.

I think just one of those options (preferably the first) would be enough.

[samparker]

Hi Matthias,

I agree that this would be nice, so I've had a play around it seems non-trivial to get a default configuration without breaking some tests. It is simple enough to predicate the PostRA scheduler on the availability of Thumb2 but this causes breakages for Swift. Do you know why we don't want to enable PostRA for MIScheduled arm cores? PostRA is used on almost all of the AArch64 cores along with the MIScheduler, so I'm wondering why the two approaches are different.

Thanks,
sam

[MatzeB]

In D36866#848488, @samparker wrote:

Hi Matthias,

I agree that this would be nice, so I've had a play around it seems non-trivial to get a default configuration without breaking some tests. It is simple enough to predicate the PostRA scheduler on the availability of Thumb2 but this causes breakages for Swift. Do you know why we don't want to enable PostRA for MIScheduled arm cores? PostRA is used on almost all of the AArch64 cores along with the MIScheduler, so I'm wondering why the two approaches are different.

• I would skip the check of the SchedModel; you should be able to set the subtarget feature on all CPUs using such a schedmodel instead.
• Similarily I thought it should be possible to check each CPU whether it uses the machine scheduler today or matches (!Thumb || Thumb2) and then add/remove the PostRA subtarget feature accordingly.
• AFAIK we disabled the post ra scheduler on Swift/Cyclone because the out of order execution hides instruction latencies in nearly all cases so spending time on the post-ra scheduler didn't seem like a good use of compiletime.

llvm/trunk/lib/Target/ARM/ARM.td

def FeatureNoNegativeImmediates
                                              "to their negated or complemented "
                                              "equivalent when the immediate does "
                                              "not fit in the encoding.">;
 
 // Use the MachineScheduler for instruction scheduling for the subtarget.
 def FeatureUseMISched: SubtargetFeature<"use-misched", "UseMISched", "true",
                                         "Use the MachineScheduler">;
 
+def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
+    "UsePostRAScheduler", "true", "Schedule again after register allocation">;
+
 //===----------------------------------------------------------------------===//
 // ARM architecture class
 //
 
 // A-series ISA
 def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass",
                                      "Is application profile ('A' series)">;
 
def : ProcessorModel<"cortex-r8",   CortexA8Model,      [ARMv7r,
                                                          FeatureMP,
                                                          FeatureSlowFPBrcc,
                                                          FeatureHWDivARM,
                                                          FeatureHasSlowFPVMLx,
                                                          FeatureAvoidPartialCPSR]>;
 
 def : ProcessorModel<"cortex-m3", CortexM3Model,        [ARMv7m,
                                                          ProcM3,
-                                                         FeatureHasNoBranchPredictor]>;
+                                                         FeatureHasNoBranchPredictor,
+                                                         FeaturePostRAScheduler]>;
 
 def : ProcessorModel<"sc300",     CortexM3Model,        [ARMv7m,
                                                          ProcM3,
                                                          FeatureHasNoBranchPredictor]>;
 
 def : ProcessorModel<"cortex-m4", CortexM3Model,        [ARMv7em,
                                                          FeatureVFP4,
                                                          FeatureVFPOnlySP,
                                                          FeatureD16,
-                                                         FeatureHasNoBranchPredictor]>;
+                                                         FeatureHasNoBranchPredictor,
+                                                         FeaturePostRAScheduler]>;
 
 def : ProcNoItin<"cortex-m7",                           [ARMv7em,
                                                          FeatureFPARMv8,
-                                                         FeatureD16]>;
+                                                         FeatureD16,
+                                                         FeaturePostRAScheduler]>;
 
 def : ProcNoItin<"cortex-m23",                          [ARMv8mBaseline,
                                                          FeatureNoMovt]>;
 
 def : ProcessorModel<"cortex-m33", CortexM3Model,       [ARMv8mMainline,
                                                          FeatureDSP,
                                                          FeatureFPARMv8,
                                                          FeatureD16,
                                                          FeatureVFPOnlySP,
-                                                         FeatureHasNoBranchPredictor]>;
+                                                         FeatureHasNoBranchPredictor,
+                                                         FeaturePostRAScheduler]>;
 
 def : ProcNoItin<"cortex-a32",                           [ARMv8a,
                                                          FeatureHWDivThumb,
                                                          FeatureHWDivARM,
                                                          FeatureCrypto,
                                                          FeatureCRC]>;
 
 def : ProcNoItin<"cortex-a35",                          [ARMv8a, ProcA35,

llvm/trunk/lib/Target/ARM/ARMSubtarget.h

protected:
   bool InThumbMode = false;
 
   /// UseSoftFloat - True if we're using software floating point features.
   bool UseSoftFloat = false;
 
   /// UseMISched - True if MachineScheduler should be used for this subtarget.
   bool UseMISched = false;
 
+  /// UsePostRAScheduler - True if scheduling should happen again after
+  /// register allocation.
+  bool UsePostRAScheduler = false;
+
   /// HasThumb2 - True if Thumb2 instructions are supported.
   bool HasThumb2 = false;
 
   /// NoARM - True if subtarget does not support ARM mode execution.
   bool NoARM = false;
 
   /// ReserveR9 - True if R9 is not available as a general purpose register.
   bool ReserveR9 = false;
public:
   bool isAPCS_ABI() const;
   bool isAAPCS_ABI() const;
   bool isAAPCS16_ABI() const;
 
   bool isROPI() const;
   bool isRWPI() const;
 
   bool useMachineScheduler() const { return UseMISched; }
+  bool usePostRAScheduler() const { return UsePostRAScheduler; }
   bool useSoftFloat() const { return UseSoftFloat; }
   bool isThumb() const { return InThumbMode; }
   bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
   bool isThumb2() const { return InThumbMode && HasThumb2; }
   bool hasThumb2() const { return HasThumb2; }
   bool isMClass() const { return ARMProcClass == MClass; }
   bool isRClass() const { return ARMProcClass == RClass; }
   bool isAClass() const { return ARMProcClass == AClass; }

llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp

 bool ARMSubtarget::enableMachineScheduler() const {
   // Enable the MachineScheduler before register allocation for subtargets
   // with the use-misched feature.
   return useMachineScheduler();
 }
 
 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
 bool ARMSubtarget::enablePostRAScheduler() const {
+  if (usePostRAScheduler())
+    return true;
+  if (SchedModel.PostRAScheduler)
+    return true;
   // No need for PostRA scheduling on subtargets where we use the
   // MachineScheduler.
   if (useMachineScheduler())
     return false;
   return (!isThumb() || hasThumb2());
 }
 
 bool ARMSubtarget::enableAtomicExpand() const { return hasAnyDataBarrier(); }
 
 bool ARMSubtarget::useStride4VFPs(const MachineFunction &MF) const {
   // For general targets, the prologue can grow when VFPs are allocated with
   // stride 4 (more vpush instructions). But WatchOS uses a compact unwind
   // format which it's more important to get right.