[X86][ARM][TargetLowering] Add SrcVT to isExtractSubvectorCheap
ClosedPublic

Authored by craig.topper on Aug 12 2017, 3:46 PM.

Details

Summary

Without the SrcVT its hard to know what is really being asked for. For example if your target has 128, 256, and 512 bit vectors. Maybe extracting 128 from 256 is cheap, but maybe extracting 128 from 512 is not.

For x86 we do support extracting a quarter of a 512-bit register. But for i1 vectors we don't have isel patterns for extracting arbitrary pieces. So we need this to have a correct implementation of isExtractSubvectorCheap for mask vectors.

Diff Detail

Repository
rL LLVM
craig.topper created this revision.Aug 12 2017, 3:46 PM
RKSimon accepted this revision.Aug 13 2017, 6:14 AM

LGTM - one minor

include/llvm/Target/TargetLowering.h
2179 ↗(On Diff #110858)

Update comment to describe ResVT and SrcVT

This revision is now accepted and ready to land.Aug 13 2017, 6:14 AM
This revision was automatically updated to reflect the committed changes.