[AVX512] Correct isExtractSubvectorCheap so that it will return true for extracting 128-bits from the upper 256-bits of a 512-bit vector

[craig.topper]

Summary

Currently this routine is only setup to return true if you're extracting half of a vector. But we should also be reporting that extracting a quarter is cheap too.

Don't have a test case just happened to notice.

[craig.topper]

I also wonder if this interface shouldn't take the source type as input. In case some other target has multiple legal vector sizes but can't extract a quarter of vector like x86 can.

[RKSimon]

In D36638#839669, @craig.topper wrote:

I also wonder if this interface shouldn't take the source type as input. In case some other target has multiple legal vector sizes but can't extract a quarter of vector like x86 can.

+1 for SrcVT as well as ResVT

[craig.topper]

Update to include the correct answer for mask registers. Which seems to be that will allow any extract of a 0 index and otherwise only extracts of upper half.

[zvi]

LGTM

llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
   return true;
 }
 
 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
                                                 unsigned Index) const {
   if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
     return false;
 
-  return (Index == 0 || Index == ResVT.getVectorNumElements());
+  // Mask vectors support all subregister combinations and operations that
+  // extract half of vector.
+  if (ResVT.getVectorElementType() == MVT::i1)
+    return Index = 0 || ((ResVT.getSizeInBits() == SrcVT.getSizeInBits() * 2) &&
+                         (Index == ResVT.getVectorNumElements()));
+
+  return (Index % ResVT.getVectorNumElements()) == 0;
 }
 
 bool X86TargetLowering::isCheapToSpeculateCttz() const {
   // Speculate cttz only if we can directly use TZCNT.
   return Subtarget.hasBMI();
 }
 
 bool X86TargetLowering::isCheapToSpeculateCtlz() const {