[AArch64] Assembler support for v8.3 RCpc

[samparker]

Summary

Added assembler and disassembler support for the new Release Consistent processor consistent instructions, introduced with ARMv8.3-A for AArch64.

[t.p.northover]

LGTM with one nit.

test/MC/AArch64/armv8.3a-rcpc.s

5–8

Can we sprinkle some plain [x0] addressing modes here? No need to duplicate them all, just make 1 or 2 have an implicit operand in case some massive, highly unlikely refactoring breaks parsing later.

[samparker]

Cheers Tim. I've updated the test to include the simple addressing method and I've also used some different registers just for some variance in the test.

[t.p.northover]

Looks good. Thanks.

lib/Target/AArch64/AArch64.td

 def FeatureFuseLiterals : SubtargetFeature<
     "fuse-literals", "HasFuseLiterals", "true",
     "CPU fuses literal generation operations">;
 
 def FeatureDisableLatencySchedHeuristic : SubtargetFeature<
     "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
     "Disable latency scheduling heuristic">;
 
+def FeatureRCPC : SubtargetFeature<"rcpc", "HasRCPC", "true",
+                                   "Enable support for RCPC extension">;
+
 def FeatureUseRSqrt : SubtargetFeature<
     "use-reciprocal-square-root", "UseRSqrt", "true",
     "Use the reciprocal square root approximation">;
 
 def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates",
                                         "NegativeImmediates", "false",
                                         "Convert immediates and instructions "
                                         "to their negated or complemented "

 
 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
   "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM]>;
 
 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
   "Support ARM v8.2a instructions", [HasV8_1aOps, FeatureRAS]>;
 
 def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
-  "Support ARM v8.3a instructions", [HasV8_2aOps]>;
+  "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC]>;
 
 //===----------------------------------------------------------------------===//
 // Register File Description
 //===----------------------------------------------------------------------===//
 
 include "AArch64RegisterInfo.td"
 include "AArch64RegisterBanks.td"
 include "AArch64CallingConvention.td"

lib/Target/AArch64/AArch64InstrFormats.td

                                "$Rn = $wback,@earlyclobber $wback", opr> {
     let DecoderMethod = "DecodeAuthLoadWriteback";
   }
 
   def : InstAlias<asm # "\t$Rt, [$Rn]",
                   (!cast<Instruction>(NAME # "indexed") GPR64:$Rt, GPR64sp:$Rn, 0)>;
 }
 
+let mayLoad = 1 in
+class RCPCLoad<bits<2> sz, string asm, RegisterClass RC>
+  : I<(outs RC:$Rt), (ins GPR64sp0:$Rn), asm, "\t$Rt, [$Rn]", "", []>,
+  Sched<[]> {
+  bits<5> Rn;
+  bits<5> Rt;
+  let Inst{31-30} = sz;
+  let Inst{29-10} = 0b11100010111111110000;
+  let Inst{9-5} = Rn;
+  let Inst{4-0} = Rt;
+}
+
 //---
 // Conditional branch instruction.
 //---
 
 // Condition code.
 // 4-bit immediate. Pretty-printed as <cc>
 def ccode : Operand<i32> {
   let PrintMethod = "printCondCode";

lib/Target/AArch64/AArch64InstrInfo.td

                                  AssemblerPredicate<"FeatureFullFP16", "fullfp16">;
 def HasSPE           : Predicate<"Subtarget->hasSPE()">,
                                  AssemblerPredicate<"FeatureSPE", "spe">;
 def HasFuseAES       : Predicate<"Subtarget->hasFuseAES()">,
                                  AssemblerPredicate<"FeatureFuseAES",
                                  "fuse-aes">;
 def HasSVE           : Predicate<"Subtarget->hasSVE()">,
                                  AssemblerPredicate<"FeatureSVE", "sve">;
+def HasRCPC          : Predicate<"Subtarget->hasRCPC()">,
+                                 AssemblerPredicate<"FeatureRCPC", "rcpc">;
 
 def IsLE             : Predicate<"Subtarget->isLittleEndian()">;
 def IsBE             : Predicate<"!Subtarget->isLittleEndian()">;
 def UseAlternateSExtLoadCVTF32
     : Predicate<"Subtarget->useAlternateSExtLoadCVTF32Pattern()">;
 
 def UseNegativeImmediates
     : Predicate<"false">, AssemblerPredicate<"!FeatureNoNegativeImmediates",

     def ERETAB  : AuthReturn<0b100, 1, "eretab">;
   }
 
   defm LDRAA  : AuthLoad<0, "ldraa", simm10Scaled>;
   defm LDRAB  : AuthLoad<1, "ldrab", simm10Scaled>;
 
 } // HasV8_3A
 
+let Predicates = [HasRCPC] in {
+  // v8.3 Release Consistent Processor Consistent support
+  def LDAPRB  : RCPCLoad<0b00, "ldaprb", GPR32>;
+  def LDAPRH  : RCPCLoad<0b01, "ldaprh", GPR32>;
+  def LDAPRW  : RCPCLoad<0b10, "ldapr", GPR32>;
+  def LDAPRX  : RCPCLoad<0b11, "ldapr", GPR64>;
+}
+
 def : InstAlias<"clrex", (CLREX 0xf)>;
 def : InstAlias<"isb", (ISB 0xf)>;
 
 def MRS    : MRSI;
 def MSR    : MSRI;
 def MSRpstateImm1 : MSRpstateImm0_1;
 def MSRpstateImm4 : MSRpstateImm0_15;
 

lib/Target/AArch64/AArch64Subtarget.h

protected:
   bool HasLSE = false;
   bool HasRAS = false;
   bool HasRDM = false;
   bool HasPerfMon = false;
   bool HasFullFP16 = false;
   bool HasSPE = false;
   bool HasLSLFast = false;
   bool HasSVE = false;
+  bool HasRCPC = false;
 
   // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
   bool HasZeroCycleRegMove = false;
 
   // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
   bool HasZeroCycleZeroing = false;
 
   // StrictAlign - Disallow unaligned memory accesses.
public:
   /// translation) and OS enables it.
   bool supportsAddressTopByteIgnored() const;
 
   bool hasPerfMon() const { return HasPerfMon; }
   bool hasFullFP16() const { return HasFullFP16; }
   bool hasSPE() const { return HasSPE; }
   bool hasLSLFast() const { return HasLSLFast; }
   bool hasSVE() const { return HasSVE; }
+  bool hasRCPC() const { return HasRCPC; }
 
   bool isLittleEndian() const { return IsLittle; }
 
   bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
   bool isTargetIOS() const { return TargetTriple.isiOS(); }
   bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
   bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
   bool isTargetAndroid() const { return TargetTriple.isAndroid(); }

test/MC/AArch64/armv8.3a-rcpc.s

+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a < %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-REQ %s < %t
+
+  ldaprb w0, [x0, #0]
+  ldaprh w0, [x0, #0]
+  ldapr w0, [x0, #0]
+  ldapr x0, [x0, #0]
+
+// CHECK: ldaprb w0, [x0]   // encoding: [0x00,0xc0,0xbf,0x38]
+// CHECK: ldaprh w0, [x0]   // encoding: [0x00,0xc0,0xbf,0x78]
+// CHECK: ldapr w0, [x0]    // encoding: [0x00,0xc0,0xbf,0xb8]
+// CHECK: ldapr x0, [x0]    // encoding: [0x00,0xc0,0xbf,0xf8]
+// CHECK-REQ: error: invalid operand for instruction
+// CHECK-REQ: error: invalid operand for instruction
+// CHECK-REQ: error: invalid operand for instruction
+// CHECK-REQ: error: invalid operand for instruction

test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt

+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a --disassemble < %s | FileCheck %s
+
+# CHECK: ldaprb w0, [x0]
+# CHECK: ldaprh w0, [x0]
+# CHECK: ldapr w0, [x0]
+# CHECK: ldapr x0, [x0]
+[0x00,0xc0,0xbf,0x38]
+[0x00,0xc0,0xbf,0x78]
+[0x00,0xc0,0xbf,0xb8]
+[0x00,0xc0,0xbf,0xf8]
+
+# RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a --disassemble < %s 2>&1 | FileCheck --check-prefix=CHECK-V8_2A %s
+
+# CHECK-V8_2A: warning: invalid instruction encoding
+# CHECK-V8_2A: [0x00,0xc0,0xbf,0x38]
+# CHECK-V8_2A:  ^
+# CHECK-V8_2A: warning: invalid instruction encoding
+# CHECK-V8_2A: [0x00,0xc0,0xbf,0x78]
+# CHECK-V8_2A:  ^
+# CHECK-V8_2A: warning: invalid instruction encoding
+# CHECK-V8_2A: [0x00,0xc0,0xbf,0xb8]
+# CHECK-V8_2A:  ^
+# CHECK-V8_2A: warning: invalid instruction encoding
+# CHECK-V8_2A: [0x00,0xc0,0xbf,0xf8]
+# CHECK-V8_2A:  ^
+