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[AArch64] Assembler support for v8.3 RCpc
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Authored by samparker on Aug 9 2017, 7:25 AM.

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Summary

Added assembler and disassembler support for the new Release Consistent processor consistent instructions, introduced with ARMv8.3-A for AArch64.

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rL LLVM

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samparker created this revision.Aug 9 2017, 7:25 AM
t.p.northover accepted this revision.Aug 9 2017, 7:29 AM
t.p.northover added a subscriber: t.p.northover.

LGTM with one nit.

test/MC/AArch64/armv8.3a-rcpc.s
5–8 ↗(On Diff #110388)

Can we sprinkle some plain [x0] addressing modes here? No need to duplicate them all, just make 1 or 2 have an implicit operand in case some massive, highly unlikely refactoring breaks parsing later.

This revision is now accepted and ready to land.Aug 9 2017, 7:29 AM
samparker updated this revision to Diff 110391.Aug 9 2017, 7:55 AM

Cheers Tim. I've updated the test to include the simple addressing method and I've also used some different registers just for some variance in the test.

Looks good. Thanks.

This revision was automatically updated to reflect the committed changes.