This is an archive of the discontinued LLVM Phabricator instance.

Differential D36306

[ARM] Fix assembly and disassembly for VMRS/VMSR
ClosedPublic

Authored by avieira on Aug 4 2017, 4:57 AM.

Details

Reviewers
rengolin
t.p.northover
Commits
rG640527f7f13b: [ARM] Fix assembly and disassembly for VMRS/VMSR
rG7dffb9bfa608: [ARM] Fix assembly and disassembly for VMRS/VMSR
rL313979: [ARM] Fix assembly and disassembly for VMRS/VMSR
rL310243: [ARM] Fix assembly and disassembly for VMRS/VMSR
Summary

This patch addresses two issues with assembly and disassembly for VMRS/VMSR:

  1. currently VMRS/VMSR instructions accessing fpsid, mvfr{0-2} and fpexc, are accepted for non ARMv8-A targets.
  1. all VMRS/VMSR instructions accept writing/reading to PC and SP, when only ARMv7-A and ARMv8-A should be allowed to write/read to SP and none to PC.

This patch addresses those issues and adds tests for these cases.

Cheers,
Andre

Diff Detail

Repository
rL LLVM

Event Timeline

avieira created this revision.Aug 4 2017, 4:57 AM
Herald added subscribers: kristof.beyls, javed.absar, aemerson. · View Herald TranscriptAug 4 2017, 4:57 AM
t.p.northover accepted this revision.Aug 4 2017, 1:48 PM
t.p.northover added a subscriber: t.p.northover.

Looks reasonable to me, though please remember to add llvm-commits as a subscriber next time.

Tim.

This revision is now accepted and ready to land.Aug 4 2017, 1:48 PM
avieira added a subscriber: llvm-commits.Aug 7 2017, 1:03 AM
Closed by commit rL310243: [ARM] Fix assembly and disassembly for VMRS/VMSR (authored by avieira). · Explain WhyAug 7 2017, 1:42 AM
This revision was automatically updated to reflect the committed changes.
avieira reopened this revision.Aug 21 2017, 4:01 AM

Reopening as this was reverted earlier, submitting new version.

This revision is now accepted and ready to land.Aug 21 2017, 4:01 AM
avieira updated this revision to Diff 111945.Aug 21 2017, 4:03 AM

Now only access to MVFR2 requires Armv8, both A and M profiles, all other instructions are available for any Arm architecture.

avieira requested review of this revision.Sep 21 2017, 8:27 AM
avieira edited edge metadata.

The new version of the patch hasnt been reviewed.

t.p.northover accepted this revision.Sep 22 2017, 1:16 AM
Thanks, this new one looks good too.
This revision is now accepted and ready to land.Sep 22 2017, 1:16 AM
Closed by commit rL313979: [ARM] Fix assembly and disassembly for VMRS/VMSR (authored by avieira). · Explain WhySep 22 2017, 5:19 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
ARM/
76 lines
AsmParser/
6 lines
Disassembler/
24 lines
test/
MC/
ARM/
180 lines
Disassembler/
ARM/
60 lines
123 lines

Diff 116335

llvm/trunk/lib/Target/ARM/ARMInstrVFP.td

Show First 20 Lines • Show All 2,158 Lines • ▼ Show 20 Lines
} }
// APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags
// to APSR. // to APSR.
let Defs = [CPSR], Uses = [FPSCR_NZCV], Rt = 0b1111 /* apsr_nzcv */ in let Defs = [CPSR], Uses = [FPSCR_NZCV], Rt = 0b1111 /* apsr_nzcv */ in
def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins), def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins),
"vmrs", "\tAPSR_nzcv, fpscr", [(arm_fmstat)]>; "vmrs", "\tAPSR_nzcv, fpscr", [(arm_fmstat)]>;
let DecoderMethod = "DecodeForVMRSandVMSR" in {
// Application level FPSCR -> GPR // Application level FPSCR -> GPR
let hasSideEffects = 1, Uses = [FPSCR] in let hasSideEffects = 1, Uses = [FPSCR] in
def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPR:$Rt), (ins), def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPRnopc:$Rt), (ins),
"vmrs", "\t$Rt, fpscr", "vmrs", "\t$Rt, fpscr",
[(set GPR:$Rt, (int_arm_get_fpscr))]>; [(set GPRnopc:$Rt, (int_arm_get_fpscr))]>;
// System level FPEXC, FPSID -> GPR // System level FPEXC, FPSID -> GPR
let Uses = [FPSCR] in { let Uses = [FPSCR] in {
def VMRS_FPEXC : MovFromVFP<0b1000 /* fpexc */, (outs GPR:$Rt), (ins), def VMRS_FPEXC : MovFromVFP<0b1000 /* fpexc */, (outs GPRnopc:$Rt), (ins),
"vmrs", "\t$Rt, fpexc", []>; "vmrs", "\t$Rt, fpexc", []>;
def VMRS_FPSID : MovFromVFP<0b0000 /* fpsid */, (outs GPR:$Rt), (ins), def VMRS_FPSID : MovFromVFP<0b0000 /* fpsid */, (outs GPRnopc:$Rt), (ins),
"vmrs", "\t$Rt, fpsid", []>; "vmrs", "\t$Rt, fpsid", []>;
def VMRS_MVFR0 : MovFromVFP<0b0111 /* mvfr0 */, (outs GPR:$Rt), (ins), def VMRS_MVFR0 : MovFromVFP<0b0111 /* mvfr0 */, (outs GPRnopc:$Rt), (ins),
"vmrs", "\t$Rt, mvfr0", []>; "vmrs", "\t$Rt, mvfr0", []>;
def VMRS_MVFR1 : MovFromVFP<0b0110 /* mvfr1 */, (outs GPR:$Rt), (ins), def VMRS_MVFR1 : MovFromVFP<0b0110 /* mvfr1 */, (outs GPRnopc:$Rt), (ins),
"vmrs", "\t$Rt, mvfr1", []>; "vmrs", "\t$Rt, mvfr1", []>;
def VMRS_MVFR2 : MovFromVFP<0b0101 /* mvfr2 */, (outs GPR:$Rt), (ins), let Predicates = [HasFPARMv8] in {
"vmrs", "\t$Rt, mvfr2", []>, Requires<[HasFPARMv8]>; def VMRS_MVFR2 : MovFromVFP<0b0101 /* mvfr2 */, (outs GPRnopc:$Rt), (ins),
def VMRS_FPINST : MovFromVFP<0b1001 /* fpinst */, (outs GPR:$Rt), (ins), "vmrs", "\t$Rt, mvfr2", []>;
}
def VMRS_FPINST : MovFromVFP<0b1001 /* fpinst */, (outs GPRnopc:$Rt), (ins),
"vmrs", "\t$Rt, fpinst", []>; "vmrs", "\t$Rt, fpinst", []>;
def VMRS_FPINST2 : MovFromVFP<0b1010 /* fpinst2 */, (outs GPR:$Rt), (ins), def VMRS_FPINST2 : MovFromVFP<0b1010 /* fpinst2 */, (outs GPRnopc:$Rt),
"vmrs", "\t$Rt, fpinst2", []>; (ins), "vmrs", "\t$Rt, fpinst2", []>;
}
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Move from ARM core register to VFP System Register. // Move from ARM core register to VFP System Register.
// //
class MovToVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm, class MovToVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,
list<dag> pattern>: list<dag> pattern>:
VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> { VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> {
// Instruction operand. // Instruction operand.
bits<4> src; bits<4> src;
// Encode instruction operand. // Encode instruction operand.
let Inst{15-12} = src; let Inst{15-12} = src;
let Inst{27-20} = 0b11101110; let Inst{27-20} = 0b11101110;
let Inst{19-16} = opc19_16; let Inst{19-16} = opc19_16;
let Inst{11-8} = 0b1010; let Inst{11-8} = 0b1010;
let Inst{7} = 0; let Inst{7} = 0;
let Inst{4} = 1; let Inst{4} = 1;
} }
let DecoderMethod = "DecodeForVMRSandVMSR" in {
let Defs = [FPSCR] in { let Defs = [FPSCR] in {
// Application level GPR -> FPSCR // Application level GPR -> FPSCR
def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPR:$src), def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPRnopc:$src),
"vmsr", "\tfpscr, $src", [(int_arm_set_fpscr GPR:$src)]>; "vmsr", "\tfpscr, $src",
[(int_arm_set_fpscr GPRnopc:$src)]>;
// System level GPR -> FPEXC // System level GPR -> FPEXC
def VMSR_FPEXC : MovToVFP<0b1000 /* fpexc */, (outs), (ins GPR:$src), def VMSR_FPEXC : MovToVFP<0b1000 /* fpexc */, (outs), (ins GPRnopc:$src),
"vmsr", "\tfpexc, $src", []>; "vmsr", "\tfpexc, $src", []>;
// System level GPR -> FPSID // System level GPR -> FPSID
def VMSR_FPSID : MovToVFP<0b0000 /* fpsid */, (outs), (ins GPR:$src), def VMSR_FPSID : MovToVFP<0b0000 /* fpsid */, (outs), (ins GPRnopc:$src),
"vmsr", "\tfpsid, $src", []>; "vmsr", "\tfpsid, $src", []>;
def VMSR_FPINST : MovToVFP<0b1001 /* fpinst */, (outs), (ins GPRnopc:$src),
def VMSR_FPINST : MovToVFP<0b1001 /* fpinst */, (outs), (ins GPR:$src),
"vmsr", "\tfpinst, $src", []>; "vmsr", "\tfpinst, $src", []>;
def VMSR_FPINST2 : MovToVFP<0b1010 /* fpinst2 */, (outs), (ins GPR:$src), def VMSR_FPINST2 : MovToVFP<0b1010 /* fpinst2 */, (outs), (ins GPRnopc:$src),
"vmsr", "\tfpinst2, $src", []>; "vmsr", "\tfpinst2, $src", []>;
} }
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Misc. // Misc.
// //
// Materialize FP immediates. VFP3 only. // Materialize FP immediates. VFP3 only.
let isReMaterializable = 1 in { let isReMaterializable = 1 in {
def FCONSTD : VFPAI<(outs DPR:$Dd), (ins vfp_f64imm:$imm), def FCONSTD : VFPAI<(outs DPR:$Dd), (ins vfp_f64imm:$imm),
▲ Show 20 Lines • Show All 164 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 8,799 Lines • ▼ Show 20 Lines if (Inst.getOperand(0).getReg() == ARM::SP &&
return Match_RequiresV8; return Match_RequiresV8;
// When flags-setting SP as either source or destination is not allowed // When flags-setting SP as either source or destination is not allowed
if (Inst.getOperand(4).getReg() == ARM::CPSR && if (Inst.getOperand(4).getReg() == ARM::CPSR &&
(Inst.getOperand(0).getReg() == ARM::SP || (Inst.getOperand(0).getReg() == ARM::SP ||
Inst.getOperand(1).getReg() == ARM::SP)) Inst.getOperand(1).getReg() == ARM::SP))
return Match_RequiresV8; return Match_RequiresV8;
} }
// Use of SP for VMRS/VMSR is only allowed in ARM mode with the exception of
// ARMv8-A.
if ((Inst.getOpcode() == ARM::VMRS || Inst.getOpcode() == ARM::VMSR) &&
Inst.getOperand(0).getReg() == ARM::SP && (isThumb() && !hasV8Ops()))
return Match_InvalidOperand;
for (unsigned I = 0; I < MCID.NumOperands; ++I) for (unsigned I = 0; I < MCID.NumOperands; ++I)
if (MCID.OpInfo[I].RegClass == ARM::rGPRRegClassID) { if (MCID.OpInfo[I].RegClass == ARM::rGPRRegClassID) {
// rGPRRegClass excludes PC, and also excluded SP before ARMv8 // rGPRRegClass excludes PC, and also excluded SP before ARMv8
if ((Inst.getOperand(I).getReg() == ARM::SP) && !hasV8Ops()) if ((Inst.getOperand(I).getReg() == ARM::SP) && !hasV8Ops())
return Match_RequiresV8; return Match_RequiresV8;
else if (Inst.getOperand(I).getReg() == ARM::PC) else if (Inst.getOperand(I).getReg() == ARM::PC)
return Match_InvalidOperand; return Match_InvalidOperand;
} }
▲ Show 20 Lines • Show All 1,465 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

Show First 20 Lines • Show All 394 Lines • ▼ Show 20 Linesstatic DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
#include "ARMGenDisassemblerTables.inc" #include "ARMGenDisassemblerTables.inc"
static MCDisassembler *createARMDisassembler(const Target &T, static MCDisassembler *createARMDisassembler(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
MCContext &Ctx) { MCContext &Ctx) {
return new ARMDisassembler(STI, Ctx); return new ARMDisassembler(STI, Ctx);
} }
▲ Show 20 Lines • Show All 4,868 Lines • ▼ Show 20 Lines if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
Inst.addOperand(MCOperand::createImm(CRm)); Inst.addOperand(MCOperand::createImm(CRm));
return S; return S;
} }
static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
uint64_t Address,
const void *Decoder) {
const FeatureBitset &featureBits =
((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
DecodeStatus S = MCDisassembler::Success;
unsigned Rt = fieldFromInstruction(Val, 12, 4);
if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) {
if (Rt == 13 || Rt == 15)
S = MCDisassembler::SoftFail;
Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
} else
Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder));
Inst.addOperand(MCOperand::createImm(ARMCC::AL));
Inst.addOperand(MCOperand::createReg(0));
return S;
}

llvm/trunk/test/MC/ARM/vmrs_vmsr.s

// RUN: not llvm-mc -triple=armv7a-arm-none-eabi -mattr=+vfp2 -show-encoding < %s 2>%t \
// RUN: | FileCheck --check-prefix=CHECK-V7A-ARM %s
// RUN: FileCheck --check-prefix=ERROR-V7A-ARM < %t %s
// RUN: not llvm-mc -triple=thumbv7a-arm-none-eabi -mattr=+vfp2 -show-encoding < %s 2>%t \
// RUN: | FileCheck --check-prefix=CHECK-V7A-THUMB %s
// RUN: FileCheck --check-prefix=ERROR-V7A-THUMB < %t %s
// RUN: not llvm-mc -triple=thumbv7m-arm-none-eabi -mattr=+vfp2 -show-encoding < %s 2>%t \
// RUN: | FileCheck --check-prefix=CHECK-V7M %s
// RUN: FileCheck --check-prefix=ERROR-V7M < %t %s
// RUN: not llvm-mc -triple=armv8a-arm-none-eabi -mattr=+fp-armv8 -show-encoding < %s 2>%t \
// RUN: | FileCheck --check-prefix=CHECK-V8A-ARM %s
// RUN: FileCheck --check-prefix=ERROR-V8A-ARM < %t %s
// RUN: not llvm-mc -triple=thumbv8a-arm-none-eabi -mattr=+fp-armv8 -show-encoding < %s 2>%t \
// RUN: | FileCheck --check-prefix=CHECK-V8A-THUMB %s
// RUN: FileCheck --check-prefix=ERROR-V8A-THUMB < %t %s
// RUN: not llvm-mc -triple=thumbv8m.main-arm-none-eabi -mattr=+fp-armv8 -show-encoding < %s 2>%t \
// RUN: | FileCheck --check-prefix=CHECK-V8M %s
// RUN: FileCheck --check-prefix=ERROR-V8M < %t %s
// RUN: not llvm-mc -triple=thumbv7m-arm-none-eabi -show-encoding < %s 2>%t
// RUN: FileCheck --check-prefix=ERROR-NOVFP < %t %s
vmrs APSR_nzcv, fpscr
vmrs apsr_nzcv, fpscr
fmstat
vmrs r10, fpscr
vmrs r2, fpsid
vmrs r3, FPSID
vmrs r4, mvfr0
vmrs r5, MVFR1
vmrs r6, mvfr2
vmrs sp, fpscr
vmrs pc, fpscr
// CHECK-V7A-ARM: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
// CHECK-V7A-ARM: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
// CHECK-V7A-ARM: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
// CHECK-V7A-ARM: vmrs r10, fpscr @ encoding: [0x10,0xaa,0xf1,0xee]
// CHECK-V7A-ARM: vmrs r2, fpsid @ encoding: [0x10,0x2a,0xf0,0xee]
// CHECK-V7A-ARM: vmrs r3, fpsid @ encoding: [0x10,0x3a,0xf0,0xee]
// CHECK-V7A-ARM: vmrs r4, mvfr0 @ encoding: [0x10,0x4a,0xf7,0xee]
// CHECK-V7A-ARM: vmrs r5, mvfr1 @ encoding: [0x10,0x5a,0xf6,0xee]
// ERROR-V7A-ARM: instruction requires: FPARMv8
// CHECK-V7A-ARM: vmrs sp, fpscr @ encoding: [0x10,0xda,0xf1,0xee]
// ERROR-V7A-ARM: invalid operand for instruction
// CHECK-V7A-THUMB: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
// CHECK-V7A-THUMB: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
// CHECK-V7A-THUMB: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
// CHECK-V7A-THUMB: vmrs r10, fpscr @ encoding: [0xf1,0xee,0x10,0xaa]
// CHECK-V7A-THUMB: vmrs r2, fpsid @ encoding: [0xf0,0xee,0x10,0x2a]
// CHECK-V7A-THUMB: vmrs r3, fpsid @ encoding: [0xf0,0xee,0x10,0x3a]
// CHECK-V7A-THUMB: vmrs r4, mvfr0 @ encoding: [0xf7,0xee,0x10,0x4a]
// CHECK-V7A-THUMB: vmrs r5, mvfr1 @ encoding: [0xf6,0xee,0x10,0x5a]
// ERROR-V7A-THUMB: instruction requires: FPARMv8
// ERROR-V7A-THUMB: invalid operand for instruction
// ERROR-V7A-THUMB: invalid operand for instruction
// CHECK-V7M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
// CHECK-V7M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
// CHECK-V7M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
// CHECK-V7M: vmrs r10, fpscr @ encoding: [0xf1,0xee,0x10,0xaa]
// CHECK-V7M: vmrs r2, fpsid @ encoding: [0xf0,0xee,0x10,0x2a]
// CHECK-V7M: vmrs r3, fpsid @ encoding: [0xf0,0xee,0x10,0x3a]
// CHECK-V7M: vmrs r4, mvfr0 @ encoding: [0xf7,0xee,0x10,0x4a]
// CHECK-V7M: vmrs r5, mvfr1 @ encoding: [0xf6,0xee,0x10,0x5a]
// ERROR-V7M: instruction requires: FPARMv8
// ERROR-V7M: invalid operand for instruction
// ERROR-V7M: invalid operand for instruction
// CHECK-V8A-ARM: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
// CHECK-V8A-ARM: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
// CHECK-V8A-ARM: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
// CHECK-V8A-ARM: vmrs r10, fpscr @ encoding: [0x10,0xaa,0xf1,0xee]
// CHECK-V8A-ARM: vmrs r2, fpsid @ encoding: [0x10,0x2a,0xf0,0xee]
// CHECK-V8A-ARM: vmrs r3, fpsid @ encoding: [0x10,0x3a,0xf0,0xee]
// CHECK-V8A-ARM: vmrs r4, mvfr0 @ encoding: [0x10,0x4a,0xf7,0xee]
// CHECK-V8A-ARM: vmrs r5, mvfr1 @ encoding: [0x10,0x5a,0xf6,0xee]
// CHECK-V8A-ARM: vmrs r6, mvfr2 @ encoding: [0x10,0x6a,0xf5,0xee]
// CHECK-V8A-ARM: vmrs sp, fpscr @ encoding: [0x10,0xda,0xf1,0xee]
// ERROR-V8A-ARM: invalid operand for instruction
// CHECK-V8A-THUMB: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
// CHECK-V8A-THUMB: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
// CHECK-V8A-THUMB: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
// CHECK-V8A-THUMB: vmrs r10, fpscr @ encoding: [0xf1,0xee,0x10,0xaa]
// CHECK-V8A-THUMB: vmrs r2, fpsid @ encoding: [0xf0,0xee,0x10,0x2a]
// CHECK-V8A-THUMB: vmrs r3, fpsid @ encoding: [0xf0,0xee,0x10,0x3a]
// CHECK-V8A-THUMB: vmrs r4, mvfr0 @ encoding: [0xf7,0xee,0x10,0x4a]
// CHECK-V8A-THUMB: vmrs r5, mvfr1 @ encoding: [0xf6,0xee,0x10,0x5a]
// CHECK-V8A-THUMB: vmrs r6, mvfr2 @ encoding: [0xf5,0xee,0x10,0x6a]
// CHECK-V8A-THUMB: vmrs sp, fpscr @ encoding: [0xf1,0xee,0x10,0xda]
// ERROR-V8A-THUMB: invalid operand for instruction
// CHECK-V8M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
// CHECK-V8M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
// CHECK-V8M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
// CHECK-V8M: vmrs r10, fpscr @ encoding: [0xf1,0xee,0x10,0xaa]
// CHECK-V8M: vmrs r2, fpsid @ encoding: [0xf0,0xee,0x10,0x2a]
// CHECK-V8M: vmrs r3, fpsid @ encoding: [0xf0,0xee,0x10,0x3a]
// CHECK-V8M: vmrs r4, mvfr0 @ encoding: [0xf7,0xee,0x10,0x4a]
// CHECK-V8M: vmrs r5, mvfr1 @ encoding: [0xf6,0xee,0x10,0x5a]
// CHECK-V8M: vmrs r6, mvfr2 @ encoding: [0xf5,0xee,0x10,0x6a]
// ERROR-V8M: invalid operand for instruction
// ERROR-V8M: invalid operand for instruction
// ERROR-NOVFP: instruction requires: VFP2
// ERROR-NOVFP: instruction requires: VFP2
// ERROR-NOVFP: instruction requires: VFP2
// ERROR-NOVFP: instruction requires: VFP2
// ERROR-NOVFP: instruction requires: VFP2
// ERROR-NOVFP: instruction requires: VFP2
// ERROR-NOVFP: instruction requires: VFP2
// ERROR-NOVFP: instruction requires: VFP2
// ERROR-NOVFP: instruction requires: FPARMv8
// ERROR-NOVFP: instruction requires: VFP2
// ERROR-NOVFP: invalid operand for instruction
vmsr fpscr, APSR_nzcv
vmsr fpscr, r0
vmsr fpexc, r1
vmsr fpsid, r2
vmsr fpscr, r10
vmsr fpscr, sp
vmsr fpscr, pc
// ERROR-V7A-ARM: invalid operand for instruction
// CHECK-V7A-ARM: vmsr fpscr, r0 @ encoding: [0x10,0x0a,0xe1,0xee]
// CHECK-V7A-ARM: vmsr fpexc, r1 @ encoding: [0x10,0x1a,0xe8,0xee]
// CHECK-V7A-ARM: vmsr fpsid, r2 @ encoding: [0x10,0x2a,0xe0,0xee]
// CHECK-V7A-ARM: vmsr fpscr, r10 @ encoding: [0x10,0xaa,0xe1,0xee]
// CHECK-V7A-ARM: vmsr fpscr, sp @ encoding: [0x10,0xda,0xe1,0xee]
// ERROR-V7A-ARM: invalid operand for instruction
// ERROR-V7A-THUMB: invalid operand for instruction
// CHECK-V7A-THUMB: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
// CHECK-V7A-THUMB: vmsr fpexc, r1 @ encoding: [0xe8,0xee,0x10,0x1a]
// CHECK-V7A-THUMB: vmsr fpsid, r2 @ encoding: [0xe0,0xee,0x10,0x2a]
// CHECK-V7A-THUMB: vmsr fpscr, r10 @ encoding: [0xe1,0xee,0x10,0xaa]
// ERROR-V7A-THUMB: invalid operand for instruction
// ERROR-V7A-THUMB: invalid operand for instruction
// ERROR-V7M: invalid operand for instruction
// CHECK-V7M: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
// CHECK-V7M: vmsr fpexc, r1 @ encoding: [0xe8,0xee,0x10,0x1a]
// CHECK-V7M: vmsr fpsid, r2 @ encoding: [0xe0,0xee,0x10,0x2a]
// CHECK-V7M: vmsr fpscr, r10 @ encoding: [0xe1,0xee,0x10,0xaa]
// ERROR-V7M: invalid operand for instruction
// ERROR-V7M: invalid operand for instruction
// ERROR-V8A-ARM: invalid operand for instruction
// CHECK-V8A-ARM: vmsr fpscr, r0 @ encoding: [0x10,0x0a,0xe1,0xee]
// CHECK-V8A-ARM: vmsr fpexc, r1 @ encoding: [0x10,0x1a,0xe8,0xee]
// CHECK-V8A-ARM: vmsr fpsid, r2 @ encoding: [0x10,0x2a,0xe0,0xee]
// CHECK-V8A-ARM: vmsr fpscr, r10 @ encoding: [0x10,0xaa,0xe1,0xee]
// CHECK-V8A-ARM: vmsr fpscr, sp @ encoding: [0x10,0xda,0xe1,0xee]
// ERROR-V8A-ARM: invalid operand for instruction
// ERROR-V8A-THUMB: invalid operand for instruction
// CHECK-V8A-THUMB: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
// CHECK-V8A-THUMB: vmsr fpexc, r1 @ encoding: [0xe8,0xee,0x10,0x1a]
// CHECK-V8A-THUMB: vmsr fpsid, r2 @ encoding: [0xe0,0xee,0x10,0x2a]
// CHECK-V8A-THUMB: vmsr fpscr, r10 @ encoding: [0xe1,0xee,0x10,0xaa]
// CHECK-V8A-THUMB: vmsr fpscr, sp @ encoding: [0xe1,0xee,0x10,0xda]
// ERROR-V8A-THUMB: invalid operand for instruction
// ERROR-V8M: invalid operand for instruction
// CHECK-V8M: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
// CHECK-V8M: vmsr fpexc, r1 @ encoding: [0xe8,0xee,0x10,0x1a]
// CHECK-V8M: vmsr fpsid, r2 @ encoding: [0xe0,0xee,0x10,0x2a]
// CHECK-V8M: vmsr fpscr, r10 @ encoding: [0xe1,0xee,0x10,0xaa]
// ERROR-V8M: invalid operand for instruction
// ERROR-V8M: invalid operand for instruction
// ERROR-NOVFP: invalid operand for instruction
// ERROR-NOVFP: instruction requires: VFP2
// ERROR-NOVFP: instruction requires: VFP2
// ERROR-NOVFP: instruction requires: VFP2
// ERROR-NOVFP: instruction requires: VFP2
// ERROR-NOVFP: instruction requires: VFP2
// ERROR-NOVFP: invalid operand for instruction

llvm/trunk/test/MC/Disassembler/ARM/arm-vmrs_vmsr.txt

# RUN: not llvm-mc -disassemble -triple=armv7a-arm-none-eabi -mattr=+vfp2 -show-encoding < %s 2>%t \
# RUN: | FileCheck --check-prefix=CHECK-V7A %s
# RUN: FileCheck --check-prefix=ERROR-V7A < %t %s
# RUN: llvm-mc -disassemble -triple=armv8a-arm-none-eabi -mattr=+fp-armv8 -show-encoding < %s 2>%t \
# RUN: | FileCheck --check-prefix=CHECK-V8A %s
# RUN: FileCheck --check-prefix=ERROR-V8A < %t %s
[0x10,0xfa,0xf1,0xee]
[0x10,0xfa,0xf1,0xee]
[0x10,0xfa,0xf1,0xee]
[0x10,0xaa,0xf1,0xee]
[0x10,0x2a,0xf0,0xee]
[0x10,0x3a,0xf0,0xee]
[0x10,0x4a,0xf7,0xee]
[0x10,0x5a,0xf6,0xee]
[0x10,0x6a,0xf5,0xee]
[0x10,0xda,0xf1,0xee]
# CHECK-V7A: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
# CHECK-V7A: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
# CHECK-V7A: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
# CHECK-V7A: vmrs r10, fpscr @ encoding: [0x10,0xaa,0xf1,0xee]
# CHECK-V7A: vmrs r2, fpsid @ encoding: [0x10,0x2a,0xf0,0xee]
# CHECK-V7A: vmrs r3, fpsid @ encoding: [0x10,0x3a,0xf0,0xee]
# CHECK-V7A: vmrs r4, mvfr0 @ encoding: [0x10,0x4a,0xf7,0xee]
# CHECK-V7A: vmrs r5, mvfr1 @ encoding: [0x10,0x5a,0xf6,0xee]
# ERROR-V7A: invalid instruction encoding
# CHECK-V7A: vmrs sp, fpscr @ encoding: [0x10,0xda,0xf1,0xee]
# CHECK-V8A: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
# CHECK-V8A: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
# CHECK-V8A: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
# CHECK-V8A: vmrs r10, fpscr @ encoding: [0x10,0xaa,0xf1,0xee]
# CHECK-V8A: vmrs r2, fpsid @ encoding: [0x10,0x2a,0xf0,0xee]
# CHECK-V8A: vmrs r3, fpsid @ encoding: [0x10,0x3a,0xf0,0xee]
# CHECK-V8A: vmrs r4, mvfr0 @ encoding: [0x10,0x4a,0xf7,0xee]
# CHECK-V8A: vmrs r5, mvfr1 @ encoding: [0x10,0x5a,0xf6,0xee]
# CHECK-V8A: vmrs r6, mvfr2 @ encoding: [0x10,0x6a,0xf5,0xee]
# CHECK-V8A: vmrs sp, fpscr @ encoding: [0x10,0xda,0xf1,0xee]
[0x10,0xfa,0xe1,0xee]
[0x10,0x0a,0xe1,0xee]
[0x10,0x1a,0xe8,0xee]
[0x10,0x2a,0xe0,0xee]
[0x10,0xaa,0xe1,0xee]
[0x10,0xda,0xe1,0xee]
# ERROR-V7A: potentially undefined instruction encoding
# CHECK-V7A: vmsr fpscr, r0 @ encoding: [0x10,0x0a,0xe1,0xee]
# CHECK-V7A: vmsr fpexc, r1 @ encoding: [0x10,0x1a,0xe8,0xee]
# CHECK-V7A: vmsr fpsid, r2 @ encoding: [0x10,0x2a,0xe0,0xee]
# CHECK-V7A: vmsr fpscr, r10 @ encoding: [0x10,0xaa,0xe1,0xee]
# CHECK-V7A: vmsr fpscr, sp @ encoding: [0x10,0xda,0xe1,0xee]
# ERROR-V8A: potentially undefined instruction encoding
# CHECK-V8A: vmsr fpscr, r0 @ encoding: [0x10,0x0a,0xe1,0xee]
# CHECK-V8A: vmsr fpexc, r1 @ encoding: [0x10,0x1a,0xe8,0xee]
# CHECK-V8A: vmsr fpsid, r2 @ encoding: [0x10,0x2a,0xe0,0xee]
# CHECK-V8A: vmsr fpscr, r10 @ encoding: [0x10,0xaa,0xe1,0xee]
# CHECK-V8A: vmsr fpscr, sp @ encoding: [0x10,0xda,0xe1,0xee]

llvm/trunk/test/MC/Disassembler/ARM/thumb-vmrs_vmsr.txt

# RUN: not llvm-mc -disassemble -triple=thumbv7a-arm-none-eabi -mattr=+vfp2 -show-encoding < %s 2>%t \
# RUN: | FileCheck --check-prefix=CHECK-V7A %s
# RUN: FileCheck --check-prefix=ERROR-V7A < %t %s
# RUN: not llvm-mc -disassemble -triple=thumbv7m-arm-none-eabi -mattr=+vfp2 -show-encoding < %s 2>%t \
# RUN: | FileCheck --check-prefix=CHECK-V7M %s
# RUN: FileCheck --check-prefix=ERROR-V7M < %t %s
# RUN: llvm-mc -disassemble -triple=thumbv8a-arm-none-eabi -mattr=+fp-armv8 -show-encoding < %s 2>%t \
# RUN: | FileCheck --check-prefix=CHECK-V8A %s
# RUN: FileCheck --check-prefix=ERROR-V8A < %t %s
# RUN: llvm-mc -disassemble -triple=thumbv8m.main-arm-none-eabi -mattr=+fp-armv8 -show-encoding < %s 2>%t \
# RUN: | FileCheck --check-prefix=CHECK-V8M %s
# RUN: FileCheck --check-prefix=ERROR-V8M < %t %s
# RUN: not llvm-mc -disassemble -triple=thumbv7m-arm-none-eabi -show-encoding < %s 2>%t
# RUN: FileCheck --check-prefix=ERROR-NOVFP < %t %s
[0xf1,0xee,0x10,0xfa]
[0xf1,0xee,0x10,0xfa]
[0xf1,0xee,0x10,0xfa]
[0xf1,0xee,0x10,0xaa]
[0xf0,0xee,0x10,0x2a]
[0xf0,0xee,0x10,0x3a]
[0xf7,0xee,0x10,0x4a]
[0xf6,0xee,0x10,0x5a]
[0xf5,0xee,0x10,0x6a]
[0xf1,0xee,0x10,0xda]
# CHECK-V7A: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
# CHECK-V7A: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
# CHECK-V7A: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
# CHECK-V7A: vmrs r10, fpscr @ encoding: [0xf1,0xee,0x10,0xaa]
# CHECK-V7A: vmrs r2, fpsid @ encoding: [0xf0,0xee,0x10,0x2a]
# CHECK-V7A: vmrs r3, fpsid @ encoding: [0xf0,0xee,0x10,0x3a]
# CHECK-V7A: vmrs r4, mvfr0 @ encoding: [0xf7,0xee,0x10,0x4a]
# CHECK-V7A: vmrs r5, mvfr1 @ encoding: [0xf6,0xee,0x10,0x5a]
# ERROR-V7A: invalid instruction encoding
# ERROR-V7A: potentially undefined instruction encoding
# CHECK-V7M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
# CHECK-V7M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
# CHECK-V7M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
# CHECK-V7M: vmrs r10, fpscr @ encoding: [0xf1,0xee,0x10,0xaa]
# CHECK-V7M: vmrs r2, fpsid @ encoding: [0xf0,0xee,0x10,0x2a]
# CHECK-V7M: vmrs r3, fpsid @ encoding: [0xf0,0xee,0x10,0x3a]
# CHECK-V7M: vmrs r4, mvfr0 @ encoding: [0xf7,0xee,0x10,0x4a]
# CHECK-V7M: vmrs r5, mvfr1 @ encoding: [0xf6,0xee,0x10,0x5a]
# ERROR-V7M: invalid instruction encoding
# ERROR-V7M: potentially undefined instruction encoding
# CHECK-V8A: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
# CHECK-V8A: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
# CHECK-V8A: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
# CHECK-V8A: vmrs r10, fpscr @ encoding: [0xf1,0xee,0x10,0xaa]
# CHECK-V8A: vmrs r2, fpsid @ encoding: [0xf0,0xee,0x10,0x2a]
# CHECK-V8A: vmrs r3, fpsid @ encoding: [0xf0,0xee,0x10,0x3a]
# CHECK-V8A: vmrs r4, mvfr0 @ encoding: [0xf7,0xee,0x10,0x4a]
# CHECK-V8A: vmrs r5, mvfr1 @ encoding: [0xf6,0xee,0x10,0x5a]
# CHECK-V8A: vmrs r6, mvfr2 @ encoding: [0xf5,0xee,0x10,0x6a]
# CHECK-V8A: vmrs sp, fpscr @ encoding: [0xf1,0xee,0x10,0xda]
# CHECK-V8M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
# CHECK-V8M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
# CHECK-V8M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
# CHECK-V8M: vmrs r10, fpscr @ encoding: [0xf1,0xee,0x10,0xaa]
# CHECK-V8M: vmrs r2, fpsid @ encoding: [0xf0,0xee,0x10,0x2a]
# CHECK-V8M: vmrs r3, fpsid @ encoding: [0xf0,0xee,0x10,0x3a]
# CHECK-V8M: vmrs r4, mvfr0 @ encoding: [0xf7,0xee,0x10,0x4a]
# CHECK-V8M: vmrs r5, mvfr1 @ encoding: [0xf6,0xee,0x10,0x5a]
# CHECK-V8M: vmrs r6, mvfr2 @ encoding: [0xf5,0xee,0x10,0x6a]
# ERROR-V8M: potentially undefined instruction encoding
# ERROR-NOVFP: invalid instruction encoding
# ERROR-NOVFP: invalid instruction encoding
# ERROR-NOVFP: invalid instruction encoding
# ERROR-NOVFP: invalid instruction encoding
# ERROR-NOVFP: invalid instruction encoding
# ERROR-NOVFP: invalid instruction encoding
# ERROR-NOVFP: invalid instruction encoding
# ERROR-NOVFP: invalid instruction encoding
# ERROR-NOVFP: invalid instruction encoding
# ERROR-NOVFP: invalid instruction encoding
[0xe1,0xee,0x10,0xfa]
[0xe1,0xee,0x10,0x0a]
[0xe8,0xee,0x10,0x1a]
[0xe0,0xee,0x10,0x2a]
[0xe1,0xee,0x10,0xaa]
[0xe1,0xee,0x10,0xda]
# ERROR-V7A: potentially undefined instruction encoding
# CHECK-V7A: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
# CHECK-V7A: vmsr fpexc, r1 @ encoding: [0xe8,0xee,0x10,0x1a]
# CHECK-V7A: vmsr fpsid, r2 @ encoding: [0xe0,0xee,0x10,0x2a]
# CHECK-V7A: vmsr fpscr, r10 @ encoding: [0xe1,0xee,0x10,0xaa]
# ERROR-V7A: potentially undefined instruction encoding
# ERROR-V7M: potentially undefined instruction encoding
# CHECK-V7M: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
# CHECK-V7M: vmsr fpexc, r1 @ encoding: [0xe8,0xee,0x10,0x1a]
# CHECK-V7M: vmsr fpsid, r2 @ encoding: [0xe0,0xee,0x10,0x2a]
# CHECK-V7M: vmsr fpscr, r10 @ encoding: [0xe1,0xee,0x10,0xaa]
# ERROR-V7M: potentially undefined instruction encoding
# ERROR-V8A: potentially undefined instruction encoding
# CHECK-V8A: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
# CHECK-V8A: vmsr fpexc, r1 @ encoding: [0xe8,0xee,0x10,0x1a]
# CHECK-V8A: vmsr fpsid, r2 @ encoding: [0xe0,0xee,0x10,0x2a]
# CHECK-V8A: vmsr fpscr, r10 @ encoding: [0xe1,0xee,0x10,0xaa]
# CHECK-V8A: vmsr fpscr, sp @ encoding: [0xe1,0xee,0x10,0xda]
# ERROR-V8M: potentially undefined instruction encoding
# CHECK-V8M: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
# CHECK-V8M: vmsr fpexc, r1 @ encoding: [0xe8,0xee,0x10,0x1a]
# CHECK-V8M: vmsr fpsid, r2 @ encoding: [0xe0,0xee,0x10,0x2a]
# CHECK-V8M: vmsr fpscr, r10 @ encoding: [0xe1,0xee,0x10,0xaa]
# ERROR-V8M: potentially undefined instruction encoding
# ERROR-NOVFP: invalid instruction encoding
# ERROR-NOVFP: invalid instruction encoding
# ERROR-NOVFP: invalid instruction encoding
# ERROR-NOVFP: invalid instruction encoding
# ERROR-NOVFP: invalid instruction encoding
# ERROR-NOVFP: invalid instruction encoding