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Differential D35984

[mips][microMIPS] Add LAPC instruction
ClosedPublic

Authored by mstojanovic on Jul 28 2017, 2:07 AM.

Details

Reviewers
sdardis
zoran.jovanovic
petarj
Commits
rGd4f3723c561f: [mips][microMIPS] add lapc instruction
rL312934: [mips][microMIPS] add lapc instruction
Summary

Implement LAPC instruction for mips32r6, mips64r6 and micromips32r6.

Diff Detail

Event Timeline

mstojanovic created this revision.Jul 28 2017, 2:07 AM
Herald added a subscriber: arichardson. · View Herald TranscriptJul 28 2017, 2:07 AM
sdardis requested changes to this revision.Aug 9 2017, 8:05 AM

This macro only exists for R6, so it shouldn't be in the generic microMIPS tests.

lib/Target/Mips/MicroMipsInstrInfo.td
1187–1189 ↗(On Diff #108604)

This macro doesn't exist for pre-R6 code, so this and the rest of the associated tests can be removed for pre-R6.

test/MC/Mips/micromips-alu-instructions.s
134–136 ↗(On Diff #108604)

This hunk and it's corresponding check lines should go in micromips32r6/valid.s

test/MC/Mips/micromips-invalid.s
43 ↗(On Diff #108604)

This should go in micromips32r6/invalid-wrong-error.s

test/MC/Mips/micromips/valid.s
181–183 ↗(On Diff #108604)

This should be in test/MC/Mips/micromips32r6/valid.s

This revision now requires changes to proceed.Aug 9 2017, 8:05 AM
mstojanovic updated this revision to Diff 113558.Sep 1 2017, 11:07 AM
mstojanovic edited edge metadata.
mstojanovic edited the summary of this revision. (Show Details)
mstojanovic added a subscriber: llvm-commits.

Marco removed from pre-R6 microMIPS.

sdardis requested changes to this revision.Sep 5 2017, 2:28 AM

I'm seeing some test failures:

LLVM :: MC/Mips/micromips32r6/invalid-wrong-error.s
LLVM :: MC/Mips/micromips32r6/valid.s

I've highlighted the issues in inline comments.

test/MC/Mips/micromips32r6/invalid-wrong-error.s
45–47

Sorry about the confusion, simm19_lsl2 does give the correct error message.

These three should be in test/MC/Mips/micromips32r6/invalid.s and should be: error: expected both 19-bit signed immediate and multiple of 4

Also, test -1048580, 1048576 as they're the next multiple of 4 instead of 16777220 / 16777216.

47

Provide a negative unencodable number as well.

test/MC/Mips/micromips32r6/valid.s
67–68

The limits should be [-1048576, 1048572].

This revision now requires changes to proceed.Sep 5 2017, 2:28 AM
mstojanovic updated this revision to Diff 113996.Sep 6 2017, 6:14 AM
mstojanovic edited edge metadata.

Fixed test ranges and moved tests to appropriate files.

sdardis accepted this revision.Sep 6 2017, 7:12 AM

LGTM with inline nit addressed.

test/MC/Mips/micromips32r6/invalid.s
41–44 ↗(On Diff #113996)

This should be duplicated into test/MC/Mips/mips{32|64}r6/invalid.s .

This revision is now accepted and ready to land.Sep 6 2017, 7:12 AM
mstojanovic updated this revision to Diff 114142.Sep 7 2017, 3:44 AM

Added tests to test/MC/Mips/mips{32|64}r6/invalid.s

Closed by commit rL312934: [mips][microMIPS] add lapc instruction (authored by petarj). · Explain WhySep 11 2017, 11:35 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
Mips/
3 lines
3 lines
test/
MC/
Disassembler/
Mips/
micromips32r6/
2 lines
mips32r6/
2 lines
2 lines
mips64r6/
2 lines
2 lines
Mips/
micromips32r6/
3 lines
9 lines
5 lines
micromips64r6/
11 lines
mips32r6/
7 lines
3 lines
mips64r6/
11 lines
3 lines

Diff 113558

lib/Target/Mips/MicroMips32r6InstrInfo.td

Show First 20 Lines • Show All 1,823 Lines • ▼ Show 20 Linesdef : MipsInstAlias<"xor $rs, $imm",
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def : MipsInstAlias<"not $rt, $rs", def : MipsInstAlias<"not $rt, $rs",
(NOR_MMR6 GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>, (NOR_MMR6 GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def : MipsInstAlias<"seh $rd", (SEH_MMR6 GPR32Opnd:$rd, GPR32Opnd:$rd), 0>, def : MipsInstAlias<"seh $rd", (SEH_MMR6 GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def : MipsInstAlias<"seb $rd", (SEB_MMR6 GPR32Opnd:$rd, GPR32Opnd:$rd), 0>, def : MipsInstAlias<"seb $rd", (SEB_MMR6 GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def : MipsInstAlias<"lapc $rd, $imm",
(ADDIUPC_MMR6 GPR32Opnd:$rd, simm19_lsl2:$imm)>,
ISA_MICROMIPS32R6;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// MicroMips arbitrary patterns that map to one or more instructions // MicroMips arbitrary patterns that map to one or more instructions
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr), def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr),
Show All 39 Lines

lib/Target/Mips/Mips32r6InstrInfo.td

Show First 20 Lines • Show All 944 Lines • ▼ Show 20 Lines
def : MipsInstAlias<"jalrc $rs", (JIALC GPR32Opnd:$rs, 0), 1>, ISA_MIPS32R6, GPR_32; def : MipsInstAlias<"jalrc $rs", (JIALC GPR32Opnd:$rs, 0), 1>, ISA_MIPS32R6, GPR_32;
} }
def : MipsInstAlias<"div $rs, $rt", (DIV GPR32Opnd:$rs, GPR32Opnd:$rs, def : MipsInstAlias<"div $rs, $rt", (DIV GPR32Opnd:$rs, GPR32Opnd:$rs,
GPR32Opnd:$rt)>, ISA_MIPS32R6; GPR32Opnd:$rt)>, ISA_MIPS32R6;
def : MipsInstAlias<"divu $rs, $rt", (DIVU GPR32Opnd:$rs, GPR32Opnd:$rs, def : MipsInstAlias<"divu $rs, $rt", (DIVU GPR32Opnd:$rs, GPR32Opnd:$rs,
GPR32Opnd:$rt)>, ISA_MIPS32R6; GPR32Opnd:$rt)>, ISA_MIPS32R6;
def : MipsInstAlias<"lapc $rd, $imm",
(ADDIUPC GPR32Opnd:$rd, simm19_lsl2:$imm)>, ISA_MIPS32R6;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// Patterns and Pseudo Instructions // Patterns and Pseudo Instructions
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// comparisons supported via another comparison // comparisons supported via another comparison
multiclass Cmp_Pats<ValueType VT, Instruction NOROp, Register ZEROReg> { multiclass Cmp_Pats<ValueType VT, Instruction NOROp, Register ZEROReg> {
▲ Show 20 Lines • Show All 77 Lines • Show Last 20 Lines

test/MC/Disassembler/Mips/micromips32r6/valid.txt

Show All 26 Lines
0x2e 0x56 # CHECK: andi16 $4, $5, 8 0x2e 0x56 # CHECK: andi16 $4, $5, 8
0x46 0x70 # CHECK: not16 $4, $7 0x46 0x70 # CHECK: not16 $4, $7
0x45 0xf9 # CHECK: or16 $3, $7 0x45 0xf9 # CHECK: or16 $3, $7
0x25 0xe0 # CHECK: sll16 $3, $6, 8 0x25 0xe0 # CHECK: sll16 $3, $6, 8
0x25 0xe1 # CHECK: srl16 $3, $6, 8 0x25 0xe1 # CHECK: srl16 $3, $6, 8
0x00 0xa4 0x19 0x10 # CHECK: add $3, $4, $5 0x00 0xa4 0x19 0x10 # CHECK: add $3, $4, $5
0x30 0x64 0x04 0xd2 # CHECK: addiu $3, $4, 1234 0x30 0x64 0x04 0xd2 # CHECK: addiu $3, $4, 1234
0x00 0xa4 0x19 0x50 # CHECK: addu $3, $4, $5 0x00 0xa4 0x19 0x50 # CHECK: addu $3, $4, $5
0x78 0x80 0x00 0x19 # CHECK: addiupc $4, 100 0x78 0x80 0x00 0x19 # CHECK: lapc $4, 100
0x78 0x7f 0x00 0x38 # CHECK: aluipc $3, 56 0x78 0x7f 0x00 0x38 # CHECK: aluipc $3, 56
0x78 0x7e 0xff 0xff # CHECK: auipc $3, -1 0x78 0x7e 0xff 0xff # CHECK: auipc $3, -1
0x00 0x43 0x24 0x1f # CHECK: align $4, $2, $3, 2 0x00 0x43 0x24 0x1f # CHECK: align $4, $2, $3, 2
0x00 0xa4 0x1a 0x50 # CHECK: and $3, $4, $5 0x00 0xa4 0x1a 0x50 # CHECK: and $3, $4, $5
0xd0 0x64 0x04 0xd2 # CHECK: andi $3, $4, 1234 0xd0 0x64 0x04 0xd2 # CHECK: andi $3, $4, 1234
0x10 0x62 0xff 0xe9 # CHECK: aui $3, $2, 65513 0x10 0x62 0xff 0xe9 # CHECK: aui $3, $2, 65513
0x74 0x83 0x00 0x04 # CHECK: beqc $3, $4, 20 0x74 0x83 0x00 0x04 # CHECK: beqc $3, $4, 20
0xf4 0x83 0x00 0x04 # CHECK: bgec $3, $4, 20 0xf4 0x83 0x00 0x04 # CHECK: bgec $3, $4, 20
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test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt

# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r6 | FileCheck %s # RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r6 | FileCheck %s
0x04 0x00 0x42 0x30 # CHECK: andi $2, $2, 4 0x04 0x00 0x42 0x30 # CHECK: andi $2, $2, 4
0x19 0x00 0x80 0xec # CHECK: addiupc $4, 100 0x19 0x00 0x80 0xec # CHECK: lapc $4, 100
0x0a 0x00 0x29 0x25 # CHECK: addiu $9, $9, 10 0x0a 0x00 0x29 0x25 # CHECK: addiu $9, $9, 10
0xa0 0x22 0x43 0x7c # CHECK: align $4, $2, $3, 2 0xa0 0x22 0x43 0x7c # CHECK: align $4, $2, $3, 2
0x38 0x00 0x7f 0xec # CHECK: aluipc $3, 56 0x38 0x00 0x7f 0xec # CHECK: aluipc $3, 56
0xe9 0xff 0x43 0x3c # CHECK: aui $3, $2, 65513 0xe9 0xff 0x43 0x3c # CHECK: aui $3, $2, 65513
0xff 0xff 0x7e 0xec # CHECK: auipc $3, -1 0xff 0xff 0x7e 0xec # CHECK: auipc $3, -1
0x9b 0x14 0x11 0x04 # CHECK: bal 21104 0x9b 0x14 0x11 0x04 # CHECK: bal 21104
0xb8 0x96 0x37 0xe8 # CHECK: balc 14572260 0xb8 0x96 0x37 0xe8 # CHECK: balc 14572260
0xb8 0x96 0x37 0xc8 # CHECK: bc 14572260 0xb8 0x96 0x37 0xc8 # CHECK: bc 14572260
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test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt

Show First 20 Lines • Show All 187 Lines • ▼ Show 20 Lines
0xd8 0x05 0x01 0x00 # CHECK: jic $5, 256 0xd8 0x05 0x01 0x00 # CHECK: jic $5, 256
0xd8 0xa0 0x46 0x90 # CHECK: beqzc $5, 72260 0xd8 0xa0 0x46 0x90 # CHECK: beqzc $5, 72260
0xd8 0x5f 0xff 0xfa # CHECK: beqzc $2, -20 0xd8 0x5f 0xff 0xfa # CHECK: beqzc $2, -20
0xe8 0x37 0x96 0xb8 # CHECK: balc 14572260 0xe8 0x37 0x96 0xb8 # CHECK: balc 14572260
0xec 0x48 0x00 0x43 # CHECK: lwpc $2, 268 0xec 0x48 0x00 0x43 # CHECK: lwpc $2, 268
0xec 0x50 0x00 0x43 # CHECK: lwupc $2, 268 0xec 0x50 0x00 0x43 # CHECK: lwupc $2, 268
0xec 0x7e 0xff 0xff # CHECK: auipc $3, -1 0xec 0x7e 0xff 0xff # CHECK: auipc $3, -1
0xec 0x7f 0x00 0x38 # CHECK: aluipc $3, 56 0xec 0x7f 0x00 0x38 # CHECK: aluipc $3, 56
0xec 0x80 0x00 0x19 # CHECK: addiupc $4, 100 0xec 0x80 0x00 0x19 # CHECK: lapc $4, 100
0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256 0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256
0xf8 0xa0 0x46 0x90 # CHECK: bnezc $5, 72260 0xf8 0xa0 0x46 0x90 # CHECK: bnezc $5, 72260
0xf8 0x5f 0xff 0xfa # CHECK: bnezc $2, -20 0xf8 0x5f 0xff 0xfa # CHECK: bnezc $2, -20

test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt

# RUN: llvm-mc %s -disassemble -triple=mipsel-unknown-linux -mcpu=mips64r6 | FileCheck %s # RUN: llvm-mc %s -disassemble -triple=mipsel-unknown-linux -mcpu=mips64r6 | FileCheck %s
0x0a 0x00 0x29 0x25 # CHECK: addiu $9, $9, 10 0x0a 0x00 0x29 0x25 # CHECK: addiu $9, $9, 10
0x19 0x00 0x80 0xec # CHECK: addiupc $4, 100
0xa0 0x22 0x43 0x7c # CHECK: align $4, $2, $3, 2 0xa0 0x22 0x43 0x7c # CHECK: align $4, $2, $3, 2
0x38 0x00 0x7f 0xec # CHECK: aluipc $3, 56 0x38 0x00 0x7f 0xec # CHECK: aluipc $3, 56
0x04 0x00 0x42 0x30 # CHECK: andi $2, $2, 4 0x04 0x00 0x42 0x30 # CHECK: andi $2, $2, 4
0xe9 0xff 0x43 0x3c # CHECK: aui $3, $2, 65513 0xe9 0xff 0x43 0x3c # CHECK: aui $3, $2, 65513
0xff 0xff 0x7e 0xec # CHECK: auipc $3, -1 0xff 0xff 0x7e 0xec # CHECK: auipc $3, -1
0x9b 0x14 0x11 0x04 # CHECK: bal 21104 0x9b 0x14 0x11 0x04 # CHECK: bal 21104
0xb8 0x96 0x37 0xe8 # CHECK: balc 14572260 0xb8 0x96 0x37 0xe8 # CHECK: balc 14572260
0xb8 0x96 0x37 0xc8 # CHECK: bc 14572260 0xb8 0x96 0x37 0xc8 # CHECK: bc 14572260
▲ Show 20 Lines • Show All 112 Lines • ▼ Show 20 Lines
0x04 0x00 0x60 0x41 # CHECK: evp $zero 0x04 0x00 0x60 0x41 # CHECK: evp $zero
0x09 0xfc 0x80 0x00 # CHECK: jalr.hb $4 0x09 0xfc 0x80 0x00 # CHECK: jalr.hb $4
0x09 0x24 0xa0 0x00 # CHECK: jalr.hb $4, $5 0x09 0x24 0xa0 0x00 # CHECK: jalr.hb $4, $5
0x00 0x00 0x19 0xf8 # CHECK: jalrc $25 0x00 0x00 0x19 0xf8 # CHECK: jalrc $25
0x00 0x01 0x05 0xf8 # CHECK: jialc $5, 256 0x00 0x01 0x05 0xf8 # CHECK: jialc $5, 256
0x00 0x01 0x05 0xd8 # CHECK: jic $5, 256 0x00 0x01 0x05 0xd8 # CHECK: jic $5, 256
0x00 0x00 0x1b 0xd8 # CHECK: jrc $27 0x00 0x00 0x1b 0xd8 # CHECK: jrc $27
0x09 0x04 0x80 0x00 # CHECK: jr.hb $4 0x09 0x04 0x80 0x00 # CHECK: jr.hb $4
0x19 0x00 0x80 0xec # CHECK: lapc $4, 100
0x43 0x0d 0xc8 0x49 # CHECK: ldc2 $8, -701($1) 0x43 0x0d 0xc8 0x49 # CHECK: ldc2 $8, -701($1)
0x48 0x3c 0x58 0xec # CHECK: ldpc $2, 123456 0x48 0x3c 0x58 0xec # CHECK: ldpc $2, 123456
0xb6 0xb3 0x42 0x7e # CHECK: ll $2, -153($18) 0xb6 0xb3 0x42 0x7e # CHECK: ll $2, -153($18)
0x37 0x38 0xe0 0x7f # CHECK: lld $zero, 112($ra) 0x37 0x38 0xe0 0x7f # CHECK: lld $zero, 112($ra)
0xc5 0x10 0x64 0x00 # CHECK: lsa $2, $3, $4, 4 0xc5 0x10 0x64 0x00 # CHECK: lsa $2, $3, $4, 4
0xb7 0x34 0x52 0x49 # CHECK: lwc2 $18, -841($6) 0xb7 0x34 0x52 0x49 # CHECK: lwc2 $18, -841($6)
0x43 0x00 0x48 0xec # CHECK: lwpc $2, 268 0x43 0x00 0x48 0xec # CHECK: lwpc $2, 268
0x43 0x00 0x50 0xec # CHECK: lwupc $2, 268 0x43 0x00 0x50 0xec # CHECK: lwupc $2, 268
▲ Show 20 Lines • Show All 59 Lines • Show Last 20 Lines

test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt

Show First 20 Lines • Show All 212 Lines • ▼ Show 20 Lines
0xd8 0xa0 0x46 0x90 # CHECK: beqzc $5, 72260 0xd8 0xa0 0x46 0x90 # CHECK: beqzc $5, 72260
0xd8 0x5f 0xff 0xfa # CHECK: beqzc $2, -20 0xd8 0x5f 0xff 0xfa # CHECK: beqzc $2, -20
0xe8 0x37 0x96 0xb8 # CHECK: balc 14572260 0xe8 0x37 0x96 0xb8 # CHECK: balc 14572260
0xec 0x48 0x00 0x43 # CHECK: lwpc $2, 268 0xec 0x48 0x00 0x43 # CHECK: lwpc $2, 268
0xec 0x50 0x00 0x43 # CHECK: lwupc $2, 268 0xec 0x50 0x00 0x43 # CHECK: lwupc $2, 268
0xec 0x58 0x3c 0x48 # CHECK: ldpc $2, 123456 0xec 0x58 0x3c 0x48 # CHECK: ldpc $2, 123456
0xec 0x7e 0xff 0xff # CHECK: auipc $3, -1 0xec 0x7e 0xff 0xff # CHECK: auipc $3, -1
0xec 0x7f 0x00 0x38 # CHECK: aluipc $3, 56 0xec 0x7f 0x00 0x38 # CHECK: aluipc $3, 56
0xec 0x80 0x00 0x19 # CHECK: addiupc $4, 100 0xec 0x80 0x00 0x19 # CHECK: lapc $4, 100
0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256 0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256
0xf8 0xa0 0x46 0x90 # CHECK: bnezc $5, 72260 0xf8 0xa0 0x46 0x90 # CHECK: bnezc $5, 72260
0xf8 0x5f 0xff 0xfa # CHECK: bnezc $2, -20 0xf8 0x5f 0xff 0xfa # CHECK: bnezc $2, -20

test/MC/Mips/micromips32r6/invalid-wrong-error.s

Show All 36 Lines# RUN: FileCheck %s < %t1
sdc2 $1, -2049($16) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled sdc2 $1, -2049($16) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
sdc2 $1, 2048($16) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled sdc2 $1, 2048($16) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
sdc2 $1, 8($32) # CHECK: :[[@LINE]]:12: error: expected memory with 16-bit signed offset sdc2 $1, 8($32) # CHECK: :[[@LINE]]:12: error: expected memory with 16-bit signed offset
swc2 $1, -2049($17) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled swc2 $1, -2049($17) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
swc2 $1, 2048($17) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled swc2 $1, 2048($17) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
swc2 $1, 777($32) # CHECK: :[[@LINE]]:12: error: expected memory with 16-bit signed offset swc2 $1, 777($32) # CHECK: :[[@LINE]]:12: error: expected memory with 16-bit signed offset
lwc2 $11, -1025($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled lwc2 $11, -1025($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
lwc2 $11, 1024($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled lwc2 $11, 1024($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
lapc $7, 16777216 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
lapc $6, -16777220 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
lapc $3, 3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
sdardisUnsubmitted
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Provide a negative unencodable number as well.

sdardis: Provide a negative unencodable number as well.
sdardisUnsubmitted
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Sorry about the confusion, simm19_lsl2 does give the correct error message.

These three should be in test/MC/Mips/micromips32r6/invalid.s and should be: error: expected both 19-bit signed immediate and multiple of 4

Also, test -1048580, 1048576 as they're the next multiple of 4 instead of 16777220 / 16777216.

sdardis: Sorry about the confusion, simm19_lsl2 does give the correct error message. These three should…

test/MC/Mips/micromips32r6/relocations.s

# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \ # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \
# RUN: -mattr=micromips | FileCheck %s -check-prefix=CHECK-FIXUP # RUN: -mattr=micromips | FileCheck %s -check-prefix=CHECK-FIXUP
# RUN: llvm-mc %s -filetype=obj -triple=mips-unknown-linux -mcpu=mips32r6 \ # RUN: llvm-mc %s -filetype=obj -triple=mips-unknown-linux -mcpu=mips32r6 \
# RUN: -mattr=micromips | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-ELF # RUN: -mattr=micromips | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-ELF
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# Check that the assembler can handle the documented syntax for fixups. # Check that the assembler can handle the documented syntax for fixups.
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# CHECK-FIXUP: balc bar # encoding: [0b101101AA,A,A,A] # CHECK-FIXUP: balc bar # encoding: [0b101101AA,A,A,A]
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar-4, kind: fixup_MICROMIPS_PC26_S1 # CHECK-FIXUP: value: bar-4, kind: fixup_MICROMIPS_PC26_S1
# CHECK-FIXUP: bc bar # encoding: [0b100101AA,A,A,A] # CHECK-FIXUP: bc bar # encoding: [0b100101AA,A,A,A]
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar-4, kind: fixup_MICROMIPS_PC26_S1 # CHECK-FIXUP: value: bar-4, kind: fixup_MICROMIPS_PC26_S1
# CHECK-FIXUP: addiupc $2, bar # encoding: [0x78,0b01000AAA,A,A] # CHECK-FIXUP: lapc $2, bar # encoding: [0x78,0b01000AAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MICROMIPS_PC19_S2
# CHECK-FIXUP: lapc $2, bar # encoding: [0x78,0b01000AAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MICROMIPS_PC19_S2 # CHECK-FIXUP: value: bar, kind: fixup_MICROMIPS_PC19_S2
# CHECK-FIXUP: lwpc $2, bar # encoding: [0x78,0b01001AAA,A,A] # CHECK-FIXUP: lwpc $2, bar # encoding: [0x78,0b01001AAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MICROMIPS_PC19_S2 # CHECK-FIXUP: value: bar, kind: fixup_MICROMIPS_PC19_S2
# CHECK-FIXUP: beqzc $3, bar # encoding: [0x80,0b011AAAAA,A,A] # CHECK-FIXUP: beqzc $3, bar # encoding: [0x80,0b011AAAAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar-4, kind: fixup_MICROMIPS_PC21_S1 # CHECK-FIXUP: value: bar-4, kind: fixup_MICROMIPS_PC21_S1
# CHECK-FIXUP: bnezc $3, bar # encoding: [0xa0,0b011AAAAA,A,A] # CHECK-FIXUP: bnezc $3, bar # encoding: [0xa0,0b011AAAAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar-4, kind: fixup_MICROMIPS_PC21_S1 # CHECK-FIXUP: value: bar-4, kind: fixup_MICROMIPS_PC21_S1
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# Check that the appropriate relocations were created. # Check that the appropriate relocations were created.
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# CHECK-ELF: Relocations [ # CHECK-ELF: Relocations [
# CHECK-ELF: 0x0 R_MICROMIPS_PC26_S1 bar 0x0 # CHECK-ELF: 0x0 R_MICROMIPS_PC26_S1 bar 0x0
# CHECK-ELF: 0x4 R_MICROMIPS_PC26_S1 bar 0x0 # CHECK-ELF: 0x4 R_MICROMIPS_PC26_S1 bar 0x0
# CHECK-ELF: 0x8 R_MICROMIPS_PC19_S2 bar 0x0 # CHECK-ELF: 0x8 R_MICROMIPS_PC19_S2 bar 0x0
# CHECK-ELF: 0xC R_MICROMIPS_PC19_S2 bar 0x0 # CHECK-ELF: 0xC R_MICROMIPS_PC19_S2 bar 0x0
# CHECK-ELF: 0x10 R_MICROMIPS_PC21_S1 bar 0x0 # CHECK-ELF: 0x10 R_MICROMIPS_PC19_S2 bar 0x0
# CHECK-ELF: 0x14 R_MICROMIPS_PC21_S1 bar 0x0 # CHECK-ELF: 0x14 R_MICROMIPS_PC21_S1 bar 0x0
# CHECK-ELF: 0x18 R_MICROMIPS_PC21_S1 bar 0x0
# CHECK-ELF: ] # CHECK-ELF: ]
balc bar balc bar
bc bar bc bar
addiupc $2,bar addiupc $2,bar
lapc $2,bar
lwpc $2,bar lwpc $2,bar
beqzc $3, bar beqzc $3, bar
bnezc $3, bar bnezc $3, bar

test/MC/Mips/micromips32r6/valid.s

# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips | FileCheck %s # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips | FileCheck %s
.set noat .set noat
add $3, $4, $5 # CHECK: add $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x10] add $3, $4, $5 # CHECK: add $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x10]
addiu $3, $4, 1234 # CHECK: addiu $3, $4, 1234 # encoding: [0x30,0x64,0x04,0xd2] addiu $3, $4, 1234 # CHECK: addiu $3, $4, 1234 # encoding: [0x30,0x64,0x04,0xd2]
addu $3, $4, $5 # CHECK: addu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x50] addu $3, $4, $5 # CHECK: addu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x50]
addiupc $4, 100 # CHECK: addiupc $4, 100 # encoding: [0x78,0x80,0x00,0x19] addiupc $4, 100 # CHECK: lapc $4, 100 # encoding: [0x78,0x80,0x00,0x19]
addiur1sp $7, 4 # CHECK: addiur1sp $7, 4 # encoding: [0x6f,0x83] addiur1sp $7, 4 # CHECK: addiur1sp $7, 4 # encoding: [0x6f,0x83]
addiur2 $6, $7, -1 # CHECK: addiur2 $6, $7, -1 # encoding: [0x6f,0x7e] addiur2 $6, $7, -1 # CHECK: addiur2 $6, $7, -1 # encoding: [0x6f,0x7e]
addiur2 $6, $7, 12 # CHECK: addiur2 $6, $7, 12 # encoding: [0x6f,0x76] addiur2 $6, $7, 12 # CHECK: addiur2 $6, $7, 12 # encoding: [0x6f,0x76]
addius5 $7, -2 # CHECK: addius5 $7, -2 # encoding: [0x4c,0xfc] addius5 $7, -2 # CHECK: addius5 $7, -2 # encoding: [0x4c,0xfc]
addiusp -1028 # CHECK: addiusp -1028 # encoding: [0x4f,0xff] addiusp -1028 # CHECK: addiusp -1028 # encoding: [0x4f,0xff]
addiusp -1032 # CHECK: addiusp -1032 # encoding: [0x4f,0xfd] addiusp -1032 # CHECK: addiusp -1032 # encoding: [0x4f,0xfd]
addiusp 1024 # CHECK: addiusp 1024 # encoding: [0x4c,0x01] addiusp 1024 # CHECK: addiusp 1024 # encoding: [0x4c,0x01]
addiusp 1028 # CHECK: addiusp 1028 # encoding: [0x4c,0x03] addiusp 1028 # CHECK: addiusp 1028 # encoding: [0x4c,0x03]
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips | FileCheck %s
di $15 # CHECK: di $15 # encoding: [0x00,0x0f,0x47,0x7c] di $15 # CHECK: di $15 # encoding: [0x00,0x0f,0x47,0x7c]
eret # CHECK: eret # encoding: [0x00,0x00,0xf3,0x7c] eret # CHECK: eret # encoding: [0x00,0x00,0xf3,0x7c]
eretnc # CHECK: eretnc # encoding: [0x00,0x01,0xf3,0x7c] eretnc # CHECK: eretnc # encoding: [0x00,0x01,0xf3,0x7c]
jalr $9 # CHECK: jalr $9 # encoding: [0x45,0x2b] jalr $9 # CHECK: jalr $9 # encoding: [0x45,0x2b]
jialc $5, 256 # CHECK: jialc $5, 256 # encoding: [0x80,0x05,0x01,0x00] jialc $5, 256 # CHECK: jialc $5, 256 # encoding: [0x80,0x05,0x01,0x00]
jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xa0,0x05,0x01,0x00] jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xa0,0x05,0x01,0x00]
jrc16 $9 # CHECK: jrc16 $9 # encoding: [0x45,0x23] jrc16 $9 # CHECK: jrc16 $9 # encoding: [0x45,0x23]
jrcaddiusp 20 # CHECK: jrcaddiusp 20 # encoding: [0x44,0xb3] jrcaddiusp 20 # CHECK: jrcaddiusp 20 # encoding: [0x44,0xb3]
lapc $4, 100 # CHECK: lapc $4, 100 # encoding: [0x78,0x80,0x00,0x19]
lapc $7, 16777212 # CHECK: lapc $7, 16777212 # encoding: [0x7b,0xbf,0xff,0xff]
lapc $7, -16777216 # CHECK: lapc $7, -16777216 # encoding: [0x7b,0xc0,0x00,0x00]
sdardisUnsubmitted
Not Done
ReplyInline Actions

The limits should be [-1048576, 1048572].

sdardis: The limits should be [-1048576, 1048572].
lh $2, 8($4) # CHECK: lh $2, 8($4) # encoding: [0x3c,0x44,0x00,0x08] lh $2, 8($4) # CHECK: lh $2, 8($4) # encoding: [0x3c,0x44,0x00,0x08]
lhe $4, 8($2) # CHECK: lhe $4, 8($2) # encoding: [0x60,0x82,0x6a,0x08] lhe $4, 8($2) # CHECK: lhe $4, 8($2) # encoding: [0x60,0x82,0x6a,0x08]
lhu $4, 8($2) # CHECK: lhu $4, 8($2) # encoding: [0x34,0x82,0x00,0x08] lhu $4, 8($2) # CHECK: lhu $4, 8($2) # encoding: [0x34,0x82,0x00,0x08]
lhue $4, 8($2) # CHECK: lhue $4, 8($2) # encoding: [0x60,0x82,0x62,0x08] lhue $4, 8($2) # CHECK: lhue $4, 8($2) # encoding: [0x60,0x82,0x62,0x08]
lsa $2, $3, $4, 3 # CHECK: lsa $2, $3, $4, 3 # encoding: [0x00,0x43,0x24,0x0f] lsa $2, $3, $4, 3 # CHECK: lsa $2, $3, $4, 3 # encoding: [0x00,0x43,0x24,0x0f]
lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0x78,0x48,0x00,0x43] lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0x78,0x48,0x00,0x43]
lwm $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22] lwm $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22]
lwm16 $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22] lwm16 $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22]
▲ Show 20 Lines • Show All 313 Lines • Show Last 20 Lines

test/MC/Mips/micromips64r6/relocations.s

# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r6 \ # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r6 \
# RUN: -mattr=micromips | FileCheck %s -check-prefix=CHECK-FIXUP # RUN: -mattr=micromips | FileCheck %s -check-prefix=CHECK-FIXUP
# RUN: llvm-mc %s -filetype=obj -triple=mips-unknown-linux -mcpu=mips64r6 \ # RUN: llvm-mc %s -filetype=obj -triple=mips-unknown-linux -mcpu=mips64r6 \
# RUN: -mattr=micromips | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-ELF # RUN: -mattr=micromips | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-ELF
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# Check that the assembler can handle the documented syntax for fixups. # Check that the assembler can handle the documented syntax for fixups.
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# CHECK-FIXUP: balc bar # encoding: [0b101101AA,A,A,A] # CHECK-FIXUP: balc bar # encoding: [0b101101AA,A,A,A]
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar-4, kind: fixup_MICROMIPS_PC26_S1 # CHECK-FIXUP: value: bar-4, kind: fixup_MICROMIPS_PC26_S1
# CHECK-FIXUP: bc bar # encoding: [0b100101AA,A,A,A] # CHECK-FIXUP: bc bar # encoding: [0b100101AA,A,A,A]
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar-4, kind: fixup_MICROMIPS_PC26_S1 # CHECK-FIXUP: value: bar-4, kind: fixup_MICROMIPS_PC26_S1
# CHECK-FIXUP: addiupc $2, bar # encoding: [0x78,0b01000AAA,A,A] # CHECK-FIXUP: lapc $2, bar # encoding: [0x78,0b01000AAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MICROMIPS_PC19_S2
# CHECK-FIXUP: lapc $2, bar # encoding: [0x78,0b01000AAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MICROMIPS_PC19_S2 # CHECK-FIXUP: value: bar, kind: fixup_MICROMIPS_PC19_S2
# CHECK-FIXUP: lwpc $2, bar # encoding: [0x78,0b01001AAA,A,A] # CHECK-FIXUP: lwpc $2, bar # encoding: [0x78,0b01001AAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MICROMIPS_PC19_S2 # CHECK-FIXUP: value: bar, kind: fixup_MICROMIPS_PC19_S2
# CHECK-FIXUP: ldpc $2, bar # encoding: [0x78,0b010110AA,A,A] # CHECK-FIXUP: ldpc $2, bar # encoding: [0x78,0b010110AA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MICROMIPS_PC18_S3 # CHECK-FIXUP: value: bar, kind: fixup_MICROMIPS_PC18_S3
# CHECK-FIXUP: beqzc $3, bar # encoding: [0x80,0b011AAAAA,A,A] # CHECK-FIXUP: beqzc $3, bar # encoding: [0x80,0b011AAAAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar-4, kind: fixup_MICROMIPS_PC21_S1 # CHECK-FIXUP: value: bar-4, kind: fixup_MICROMIPS_PC21_S1
# CHECK-FIXUP: bnezc $3, bar # encoding: [0xa0,0b011AAAAA,A,A] # CHECK-FIXUP: bnezc $3, bar # encoding: [0xa0,0b011AAAAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar-4, kind: fixup_MICROMIPS_PC21_S1 # CHECK-FIXUP: value: bar-4, kind: fixup_MICROMIPS_PC21_S1
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# Check that the appropriate relocations were created. # Check that the appropriate relocations were created.
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# CHECK-ELF: Relocations [ # CHECK-ELF: Relocations [
# CHECK-ELF: 0x0 R_MICROMIPS_PC26_S1 bar 0x0 # CHECK-ELF: 0x0 R_MICROMIPS_PC26_S1 bar 0x0
# CHECK-ELF: 0x4 R_MICROMIPS_PC26_S1 bar 0x0 # CHECK-ELF: 0x4 R_MICROMIPS_PC26_S1 bar 0x0
# CHECK-ELF: 0x8 R_MICROMIPS_PC19_S2 bar 0x0 # CHECK-ELF: 0x8 R_MICROMIPS_PC19_S2 bar 0x0
# CHECK-ELF: 0xC R_MICROMIPS_PC19_S2 bar 0x0 # CHECK-ELF: 0xC R_MICROMIPS_PC19_S2 bar 0x0
# CHECK-ELF: 0x10 R_MICROMIPS_PC18_S3 bar 0x0 # CHECK-ELF: 0x10 R_MICROMIPS_PC19_S2 bar 0x0
# CHECK-ELF: 0x14 R_MICROMIPS_PC21_S1 bar 0x0 # CHECK-ELF: 0x14 R_MICROMIPS_PC18_S3 bar 0x0
# CHECK-ELF: 0x18 R_MICROMIPS_PC21_S1 bar 0x0 # CHECK-ELF: 0x18 R_MICROMIPS_PC21_S1 bar 0x0
# CHECK-ELF: 0x1C R_MICROMIPS_PC21_S1 bar 0x0
# CHECK-ELF: ] # CHECK-ELF: ]
balc bar balc bar
bc bar bc bar
addiupc $2,bar addiupc $2,bar
lapc $2,bar
lwpc $2,bar lwpc $2,bar
ldpc $2, bar ldpc $2, bar
beqzc $3, bar beqzc $3, bar
bnezc $3, bar bnezc $3, bar

test/MC/Mips/mips32r6/relocations.s

# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \ # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \
# RUN: | FileCheck %s -check-prefix=CHECK-FIXUP # RUN: | FileCheck %s -check-prefix=CHECK-FIXUP
# RUN: llvm-mc %s -filetype=obj -triple=mips-unknown-linux -mcpu=mips32r6 \ # RUN: llvm-mc %s -filetype=obj -triple=mips-unknown-linux -mcpu=mips32r6 \
# RUN: | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-ELF # RUN: | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-ELF
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# Check that the assembler can handle the documented syntax for fixups. # Check that the assembler can handle the documented syntax for fixups.
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# CHECK-FIXUP: addiupc $2, bar # encoding: [0xec,0b01000AAA,A,A] # CHECK-FIXUP: lapc $2, bar # encoding: [0xec,0b01000AAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2 # CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2
# CHECK-FIXUP: beqc $5, $6, bar # encoding: [0x20,0xa6,A,A] # CHECK-FIXUP: beqc $5, $6, bar # encoding: [0x20,0xa6,A,A]
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar-4, kind: fixup_Mips_PC16 # CHECK-FIXUP: value: bar-4, kind: fixup_Mips_PC16
# CHECK-FIXUP: bnec $5, $6, bar # encoding: [0x60,0xa6,A,A] # CHECK-FIXUP: bnec $5, $6, bar # encoding: [0x60,0xa6,A,A]
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar-4, kind: fixup_Mips_PC16 # CHECK-FIXUP: value: bar-4, kind: fixup_Mips_PC16
Show All 12 Lines
# CHECK-FIXUP: aluipc $2, %pcrel_hi(bar) # encoding: [0xec,0x5f,A,A] # CHECK-FIXUP: aluipc $2, %pcrel_hi(bar) # encoding: [0xec,0x5f,A,A]
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: %pcrel_hi(bar), # CHECK-FIXUP: value: %pcrel_hi(bar),
# CHECK-FIXUP: kind: fixup_MIPS_PCHI16 # CHECK-FIXUP: kind: fixup_MIPS_PCHI16
# CHECK-FIXUP: addiu $2, $2, %pcrel_lo(bar) # encoding: [0x24,0x42,A,A] # CHECK-FIXUP: addiu $2, $2, %pcrel_lo(bar) # encoding: [0x24,0x42,A,A]
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: %pcrel_lo(bar), # CHECK-FIXUP: value: %pcrel_lo(bar),
# CHECK-FIXUP: kind: fixup_MIPS_PCLO16 # CHECK-FIXUP: kind: fixup_MIPS_PCLO16
# CHECK-FIXUP: lapc $2, bar # encoding: [0xec,0b01000AAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2
# CHECK-FIXUP: lwpc $2, bar # encoding: [0xec,0b01001AAA,A,A] # CHECK-FIXUP: lwpc $2, bar # encoding: [0xec,0b01001AAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2 # CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2
# CHECK-FIXUP: lwupc $2, bar # encoding: [0xec,0b01010AAA,A,A] # CHECK-FIXUP: lwupc $2, bar # encoding: [0xec,0b01010AAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2 # CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# Check that the appropriate relocations were created. # Check that the appropriate relocations were created.
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# CHECK-ELF: Relocations [ # CHECK-ELF: Relocations [
# CHECK-ELF: 0x0 R_MIPS_PC19_S2 bar 0x0 # CHECK-ELF: 0x0 R_MIPS_PC19_S2 bar 0x0
# CHECK-ELF: 0x4 R_MIPS_PC16 bar 0x0 # CHECK-ELF: 0x4 R_MIPS_PC16 bar 0x0
# CHECK-ELF: 0x8 R_MIPS_PC16 bar 0x0 # CHECK-ELF: 0x8 R_MIPS_PC16 bar 0x0
# CHECK-ELF: 0xC R_MIPS_PC21_S2 bar 0x0 # CHECK-ELF: 0xC R_MIPS_PC21_S2 bar 0x0
# CHECK-ELF: 0x10 R_MIPS_PC21_S2 bar 0x0 # CHECK-ELF: 0x10 R_MIPS_PC21_S2 bar 0x0
# CHECK-ELF: 0x14 R_MIPS_PC26_S2 bar 0x0 # CHECK-ELF: 0x14 R_MIPS_PC26_S2 bar 0x0
# CHECK-ELF: 0x18 R_MIPS_PC26_S2 bar 0x0 # CHECK-ELF: 0x18 R_MIPS_PC26_S2 bar 0x0
# CHECK-ELF: 0x1C R_MIPS_PCHI16 bar 0x0 # CHECK-ELF: 0x1C R_MIPS_PCHI16 bar 0x0
# CHECK-ELF: 0x20 R_MIPS_PCLO16 bar 0x0 # CHECK-ELF: 0x20 R_MIPS_PCLO16 bar 0x0
# CHECK-ELF: 0x24 R_MIPS_PC19_S2 bar 0x0 # CHECK-ELF: 0x24 R_MIPS_PC19_S2 bar 0x0
# CHECK-ELF: 0x28 R_MIPS_PC19_S2 bar 0x0 # CHECK-ELF: 0x28 R_MIPS_PC19_S2 bar 0x0
# CHECK-ELF: 0x2C R_MIPS_PC19_S2 bar 0x0
# CHECK-ELF: ] # CHECK-ELF: ]
addiupc $2,bar addiupc $2,bar
beqc $5, $6, bar beqc $5, $6, bar
bnec $5, $6, bar bnec $5, $6, bar
beqzc $9, bar beqzc $9, bar
bnezc $9, bar bnezc $9, bar
balc bar balc bar
bc bar bc bar
aluipc $2, %pcrel_hi(bar) aluipc $2, %pcrel_hi(bar)
addiu $2, $2, %pcrel_lo(bar) addiu $2, $2, %pcrel_lo(bar)
lapc $2,bar
lwpc $2,bar lwpc $2,bar
lwupc $2,bar lwupc $2,bar

test/MC/Mips/mips32r6/valid.s

Show All 10 Lines
# appropriately for each branch instruction # appropriately for each branch instruction
# #
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 2> %t0 | FileCheck %s # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 2> %t0 | FileCheck %s
# RUN: FileCheck %s -check-prefix=WARNING < %t0 # RUN: FileCheck %s -check-prefix=WARNING < %t0
a: a:
.set noat .set noat
# FIXME: Add the instructions carried forward from older ISA's # FIXME: Add the instructions carried forward from older ISA's
and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04] and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04]
addiupc $4, 100 # CHECK: addiupc $4, 100 # encoding: [0xec,0x80,0x00,0x19] addiupc $4, 100 # CHECK: lapc $4, 100 # encoding: [0xec,0x80,0x00,0x19]
addu $9,10 # CHECK: addiu $9, $9, 10 # encoding: [0x25,0x29,0x00,0x0a] addu $9,10 # CHECK: addiu $9, $9, 10 # encoding: [0x25,0x29,0x00,0x0a]
align $4, $2, $3, 2 # CHECK: align $4, $2, $3, 2 # encoding: [0x7c,0x43,0x22,0xa0] align $4, $2, $3, 2 # CHECK: align $4, $2, $3, 2 # encoding: [0x7c,0x43,0x22,0xa0]
aluipc $3, 56 # CHECK: aluipc $3, 56 # encoding: [0xec,0x7f,0x00,0x38] aluipc $3, 56 # CHECK: aluipc $3, 56 # encoding: [0xec,0x7f,0x00,0x38]
aui $3, $2, 23 # CHECK: aui $3, $2, 23 # encoding: [0x3c,0x43,0x00,0x17] aui $3, $2, 23 # CHECK: aui $3, $2, 23 # encoding: [0x3c,0x43,0x00,0x17]
auipc $3, -1 # CHECK: auipc $3, -1 # encoding: [0xec,0x7e,0xff,0xff] auipc $3, -1 # CHECK: auipc $3, -1 # encoding: [0xec,0x7e,0xff,0xff]
bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
balc 14572256 # CHECK: balc 14572256 # encoding: [0xe8,0x37,0x96,0xb8] balc 14572256 # CHECK: balc 14572256 # encoding: [0xe8,0x37,0x96,0xb8]
bc 14572256 # CHECK: bc 14572256 # encoding: [0xc8,0x37,0x96,0xb8] bc 14572256 # CHECK: bc 14572256 # encoding: [0xc8,0x37,0x96,0xb8]
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eret eret
eretnc # CHECK: eretnc # encoding: [0x42,0x00,0x00,0x58] eretnc # CHECK: eretnc # encoding: [0x42,0x00,0x00,0x58]
evp $5 # CHECK: evp $5 # encoding: [0x41,0x65,0x00,0x04] evp $5 # CHECK: evp $5 # encoding: [0x41,0x65,0x00,0x04]
evp # CHECK: evp $zero # encoding: [0x41,0x60,0x00,0x04] evp # CHECK: evp $zero # encoding: [0x41,0x60,0x00,0x04]
jialc $5, 256 # CHECK: jialc $5, 256 # encoding: [0xf8,0x05,0x01,0x00] jialc $5, 256 # CHECK: jialc $5, 256 # encoding: [0xf8,0x05,0x01,0x00]
jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xd8,0x05,0x01,0x00] jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xd8,0x05,0x01,0x00]
l.s $f2, 8($3) # CHECK: lwc1 $f2, 8($3) # encoding: [0xc4,0x62,0x00,0x08] l.s $f2, 8($3) # CHECK: lwc1 $f2, 8($3) # encoding: [0xc4,0x62,0x00,0x08]
l.d $f2, 8($3) # CHECK: ldc1 $f2, 8($3) # encoding: [0xd4,0x62,0x00,0x08] l.d $f2, 8($3) # CHECK: ldc1 $f2, 8($3) # encoding: [0xd4,0x62,0x00,0x08]
lapc $4, 100 # CHECK: lapc $4, 100 # encoding: [0xec,0x80,0x00,0x19]
lsa $2, $3, $4, 3 # CHECK: lsa $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0x85] lsa $2, $3, $4, 3 # CHECK: lsa $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0x85]
lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0xec,0x48,0x00,0x43] lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0xec,0x48,0x00,0x43]
lwupc $2,268 # CHECK: lwupc $2, 268 # encoding: [0xec,0x50,0x00,0x43] lwupc $2,268 # CHECK: lwupc $2, 268 # encoding: [0xec,0x50,0x00,0x43]
mfc0 $8,$15,1 # CHECK: mfc0 $8, $15, 1 # encoding: [0x40,0x08,0x78,0x01] mfc0 $8,$15,1 # CHECK: mfc0 $8, $15, 1 # encoding: [0x40,0x08,0x78,0x01]
mod $2,$3,$4 # CHECK: mod $2, $3, $4 # encoding: [0x00,0x64,0x10,0xda] mod $2,$3,$4 # CHECK: mod $2, $3, $4 # encoding: [0x00,0x64,0x10,0xda]
modu $2,$3,$4 # CHECK: modu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdb] modu $2,$3,$4 # CHECK: modu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdb]
move $a0,$a3 # CHECK: move $4, $7 # encoding: [0x00,0xe0,0x20,0x25] move $a0,$a3 # CHECK: move $4, $7 # encoding: [0x00,0xe0,0x20,0x25]
move $s5,$a0 # CHECK: move $21, $4 # encoding: [0x00,0x80,0xa8,0x25] move $s5,$a0 # CHECK: move $21, $4 # encoding: [0x00,0x80,0xa8,0x25]
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test/MC/Mips/mips64r6/relocations.s

# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 \ # RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 \
# RUN: | FileCheck %s -check-prefix=CHECK-FIXUP # RUN: | FileCheck %s -check-prefix=CHECK-FIXUP
# RUN: llvm-mc %s -filetype=obj -triple=mips64-unknown-linux -mcpu=mips64r6 \ # RUN: llvm-mc %s -filetype=obj -triple=mips64-unknown-linux -mcpu=mips64r6 \
# RUN: | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-ELF # RUN: | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-ELF
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# Check that the assembler can handle the documented syntax for fixups. # Check that the assembler can handle the documented syntax for fixups.
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# CHECK-FIXUP: addiupc $2, bar # encoding: [0xec,0b01000AAA,A,A] # CHECK-FIXUP: lapc $2, bar # encoding: [0xec,0b01000AAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2 # CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2
# CHECK-FIXUP: beqc $5, $6, bar # encoding: [0x20,0xa6,A,A] # CHECK-FIXUP: beqc $5, $6, bar # encoding: [0x20,0xa6,A,A]
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar-4, kind: fixup_Mips_PC16 # CHECK-FIXUP: value: bar-4, kind: fixup_Mips_PC16
# CHECK-FIXUP: bnec $5, $6, bar # encoding: [0x60,0xa6,A,A] # CHECK-FIXUP: bnec $5, $6, bar # encoding: [0x60,0xa6,A,A]
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar-4, kind: fixup_Mips_PC16 # CHECK-FIXUP: value: bar-4, kind: fixup_Mips_PC16
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# CHECK-FIXUP: aluipc $2, %pcrel_hi(bar) # encoding: [0xec,0x5f,A,A] # CHECK-FIXUP: aluipc $2, %pcrel_hi(bar) # encoding: [0xec,0x5f,A,A]
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: %pcrel_hi(bar), # CHECK-FIXUP: value: %pcrel_hi(bar),
# CHECK-FIXUP: kind: fixup_MIPS_PCHI16 # CHECK-FIXUP: kind: fixup_MIPS_PCHI16
# CHECK-FIXUP: addiu $2, $2, %pcrel_lo(bar) # encoding: [0x24,0x42,A,A] # CHECK-FIXUP: addiu $2, $2, %pcrel_lo(bar) # encoding: [0x24,0x42,A,A]
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: %pcrel_lo(bar), # CHECK-FIXUP: value: %pcrel_lo(bar),
# CHECK-FIXUP: kind: fixup_MIPS_PCLO16 # CHECK-FIXUP: kind: fixup_MIPS_PCLO16
# CHECK-FIXUP: lapc $2, bar # encoding: [0xec,0b01000AAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2
# CHECK-FIXUP: ldpc $2, bar # encoding: [0xec,0b010110AA,A,A] # CHECK-FIXUP: ldpc $2, bar # encoding: [0xec,0b010110AA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, # CHECK-FIXUP: value: bar,
# CHECK-FIXUP: kind: fixup_Mips_PC18_S3 # CHECK-FIXUP: kind: fixup_Mips_PC18_S3
# CHECK-FIXUP: lwpc $2, bar # encoding: [0xec,0b01001AAA,A,A] # CHECK-FIXUP: lwpc $2, bar # encoding: [0xec,0b01001AAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2 # CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2
# CHECK-FIXUP: lwupc $2, bar # encoding: [0xec,0b01010AAA,A,A] # CHECK-FIXUP: lwupc $2, bar # encoding: [0xec,0b01010AAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2 # CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# Check that the appropriate relocations were created. # Check that the appropriate relocations were created.
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# CHECK-ELF: Relocations [ # CHECK-ELF: Relocations [
# CHECK-ELF: 0x0 R_MIPS_PC19_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0 # CHECK-ELF: 0x0 R_MIPS_PC19_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0
# CHECK-ELF: 0x4 R_MIPS_PC16/R_MIPS_NONE/R_MIPS_NONE bar 0xFFFFFFFFFFFFFFFC # CHECK-ELF: 0x4 R_MIPS_PC16/R_MIPS_NONE/R_MIPS_NONE bar 0xFFFFFFFFFFFFFFFC
# CHECK-ELF: 0x8 R_MIPS_PC16/R_MIPS_NONE/R_MIPS_NONE bar 0xFFFFFFFFFFFFFFFC # CHECK-ELF: 0x8 R_MIPS_PC16/R_MIPS_NONE/R_MIPS_NONE bar 0xFFFFFFFFFFFFFFFC
# CHECK-ELF: 0xC R_MIPS_PC21_S2/R_MIPS_NONE/R_MIPS_NONE bar 0xFFFFFFFFFFFFFFFC # CHECK-ELF: 0xC R_MIPS_PC21_S2/R_MIPS_NONE/R_MIPS_NONE bar 0xFFFFFFFFFFFFFFFC
# CHECK-ELF: 0x10 R_MIPS_PC21_S2/R_MIPS_NONE/R_MIPS_NONE bar 0xFFFFFFFFFFFFFFFC # CHECK-ELF: 0x10 R_MIPS_PC21_S2/R_MIPS_NONE/R_MIPS_NONE bar 0xFFFFFFFFFFFFFFFC
# CHECK-ELF: 0x14 R_MIPS_PC26_S2/R_MIPS_NONE/R_MIPS_NONE bar 0xFFFFFFFFFFFFFFFC # CHECK-ELF: 0x14 R_MIPS_PC26_S2/R_MIPS_NONE/R_MIPS_NONE bar 0xFFFFFFFFFFFFFFFC
# CHECK-ELF: 0x18 R_MIPS_PC26_S2/R_MIPS_NONE/R_MIPS_NONE bar 0xFFFFFFFFFFFFFFFC # CHECK-ELF: 0x18 R_MIPS_PC26_S2/R_MIPS_NONE/R_MIPS_NONE bar 0xFFFFFFFFFFFFFFFC
# CHECK-ELF: 0x1C R_MIPS_PCHI16/R_MIPS_NONE/R_MIPS_NONE bar 0x0 # CHECK-ELF: 0x1C R_MIPS_PCHI16/R_MIPS_NONE/R_MIPS_NONE bar 0x0
# CHECK-ELF: 0x20 R_MIPS_PCLO16/R_MIPS_NONE/R_MIPS_NONE bar 0x0 # CHECK-ELF: 0x20 R_MIPS_PCLO16/R_MIPS_NONE/R_MIPS_NONE bar 0x0
# CHECK-ELF: 0x24 R_MIPS_PC18_S3/R_MIPS_NONE/R_MIPS_NONE bar 0x0 # CHECK-ELF: 0x24 R_MIPS_PC19_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0
# CHECK-ELF: 0x28 R_MIPS_PC19_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0 # CHECK-ELF: 0x28 R_MIPS_PC18_S3/R_MIPS_NONE/R_MIPS_NONE bar 0x0
# CHECK-ELF: 0x2C R_MIPS_PC19_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0 # CHECK-ELF: 0x2C R_MIPS_PC19_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0
# CHECK-ELF: 0x30 R_MIPS_PC19_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0
# CHECK-ELF: ] # CHECK-ELF: ]
addiupc $2,bar addiupc $2,bar
beqc $5, $6, bar beqc $5, $6, bar
bnec $5, $6, bar bnec $5, $6, bar
beqzc $9, bar beqzc $9, bar
bnezc $9, bar bnezc $9, bar
balc bar balc bar
bc bar bc bar
aluipc $2, %pcrel_hi(bar) aluipc $2, %pcrel_hi(bar)
addiu $2, $2, %pcrel_lo(bar) addiu $2, $2, %pcrel_lo(bar)
lapc $2,bar
ldpc $2,bar ldpc $2,bar
lwpc $2,bar lwpc $2,bar
lwupc $2,bar lwupc $2,bar

test/MC/Mips/mips64r6/valid.s

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# rs > rt # rs > rt
# appropriately for each branch instruction # appropriately for each branch instruction
# #
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r6 2> %t0 | FileCheck %s # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r6 2> %t0 | FileCheck %s
# RUN: FileCheck %s -check-prefix=WARNING < %t0 # RUN: FileCheck %s -check-prefix=WARNING < %t0
a: a:
.set noat .set noat
# FIXME: Add the instructions carried forward from older ISA's # FIXME: Add the instructions carried forward from older ISA's
addiupc $4, 100 # CHECK: addiupc $4, 100 # encoding: [0xec,0x80,0x00,0x19] addiupc $4, 100 # CHECK: lapc $4, 100 # encoding: [0xec,0x80,0x00,0x19]
addu $9,10 # CHECK: addiu $9, $9, 10 # encoding: [0x25,0x29,0x00,0x0a] addu $9,10 # CHECK: addiu $9, $9, 10 # encoding: [0x25,0x29,0x00,0x0a]
align $4, $2, $3, 2 # CHECK: align $4, $2, $3, 2 # encoding: [0x7c,0x43,0x22,0xa0] align $4, $2, $3, 2 # CHECK: align $4, $2, $3, 2 # encoding: [0x7c,0x43,0x22,0xa0]
aluipc $3, 56 # CHECK: aluipc $3, 56 # encoding: [0xec,0x7f,0x00,0x38] aluipc $3, 56 # CHECK: aluipc $3, 56 # encoding: [0xec,0x7f,0x00,0x38]
and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04] and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04]
aui $3, $2, 23 # CHECK: aui $3, $2, 23 # encoding: [0x3c,0x43,0x00,0x17] aui $3, $2, 23 # CHECK: aui $3, $2, 23 # encoding: [0x3c,0x43,0x00,0x17]
auipc $3, -1 # CHECK: auipc $3, -1 # encoding: [0xec,0x7e,0xff,0xff] auipc $3, -1 # CHECK: auipc $3, -1 # encoding: [0xec,0x7e,0xff,0xff]
bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
balc 14572256 # CHECK: balc 14572256 # encoding: [0xe8,0x37,0x96,0xb8] balc 14572256 # CHECK: balc 14572256 # encoding: [0xe8,0x37,0x96,0xb8]
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jrc $27 # CHECK: jrc $27 # encoding: [0xd8,0x1b,0x00,0x00] jrc $27 # CHECK: jrc $27 # encoding: [0xd8,0x1b,0x00,0x00]
jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09] jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09]
jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09] jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09]
jalrc $25 # CHECK: jalrc $25 # encoding: [0xf8,0x19,0x00,0x00] jalrc $25 # CHECK: jalrc $25 # encoding: [0xf8,0x19,0x00,0x00]
jialc $5, 256 # CHECK: jialc $5, 256 # encoding: [0xf8,0x05,0x01,0x00] jialc $5, 256 # CHECK: jialc $5, 256 # encoding: [0xf8,0x05,0x01,0x00]
jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xd8,0x05,0x01,0x00] jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xd8,0x05,0x01,0x00]
l.s $f2, 8($3) # CHECK: lwc1 $f2, 8($3) # encoding: [0xc4,0x62,0x00,0x08] l.s $f2, 8($3) # CHECK: lwc1 $f2, 8($3) # encoding: [0xc4,0x62,0x00,0x08]
l.d $f2, 8($3) # CHECK: ldc1 $f2, 8($3) # encoding: [0xd4,0x62,0x00,0x08] l.d $f2, 8($3) # CHECK: ldc1 $f2, 8($3) # encoding: [0xd4,0x62,0x00,0x08]
lapc $4, 100 # CHECK: lapc $4, 100 # encoding: [0xec,0x80,0x00,0x19]
ldc2 $8, -701($at) # CHECK: ldc2 $8, -701($1) # encoding: [0x49,0xc8,0x0d,0x43] ldc2 $8, -701($at) # CHECK: ldc2 $8, -701($1) # encoding: [0x49,0xc8,0x0d,0x43]
ldpc $2,123456 # CHECK: ldpc $2, 123456 # encoding: [0xec,0x58,0x3c,0x48] ldpc $2,123456 # CHECK: ldpc $2, 123456 # encoding: [0xec,0x58,0x3c,0x48]
ll $v0,-153($s2) # CHECK: ll $2, -153($18) # encoding: [0x7e,0x42,0xb3,0xb6] ll $v0,-153($s2) # CHECK: ll $2, -153($18) # encoding: [0x7e,0x42,0xb3,0xb6]
lld $zero,112($ra) # CHECK: lld $zero, 112($ra) # encoding: [0x7f,0xe0,0x38,0x37] lld $zero,112($ra) # CHECK: lld $zero, 112($ra) # encoding: [0x7f,0xe0,0x38,0x37]
lsa $2, $3, $4, 3 # CHECK: lsa $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0x85] lsa $2, $3, $4, 3 # CHECK: lsa $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0x85]
lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0x49,0x52,0x34,0xb7] lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0x49,0x52,0x34,0xb7]
lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0xec,0x48,0x00,0x43] lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0xec,0x48,0x00,0x43]
lwupc $2,268 # CHECK: lwupc $2, 268 # encoding: [0xec,0x50,0x00,0x43] lwupc $2,268 # CHECK: lwupc $2, 268 # encoding: [0xec,0x50,0x00,0x43]
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