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Differential D35882

[TargetParser] Use enum classes for various ARM kind enums.
ClosedPublic

Authored by fhahn on Jul 26 2017, 2:29 AM.

Details

Reviewers
rengolin
javed.absar
chandlerc
rovka
Commits
rG67ddd1d08f3d: [TargetParser] Use enum classes for various ARM kind enums.
rL309287: [TargetParser] Use enum classes for various ARM kind enums.
Summary

Using c++11 enum classes ensures that only valid enum values are used
for ArchKind, ProfileKind, VersionKind and ISAKind. This removes the
need for checks that the provided values map to a proper enum value,
allows us to get rid of AK_LAST and prevents comparing values from
different enums. It also removes a bunch of static_cast
from unsigned to enum values and vice versa, at the cost of introducing
static casts to access AArch64ARCHNames and ARMARCHNames by ArchKind.

FPUKind and ArchExtKind are the only remaining old-style enum in
TargetParser.h. I think it's beneficial to keep ArchExtKind as old-style
enum, but FPUKind can be converted too, but this patch is quite big, so
could do this in a follow-up patch. I could also split this patch up a
bit, if people would prefer that.

Diff Detail

Event Timeline

fhahn created this revision.Jul 26 2017, 2:29 AM
Herald added subscribers: kristof.beyls, aemerson. · View Herald TranscriptJul 26 2017, 2:29 AM
fhahn added a comment.Jul 26 2017, 2:29 AM

This commit should not change any existing functionality, but I think technically it's not really a NFC, as it restricts the APIs of the functions taking various enum values as unsigned previously.

fhahn mentioned this in D35884: Update to use enum classes for various ARM *Kind enums.Jul 26 2017, 2:35 AM
javed.absar edited edge metadata.Jul 26 2017, 8:27 PM

Looks like a nice clean-up.
Its a pity we still need 'invalid' despite using enum class.

LGTM, but will wait for others to comment.

fhahn added a comment.Jul 26 2017, 10:13 PM

Thanks Javed! I think we may be able to get rid of INVALID, after this change goes in, by doing the validation early once. I'll try to look into this after this one went in.

fhahn added a reviewer: rovka.Jul 27 2017, 2:00 AM
rovka added inline comments.Jul 27 2017, 5:15 AM
lib/Support/TargetParser.cpp
380

This can still return INVALID, I don't think you should remove the check just yet.

766

I'd rather make the switch fully covered than add a default. Also, you could add an unreachable before the end of the function.

unittests/Support/TargetParserTest.cpp
452

Are the extra checks necessary?

790

This kind of iteration was sort of ok when there was an AK_LAST, but I think with that gone there's the chance that this test won't get updated when someone adds something after ARMV8_2A.

One alternative would be to add the enum values to a vector (you can just #define AARCH64_ARCH(NAME, ID [...]) to push_back and include AArch64TargetParser.def) and iterate over the vector instead.

fhahn updated this revision to Diff 108454.Jul 27 2017, 6:26 AM
fhahn marked an inline comment as done.

Thanks for having a look Diana. I hope I have addressed your comments adequately

fhahn added inline comments.Jul 27 2017, 6:27 AM
lib/Support/TargetParser.cpp
380

I thought a change in the .def file made that unnecessary, but I was mistaken.

766

Excellent point! I've removed the default case from this switch and the switch above in ARM::parseArchProfile.

unittests/Support/TargetParserTest.cpp
452

Unfortunately yes, but I am not sure if that test adds much value.

It seems like the previous test just checked if "0 <= ARM::getFPUVersion(FK)" for all FK holds. I think the intention was to check that it always returns an element in the enum, but wouldn't the condition be always true, because ARM::getFPUVersion(FK) used to return unsigned?

I think the tests in ARMFPUNeonSupportLevel and ARMFPURestriction have the same problem.

790

Agreed, thanks for the vector tip! :)

fhahn added a child revision: D35884: Update to use enum classes for various ARM *Kind enums.Jul 27 2017, 7:21 AM
rovka accepted this revision.Jul 27 2017, 7:45 AM

LGTM.

unittests/Support/TargetParserTest.cpp
452

You're right, these tests were a bit iffy to begin with.

790

That's even nicer :)

This revision is now accepted and ready to land.Jul 27 2017, 7:45 AM
fhahn added a comment.Jul 27 2017, 7:50 AM

Great thanks again for having a look! This patch needs to go in with D35884, so I'll wait until D35884 is reviewed to and commit them together.

fhahn closed this revision.Jul 27 2017, 9:28 AM
fhahn mentioned this in rL309289: Update to use enum classes for various ARM *Kind enums.Jul 27 2017, 9:29 AM

Revision Contents

PathSize
include/
llvm/
MC/
5 lines
Support/
42 lines
270 lines
112 lines
lib/
Support/
298 lines
89 lines
Target/
AArch64/
AsmParser/
4 lines
ARM/
6 lines
AsmParser/
8 lines
MCTargetDesc/
26 lines
72 lines
4 lines
4 lines
unittests/
Support/
325 lines

Diff 108238

include/llvm/MC/MCStreamer.h

Show All 18 Lines
#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h" #include "llvm/ADT/StringRef.h"
#include "llvm/MC/MCDirectives.h" #include "llvm/MC/MCDirectives.h"
#include "llvm/MC/MCDwarf.h" #include "llvm/MC/MCDwarf.h"
#include "llvm/MC/MCLinkerOptimizationHint.h" #include "llvm/MC/MCLinkerOptimizationHint.h"
#include "llvm/MC/MCSymbol.h" #include "llvm/MC/MCSymbol.h"
#include "llvm/MC/MCWinEH.h" #include "llvm/MC/MCWinEH.h"
#include "llvm/Support/SMLoc.h" #include "llvm/Support/SMLoc.h"
#include "llvm/Support/TargetParser.h"
#include <cassert> #include <cassert>
#include <cstdint> #include <cstdint>
#include <memory> #include <memory>
#include <string> #include <string>
#include <utility> #include <utility>
#include <vector> #include <vector>
namespace llvm { namespace llvm {
▲ Show 20 Lines • Show All 84 Lines • ▼ Show 20 Lines virtual void emitUnwindRaw(int64_t StackOffset,
const SmallVectorImpl<uint8_t> &Opcodes); const SmallVectorImpl<uint8_t> &Opcodes);
virtual void switchVendor(StringRef Vendor); virtual void switchVendor(StringRef Vendor);
virtual void emitAttribute(unsigned Attribute, unsigned Value); virtual void emitAttribute(unsigned Attribute, unsigned Value);
virtual void emitTextAttribute(unsigned Attribute, StringRef String); virtual void emitTextAttribute(unsigned Attribute, StringRef String);
virtual void emitIntTextAttribute(unsigned Attribute, unsigned IntValue, virtual void emitIntTextAttribute(unsigned Attribute, unsigned IntValue,
StringRef StringValue = ""); StringRef StringValue = "");
virtual void emitFPU(unsigned FPU); virtual void emitFPU(unsigned FPU);
virtual void emitArch(unsigned Arch); virtual void emitArch(ARM::ArchKind Arch);
virtual void emitArchExtension(unsigned ArchExt); virtual void emitArchExtension(unsigned ArchExt);
virtual void emitObjectArch(unsigned Arch); virtual void emitObjectArch(ARM::ArchKind Arch);
void emitTargetAttributes(const MCSubtargetInfo &STI); void emitTargetAttributes(const MCSubtargetInfo &STI);
virtual void finishAttributeSection(); virtual void finishAttributeSection();
virtual void emitInst(uint32_t Inst, char Suffix = '\0'); virtual void emitInst(uint32_t Inst, char Suffix = '\0');
virtual void AnnotateTLSDescriptorSequence(const MCSymbolRefExpr *SRE); virtual void AnnotateTLSDescriptorSequence(const MCSymbolRefExpr *SRE);
virtual void emitThumbSet(MCSymbol *Symbol, const MCExpr *Value); virtual void emitThumbSet(MCSymbol *Symbol, const MCExpr *Value);
▲ Show 20 Lines • Show All 761 Lines • Show Last 20 Lines

include/llvm/Support/AArch64TargetParser.def

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// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// NOTE: NO INCLUDE GUARD DESIRED! // NOTE: NO INCLUDE GUARD DESIRED!
#ifndef AARCH64_ARCH #ifndef AARCH64_ARCH
#define AARCH64_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) #define AARCH64_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT)
#endif #endif
AARCH64_ARCH("invalid", AK_INVALID, nullptr, nullptr, AARCH64_ARCH("invalid", INVALID, "", "",
ARMBuildAttrs::CPUArch::v8_A, FK_NONE, AArch64::AEK_NONE) ARMBuildAttrs::CPUArch::v8_A, FK_NONE, AArch64::AEK_NONE)
AARCH64_ARCH("armv8-a", AK_ARMV8A, "8-A", "v8", ARMBuildAttrs::CPUArch::v8_A, AARCH64_ARCH("armv8-a", ARMV8A, "8-A", "v8", ARMBuildAttrs::CPUArch::v8_A,
FK_CRYPTO_NEON_FP_ARMV8, FK_CRYPTO_NEON_FP_ARMV8,
(AArch64::AEK_CRYPTO | AArch64::AEK_FP | AArch64::AEK_SIMD)) (AArch64::AEK_CRYPTO | AArch64::AEK_FP | AArch64::AEK_SIMD))
AARCH64_ARCH("armv8.1-a", AK_ARMV8_1A, "8.1-A", "v8.1a", AARCH64_ARCH("armv8.1-a", ARMV8_1A, "8.1-A", "v8.1a",
ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8, ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
(AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP | (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
AArch64::AEK_SIMD | AArch64::AEK_LSE)) AArch64::AEK_SIMD | AArch64::AEK_LSE))
AARCH64_ARCH("armv8.2-a", AK_ARMV8_2A, "8.2-A", "v8.2a", AARCH64_ARCH("armv8.2-a", ARMV8_2A, "8.2-A", "v8.2a",
ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8, ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
(AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP | (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE)) AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE))
#undef AARCH64_ARCH #undef AARCH64_ARCH
#ifndef AARCH64_ARCH_EXT_NAME #ifndef AARCH64_ARCH_EXT_NAME
#define AARCH64_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE) #define AARCH64_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE)
#endif #endif
Show All 9 Lines
AARCH64_ARCH_EXT_NAME("profile", AArch64::AEK_PROFILE, "+spe", "-spe") AARCH64_ARCH_EXT_NAME("profile", AArch64::AEK_PROFILE, "+spe", "-spe")
AARCH64_ARCH_EXT_NAME("ras", AArch64::AEK_RAS, "+ras", "-ras") AARCH64_ARCH_EXT_NAME("ras", AArch64::AEK_RAS, "+ras", "-ras")
AARCH64_ARCH_EXT_NAME("sve", AArch64::AEK_SVE, "+sve", "-sve") AARCH64_ARCH_EXT_NAME("sve", AArch64::AEK_SVE, "+sve", "-sve")
#undef AARCH64_ARCH_EXT_NAME #undef AARCH64_ARCH_EXT_NAME
#ifndef AARCH64_CPU_NAME #ifndef AARCH64_CPU_NAME
#define AARCH64_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) #define AARCH64_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT)
#endif #endif
AARCH64_CPU_NAME("cortex-a35", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, AARCH64_CPU_NAME("cortex-a35", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_CRC)) (AArch64::AEK_CRC))
AARCH64_CPU_NAME("cortex-a53", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, true, AARCH64_CPU_NAME("cortex-a53", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, true,
(AArch64::AEK_CRC)) (AArch64::AEK_CRC))
AARCH64_CPU_NAME("cortex-a57", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, AARCH64_CPU_NAME("cortex-a57", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_CRC)) (AArch64::AEK_CRC))
AARCH64_CPU_NAME("cortex-a72", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, AARCH64_CPU_NAME("cortex-a72", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_CRC)) (AArch64::AEK_CRC))
AARCH64_CPU_NAME("cortex-a73", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, AARCH64_CPU_NAME("cortex-a73", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_CRC)) (AArch64::AEK_CRC))
AARCH64_CPU_NAME("cyclone", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, AARCH64_CPU_NAME("cyclone", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_NONE)) (AArch64::AEK_NONE))
AARCH64_CPU_NAME("exynos-m1", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, AARCH64_CPU_NAME("exynos-m1", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_CRC)) (AArch64::AEK_CRC))
AARCH64_CPU_NAME("exynos-m2", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, AARCH64_CPU_NAME("exynos-m2", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_CRC)) (AArch64::AEK_CRC))
AARCH64_CPU_NAME("exynos-m3", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, AARCH64_CPU_NAME("exynos-m3", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_CRC)) (AArch64::AEK_CRC))
AARCH64_CPU_NAME("falkor", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, AARCH64_CPU_NAME("falkor", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_CRC)) (AArch64::AEK_CRC))
AARCH64_CPU_NAME("kryo", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, AARCH64_CPU_NAME("kryo", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_CRC)) (AArch64::AEK_CRC))
AARCH64_CPU_NAME("thunderx2t99", AK_ARMV8_1A, FK_CRYPTO_NEON_FP_ARMV8, false, AARCH64_CPU_NAME("thunderx2t99", ARMV8_1A, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_NONE)) (AArch64::AEK_NONE))
AARCH64_CPU_NAME("thunderx", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, AARCH64_CPU_NAME("thunderx", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_CRC | AArch64::AEK_PROFILE)) (AArch64::AEK_CRC | AArch64::AEK_PROFILE))
AARCH64_CPU_NAME("thunderxt88", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, AARCH64_CPU_NAME("thunderxt88", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_CRC | AArch64::AEK_PROFILE)) (AArch64::AEK_CRC | AArch64::AEK_PROFILE))
AARCH64_CPU_NAME("thunderxt81", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, AARCH64_CPU_NAME("thunderxt81", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_CRC | AArch64::AEK_PROFILE)) (AArch64::AEK_CRC | AArch64::AEK_PROFILE))
AARCH64_CPU_NAME("thunderxt83", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, AARCH64_CPU_NAME("thunderxt83", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_CRC | AArch64::AEK_PROFILE)) (AArch64::AEK_CRC | AArch64::AEK_PROFILE))
// Invalid CPU // Invalid CPU
AARCH64_CPU_NAME("invalid", AK_INVALID, FK_INVALID, true, AArch64::AEK_INVALID) AARCH64_CPU_NAME("invalid", INVALID, FK_INVALID, true, AArch64::AEK_INVALID)
#undef AARCH64_CPU_NAME #undef AARCH64_CPU_NAME

include/llvm/Support/ARMTargetParser.def

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// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// NOTE: NO INCLUDE GUARD DESIRED! // NOTE: NO INCLUDE GUARD DESIRED!
#ifndef ARM_FPU #ifndef ARM_FPU
#define ARM_FPU(NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION) #define ARM_FPU(NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION)
#endif #endif
ARM_FPU("invalid", FK_INVALID, FV_NONE, NS_None, FR_None) ARM_FPU("invalid", FK_INVALID, FPUVersion::NONE, NeonSupportLevel::None, FPURestriction::None)
ARM_FPU("none", FK_NONE, FV_NONE, NS_None, FR_None) ARM_FPU("none", FK_NONE, FPUVersion::NONE, NeonSupportLevel::None, FPURestriction::None)
ARM_FPU("vfp", FK_VFP, FV_VFPV2, NS_None, FR_None) ARM_FPU("vfp", FK_VFP, FPUVersion::VFPV2, NeonSupportLevel::None, FPURestriction::None)
ARM_FPU("vfpv2", FK_VFPV2, FV_VFPV2, NS_None, FR_None) ARM_FPU("vfpv2", FK_VFPV2, FPUVersion::VFPV2, NeonSupportLevel::None, FPURestriction::None)
ARM_FPU("vfpv3", FK_VFPV3, FV_VFPV3, NS_None, FR_None) ARM_FPU("vfpv3", FK_VFPV3, FPUVersion::VFPV3, NeonSupportLevel::None, FPURestriction::None)
ARM_FPU("vfpv3-fp16", FK_VFPV3_FP16, FV_VFPV3_FP16, NS_None, FR_None) ARM_FPU("vfpv3-fp16", FK_VFPV3_FP16, FPUVersion::VFPV3_FP16, NeonSupportLevel::None, FPURestriction::None)
ARM_FPU("vfpv3-d16", FK_VFPV3_D16, FV_VFPV3, NS_None, FR_D16) ARM_FPU("vfpv3-d16", FK_VFPV3_D16, FPUVersion::VFPV3, NeonSupportLevel::None, FPURestriction::D16)
ARM_FPU("vfpv3-d16-fp16", FK_VFPV3_D16_FP16, FV_VFPV3_FP16, NS_None, FR_D16) ARM_FPU("vfpv3-d16-fp16", FK_VFPV3_D16_FP16, FPUVersion::VFPV3_FP16, NeonSupportLevel::None, FPURestriction::D16)
ARM_FPU("vfpv3xd", FK_VFPV3XD, FV_VFPV3, NS_None, FR_SP_D16) ARM_FPU("vfpv3xd", FK_VFPV3XD, FPUVersion::VFPV3, NeonSupportLevel::None, FPURestriction::SP_D16)
ARM_FPU("vfpv3xd-fp16", FK_VFPV3XD_FP16, FV_VFPV3_FP16, NS_None, FR_SP_D16) ARM_FPU("vfpv3xd-fp16", FK_VFPV3XD_FP16, FPUVersion::VFPV3_FP16, NeonSupportLevel::None, FPURestriction::SP_D16)
ARM_FPU("vfpv4", FK_VFPV4, FV_VFPV4, NS_None, FR_None) ARM_FPU("vfpv4", FK_VFPV4, FPUVersion::VFPV4, NeonSupportLevel::None, FPURestriction::None)
ARM_FPU("vfpv4-d16", FK_VFPV4_D16, FV_VFPV4, NS_None, FR_D16) ARM_FPU("vfpv4-d16", FK_VFPV4_D16, FPUVersion::VFPV4, NeonSupportLevel::None, FPURestriction::D16)
ARM_FPU("fpv4-sp-d16", FK_FPV4_SP_D16, FV_VFPV4, NS_None, FR_SP_D16) ARM_FPU("fpv4-sp-d16", FK_FPV4_SP_D16, FPUVersion::VFPV4, NeonSupportLevel::None, FPURestriction::SP_D16)
ARM_FPU("fpv5-d16", FK_FPV5_D16, FV_VFPV5, NS_None, FR_D16) ARM_FPU("fpv5-d16", FK_FPV5_D16, FPUVersion::VFPV5, NeonSupportLevel::None, FPURestriction::D16)
ARM_FPU("fpv5-sp-d16", FK_FPV5_SP_D16, FV_VFPV5, NS_None, FR_SP_D16) ARM_FPU("fpv5-sp-d16", FK_FPV5_SP_D16, FPUVersion::VFPV5, NeonSupportLevel::None, FPURestriction::SP_D16)
ARM_FPU("fp-armv8", FK_FP_ARMV8, FV_VFPV5, NS_None, FR_None) ARM_FPU("fp-armv8", FK_FP_ARMV8, FPUVersion::VFPV5, NeonSupportLevel::None, FPURestriction::None)
ARM_FPU("neon", FK_NEON, FV_VFPV3, NS_Neon, FR_None) ARM_FPU("neon", FK_NEON, FPUVersion::VFPV3, NeonSupportLevel::Neon, FPURestriction::None)
ARM_FPU("neon-fp16", FK_NEON_FP16, FV_VFPV3_FP16, NS_Neon, FR_None) ARM_FPU("neon-fp16", FK_NEON_FP16, FPUVersion::VFPV3_FP16, NeonSupportLevel::Neon, FPURestriction::None)
ARM_FPU("neon-vfpv4", FK_NEON_VFPV4, FV_VFPV4, NS_Neon, FR_None) ARM_FPU("neon-vfpv4", FK_NEON_VFPV4, FPUVersion::VFPV4, NeonSupportLevel::Neon, FPURestriction::None)
ARM_FPU("neon-fp-armv8", FK_NEON_FP_ARMV8, FV_VFPV5, NS_Neon, FR_None) ARM_FPU("neon-fp-armv8", FK_NEON_FP_ARMV8, FPUVersion::VFPV5, NeonSupportLevel::Neon, FPURestriction::None)
ARM_FPU("crypto-neon-fp-armv8", FK_CRYPTO_NEON_FP_ARMV8, FV_VFPV5, NS_Crypto, ARM_FPU("crypto-neon-fp-armv8", FK_CRYPTO_NEON_FP_ARMV8, FPUVersion::VFPV5, NeonSupportLevel::Crypto,
FR_None) FPURestriction::None)
ARM_FPU("softvfp", FK_SOFTVFP, FV_NONE, NS_None, FR_None) ARM_FPU("softvfp", FK_SOFTVFP, FPUVersion::NONE, NeonSupportLevel::None, FPURestriction::None)
#undef ARM_FPU #undef ARM_FPU
#ifndef ARM_ARCH #ifndef ARM_ARCH
#define ARM_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) #define ARM_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT)
#endif #endif
ARM_ARCH("invalid", AK_INVALID, nullptr, nullptr, ARM_ARCH("invalid", INVALID, "", "",
ARMBuildAttrs::CPUArch::Pre_v4, FK_NONE, ARM::AEK_NONE) ARMBuildAttrs::CPUArch::Pre_v4, FK_NONE, ARM::AEK_NONE)
ARM_ARCH("armv2", AK_ARMV2, "2", "v2", ARMBuildAttrs::CPUArch::Pre_v4, ARM_ARCH("armv2", ARMV2, "2", "v2", ARMBuildAttrs::CPUArch::Pre_v4,
FK_NONE, ARM::AEK_NONE) FK_NONE, ARM::AEK_NONE)
ARM_ARCH("armv2a", AK_ARMV2A, "2A", "v2a", ARMBuildAttrs::CPUArch::Pre_v4, ARM_ARCH("armv2a", ARMV2A, "2A", "v2a", ARMBuildAttrs::CPUArch::Pre_v4,
FK_NONE, ARM::AEK_NONE) FK_NONE, ARM::AEK_NONE)
ARM_ARCH("armv3", AK_ARMV3, "3", "v3", ARMBuildAttrs::CPUArch::Pre_v4, ARM_ARCH("armv3", ARMV3, "3", "v3", ARMBuildAttrs::CPUArch::Pre_v4,
FK_NONE, ARM::AEK_NONE) FK_NONE, ARM::AEK_NONE)
ARM_ARCH("armv3m", AK_ARMV3M, "3M", "v3m", ARMBuildAttrs::CPUArch::Pre_v4, ARM_ARCH("armv3m", ARMV3M, "3M", "v3m", ARMBuildAttrs::CPUArch::Pre_v4,
FK_NONE, ARM::AEK_NONE) FK_NONE, ARM::AEK_NONE)
ARM_ARCH("armv4", AK_ARMV4, "4", "v4", ARMBuildAttrs::CPUArch::v4, ARM_ARCH("armv4", ARMV4, "4", "v4", ARMBuildAttrs::CPUArch::v4,
FK_NONE, ARM::AEK_NONE) FK_NONE, ARM::AEK_NONE)
ARM_ARCH("armv4t", AK_ARMV4T, "4T", "v4t", ARMBuildAttrs::CPUArch::v4T, ARM_ARCH("armv4t", ARMV4T, "4T", "v4t", ARMBuildAttrs::CPUArch::v4T,
FK_NONE, ARM::AEK_NONE) FK_NONE, ARM::AEK_NONE)
ARM_ARCH("armv5t", AK_ARMV5T, "5T", "v5", ARMBuildAttrs::CPUArch::v5T, ARM_ARCH("armv5t", ARMV5T, "5T", "v5", ARMBuildAttrs::CPUArch::v5T,
FK_NONE, ARM::AEK_NONE) FK_NONE, ARM::AEK_NONE)
ARM_ARCH("armv5te", AK_ARMV5TE, "5TE", "v5e", ARMBuildAttrs::CPUArch::v5TE, ARM_ARCH("armv5te", ARMV5TE, "5TE", "v5e", ARMBuildAttrs::CPUArch::v5TE,
FK_NONE, ARM::AEK_DSP) FK_NONE, ARM::AEK_DSP)
ARM_ARCH("armv5tej", AK_ARMV5TEJ, "5TEJ", "v5e", ARMBuildAttrs::CPUArch::v5TEJ, ARM_ARCH("armv5tej", ARMV5TEJ, "5TEJ", "v5e", ARMBuildAttrs::CPUArch::v5TEJ,
FK_NONE, ARM::AEK_DSP) FK_NONE, ARM::AEK_DSP)
ARM_ARCH("armv6", AK_ARMV6, "6", "v6", ARMBuildAttrs::CPUArch::v6, ARM_ARCH("armv6", ARMV6, "6", "v6", ARMBuildAttrs::CPUArch::v6,
FK_VFPV2, ARM::AEK_DSP) FK_VFPV2, ARM::AEK_DSP)
ARM_ARCH("armv6k", AK_ARMV6K, "6K", "v6k", ARMBuildAttrs::CPUArch::v6K, ARM_ARCH("armv6k", ARMV6K, "6K", "v6k", ARMBuildAttrs::CPUArch::v6K,
FK_VFPV2, ARM::AEK_DSP) FK_VFPV2, ARM::AEK_DSP)
ARM_ARCH("armv6t2", AK_ARMV6T2, "6T2", "v6t2", ARMBuildAttrs::CPUArch::v6T2, ARM_ARCH("armv6t2", ARMV6T2, "6T2", "v6t2", ARMBuildAttrs::CPUArch::v6T2,
FK_NONE, ARM::AEK_DSP) FK_NONE, ARM::AEK_DSP)
ARM_ARCH("armv6kz", AK_ARMV6KZ, "6KZ", "v6kz", ARMBuildAttrs::CPUArch::v6KZ, ARM_ARCH("armv6kz", ARMV6KZ, "6KZ", "v6kz", ARMBuildAttrs::CPUArch::v6KZ,
FK_VFPV2, (ARM::AEK_SEC | ARM::AEK_DSP)) FK_VFPV2, (ARM::AEK_SEC | ARM::AEK_DSP))
ARM_ARCH("armv6-m", AK_ARMV6M, "6-M", "v6m", ARMBuildAttrs::CPUArch::v6_M, ARM_ARCH("armv6-m", ARMV6M, "6-M", "v6m", ARMBuildAttrs::CPUArch::v6_M,
FK_NONE, ARM::AEK_NONE) FK_NONE, ARM::AEK_NONE)
ARM_ARCH("armv7-a", AK_ARMV7A, "7-A", "v7", ARMBuildAttrs::CPUArch::v7, ARM_ARCH("armv7-a", ARMV7A, "7-A", "v7", ARMBuildAttrs::CPUArch::v7,
FK_NEON, ARM::AEK_DSP) FK_NEON, ARM::AEK_DSP)
ARM_ARCH("armv7ve", AK_ARMV7VE, "7VE", "v7ve", ARMBuildAttrs::CPUArch::v7, ARM_ARCH("armv7ve", ARMV7VE, "7VE", "v7ve", ARMBuildAttrs::CPUArch::v7,
FK_NEON, (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | FK_NEON, (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT |
ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP)) ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP))
ARM_ARCH("armv7-r", AK_ARMV7R, "7-R", "v7r", ARMBuildAttrs::CPUArch::v7, ARM_ARCH("armv7-r", ARMV7R, "7-R", "v7r", ARMBuildAttrs::CPUArch::v7,
FK_NONE, (ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP)) FK_NONE, (ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP))
ARM_ARCH("armv7-m", AK_ARMV7M, "7-M", "v7m", ARMBuildAttrs::CPUArch::v7, ARM_ARCH("armv7-m", ARMV7M, "7-M", "v7m", ARMBuildAttrs::CPUArch::v7,
FK_NONE, ARM::AEK_HWDIVTHUMB) FK_NONE, ARM::AEK_HWDIVTHUMB)
ARM_ARCH("armv7e-m", AK_ARMV7EM, "7E-M", "v7em", ARMBuildAttrs::CPUArch::v7E_M, ARM_ARCH("armv7e-m", ARMV7EM, "7E-M", "v7em", ARMBuildAttrs::CPUArch::v7E_M,
FK_NONE, (ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP)) FK_NONE, (ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP))
ARM_ARCH("armv8-a", AK_ARMV8A, "8-A", "v8", ARMBuildAttrs::CPUArch::v8_A, ARM_ARCH("armv8-a", ARMV8A, "8-A", "v8", ARMBuildAttrs::CPUArch::v8_A,
FK_CRYPTO_NEON_FP_ARMV8, FK_CRYPTO_NEON_FP_ARMV8,
(ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC)) ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC))
ARM_ARCH("armv8.1-a", AK_ARMV8_1A, "8.1-A", "v8.1a", ARM_ARCH("armv8.1-a", ARMV8_1A, "8.1-A", "v8.1a",
ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8, ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
(ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC)) ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC))
ARM_ARCH("armv8.2-a", AK_ARMV8_2A, "8.2-A", "v8.2a", ARM_ARCH("armv8.2-a", ARMV8_2A, "8.2-A", "v8.2a",
ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8, ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
(ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS)) ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS))
ARM_ARCH("armv8-r", AK_ARMV8R, "8-R", "v8r", ARMBuildAttrs::CPUArch::v8_R, ARM_ARCH("armv8-r", ARMV8R, "8-R", "v8r", ARMBuildAttrs::CPUArch::v8_R,
FK_NEON_FP_ARMV8, FK_NEON_FP_ARMV8,
(ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | (ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
ARM::AEK_DSP | ARM::AEK_CRC)) ARM::AEK_DSP | ARM::AEK_CRC))
ARM_ARCH("armv8-m.base", AK_ARMV8MBaseline, "8-M.Baseline", "v8m.base", ARM_ARCH("armv8-m.base", ARMV8MBaseline, "8-M.Baseline", "v8m.base",
ARMBuildAttrs::CPUArch::v8_M_Base, FK_NONE, ARM::AEK_HWDIVTHUMB) ARMBuildAttrs::CPUArch::v8_M_Base, FK_NONE, ARM::AEK_HWDIVTHUMB)
ARM_ARCH("armv8-m.main", AK_ARMV8MMainline, "8-M.Mainline", "v8m.main", ARM_ARCH("armv8-m.main", ARMV8MMainline, "8-M.Mainline", "v8m.main",
ARMBuildAttrs::CPUArch::v8_M_Main, FK_FPV5_D16, ARM::AEK_HWDIVTHUMB) ARMBuildAttrs::CPUArch::v8_M_Main, FK_FPV5_D16, ARM::AEK_HWDIVTHUMB)
// Non-standard Arch names. // Non-standard Arch names.
ARM_ARCH("iwmmxt", AK_IWMMXT, "iwmmxt", "", ARMBuildAttrs::CPUArch::v5TE, ARM_ARCH("iwmmxt", IWMMXT, "iwmmxt", "", ARMBuildAttrs::CPUArch::v5TE,
FK_NONE, ARM::AEK_NONE) FK_NONE, ARM::AEK_NONE)
ARM_ARCH("iwmmxt2", AK_IWMMXT2, "iwmmxt2", "", ARMBuildAttrs::CPUArch::v5TE, ARM_ARCH("iwmmxt2", IWMMXT2, "iwmmxt2", "", ARMBuildAttrs::CPUArch::v5TE,
FK_NONE, ARM::AEK_NONE) FK_NONE, ARM::AEK_NONE)
ARM_ARCH("xscale", AK_XSCALE, "xscale", "v5e", ARMBuildAttrs::CPUArch::v5TE, ARM_ARCH("xscale", XSCALE, "xscale", "v5e", ARMBuildAttrs::CPUArch::v5TE,
FK_NONE, ARM::AEK_NONE) FK_NONE, ARM::AEK_NONE)
ARM_ARCH("armv7s", AK_ARMV7S, "7-S", "v7s", ARMBuildAttrs::CPUArch::v7, ARM_ARCH("armv7s", ARMV7S, "7-S", "v7s", ARMBuildAttrs::CPUArch::v7,
FK_NEON_VFPV4, ARM::AEK_DSP) FK_NEON_VFPV4, ARM::AEK_DSP)
ARM_ARCH("armv7k", AK_ARMV7K, "7-K", "v7k", ARMBuildAttrs::CPUArch::v7, ARM_ARCH("armv7k", ARMV7K, "7-K", "v7k", ARMBuildAttrs::CPUArch::v7,
FK_NONE, ARM::AEK_DSP) FK_NONE, ARM::AEK_DSP)
#undef ARM_ARCH #undef ARM_ARCH
#ifndef ARM_ARCH_EXT_NAME #ifndef ARM_ARCH_EXT_NAME
#define ARM_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE) #define ARM_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE)
#endif #endif
// FIXME: This would be nicer were it tablegen // FIXME: This would be nicer were it tablegen
ARM_ARCH_EXT_NAME("invalid", ARM::AEK_INVALID, nullptr, nullptr) ARM_ARCH_EXT_NAME("invalid", ARM::AEK_INVALID, nullptr, nullptr)
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ARM_HW_DIV_NAME("thumb", ARM::AEK_HWDIVTHUMB) ARM_HW_DIV_NAME("thumb", ARM::AEK_HWDIVTHUMB)
ARM_HW_DIV_NAME("arm", ARM::AEK_HWDIVARM) ARM_HW_DIV_NAME("arm", ARM::AEK_HWDIVARM)
ARM_HW_DIV_NAME("arm,thumb", (ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB)) ARM_HW_DIV_NAME("arm,thumb", (ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB))
#undef ARM_HW_DIV_NAME #undef ARM_HW_DIV_NAME
#ifndef ARM_CPU_NAME #ifndef ARM_CPU_NAME
#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) #define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT)
#endif #endif
ARM_CPU_NAME("arm2", AK_ARMV2, FK_NONE, true, ARM::AEK_NONE) ARM_CPU_NAME("arm2", ARMV2, FK_NONE, true, ARM::AEK_NONE)
ARM_CPU_NAME("arm3", AK_ARMV2A, FK_NONE, true, ARM::AEK_NONE) ARM_CPU_NAME("arm3", ARMV2A, FK_NONE, true, ARM::AEK_NONE)
ARM_CPU_NAME("arm6", AK_ARMV3, FK_NONE, true, ARM::AEK_NONE) ARM_CPU_NAME("arm6", ARMV3, FK_NONE, true, ARM::AEK_NONE)
ARM_CPU_NAME("arm7m", AK_ARMV3M, FK_NONE, true, ARM::AEK_NONE) ARM_CPU_NAME("arm7m", ARMV3M, FK_NONE, true, ARM::AEK_NONE)
ARM_CPU_NAME("arm8", AK_ARMV4, FK_NONE, false, ARM::AEK_NONE) ARM_CPU_NAME("arm8", ARMV4, FK_NONE, false, ARM::AEK_NONE)
ARM_CPU_NAME("arm810", AK_ARMV4, FK_NONE, false, ARM::AEK_NONE) ARM_CPU_NAME("arm810", ARMV4, FK_NONE, false, ARM::AEK_NONE)
ARM_CPU_NAME("strongarm", AK_ARMV4, FK_NONE, true, ARM::AEK_NONE) ARM_CPU_NAME("strongarm", ARMV4, FK_NONE, true, ARM::AEK_NONE)
ARM_CPU_NAME("strongarm110", AK_ARMV4, FK_NONE, false, ARM::AEK_NONE) ARM_CPU_NAME("strongarm110", ARMV4, FK_NONE, false, ARM::AEK_NONE)
ARM_CPU_NAME("strongarm1100", AK_ARMV4, FK_NONE, false, ARM::AEK_NONE) ARM_CPU_NAME("strongarm1100", ARMV4, FK_NONE, false, ARM::AEK_NONE)
ARM_CPU_NAME("strongarm1110", AK_ARMV4, FK_NONE, false, ARM::AEK_NONE) ARM_CPU_NAME("strongarm1110", ARMV4, FK_NONE, false, ARM::AEK_NONE)
ARM_CPU_NAME("arm7tdmi", AK_ARMV4T, FK_NONE, true, ARM::AEK_NONE) ARM_CPU_NAME("arm7tdmi", ARMV4T, FK_NONE, true, ARM::AEK_NONE)
ARM_CPU_NAME("arm7tdmi-s", AK_ARMV4T, FK_NONE, false, ARM::AEK_NONE) ARM_CPU_NAME("arm7tdmi-s", ARMV4T, FK_NONE, false, ARM::AEK_NONE)
ARM_CPU_NAME("arm710t", AK_ARMV4T, FK_NONE, false, ARM::AEK_NONE) ARM_CPU_NAME("arm710t", ARMV4T, FK_NONE, false, ARM::AEK_NONE)
ARM_CPU_NAME("arm720t", AK_ARMV4T, FK_NONE, false, ARM::AEK_NONE) ARM_CPU_NAME("arm720t", ARMV4T, FK_NONE, false, ARM::AEK_NONE)
ARM_CPU_NAME("arm9", AK_ARMV4T, FK_NONE, false, ARM::AEK_NONE) ARM_CPU_NAME("arm9", ARMV4T, FK_NONE, false, ARM::AEK_NONE)
ARM_CPU_NAME("arm9tdmi", AK_ARMV4T, FK_NONE, false, ARM::AEK_NONE) ARM_CPU_NAME("arm9tdmi", ARMV4T, FK_NONE, false, ARM::AEK_NONE)
ARM_CPU_NAME("arm920", AK_ARMV4T, FK_NONE, false, ARM::AEK_NONE) ARM_CPU_NAME("arm920", ARMV4T, FK_NONE, false, ARM::AEK_NONE)
ARM_CPU_NAME("arm920t", AK_ARMV4T, FK_NONE, false, ARM::AEK_NONE) ARM_CPU_NAME("arm920t", ARMV4T, FK_NONE, false, ARM::AEK_NONE)
ARM_CPU_NAME("arm922t", AK_ARMV4T, FK_NONE, false, ARM::AEK_NONE) ARM_CPU_NAME("arm922t", ARMV4T, FK_NONE, false, ARM::AEK_NONE)
ARM_CPU_NAME("arm9312", AK_ARMV4T, FK_NONE, false, ARM::AEK_NONE) ARM_CPU_NAME("arm9312", ARMV4T, FK_NONE, false, ARM::AEK_NONE)
ARM_CPU_NAME("arm940t", AK_ARMV4T, FK_NONE, false, ARM::AEK_NONE) ARM_CPU_NAME("arm940t", ARMV4T, FK_NONE, false, ARM::AEK_NONE)
ARM_CPU_NAME("ep9312", AK_ARMV4T, FK_NONE, false, ARM::AEK_NONE) ARM_CPU_NAME("ep9312", ARMV4T, FK_NONE, false, ARM::AEK_NONE)
ARM_CPU_NAME("arm10tdmi", AK_ARMV5T, FK_NONE, true, ARM::AEK_NONE) ARM_CPU_NAME("arm10tdmi", ARMV5T, FK_NONE, true, ARM::AEK_NONE)
ARM_CPU_NAME("arm1020t", AK_ARMV5T, FK_NONE, false, ARM::AEK_NONE) ARM_CPU_NAME("arm1020t", ARMV5T, FK_NONE, false, ARM::AEK_NONE)
ARM_CPU_NAME("arm9e", AK_ARMV5TE, FK_NONE, false, ARM::AEK_NONE) ARM_CPU_NAME("arm9e", ARMV5TE, FK_NONE, false, ARM::AEK_NONE)
ARM_CPU_NAME("arm946e-s", AK_ARMV5TE, FK_NONE, false, ARM::AEK_NONE) ARM_CPU_NAME("arm946e-s", ARMV5TE, FK_NONE, false, ARM::AEK_NONE)
ARM_CPU_NAME("arm966e-s", AK_ARMV5TE, FK_NONE, false, ARM::AEK_NONE) ARM_CPU_NAME("arm966e-s", ARMV5TE, FK_NONE, false, ARM::AEK_NONE)
ARM_CPU_NAME("arm968e-s", AK_ARMV5TE, FK_NONE, false, ARM::AEK_NONE) ARM_CPU_NAME("arm968e-s", ARMV5TE, FK_NONE, false, ARM::AEK_NONE)
ARM_CPU_NAME("arm10e", AK_ARMV5TE, FK_NONE, false, ARM::AEK_NONE) ARM_CPU_NAME("arm10e", ARMV5TE, FK_NONE, false, ARM::AEK_NONE)
ARM_CPU_NAME("arm1020e", AK_ARMV5TE, FK_NONE, false, ARM::AEK_NONE) ARM_CPU_NAME("arm1020e", ARMV5TE, FK_NONE, false, ARM::AEK_NONE)
ARM_CPU_NAME("arm1022e", AK_ARMV5TE, FK_NONE, true, ARM::AEK_NONE) ARM_CPU_NAME("arm1022e", ARMV5TE, FK_NONE, true, ARM::AEK_NONE)
ARM_CPU_NAME("arm926ej-s", AK_ARMV5TEJ, FK_NONE, true, ARM::AEK_NONE) ARM_CPU_NAME("arm926ej-s", ARMV5TEJ, FK_NONE, true, ARM::AEK_NONE)
ARM_CPU_NAME("arm1136j-s", AK_ARMV6, FK_NONE, false, ARM::AEK_NONE) ARM_CPU_NAME("arm1136j-s", ARMV6, FK_NONE, false, ARM::AEK_NONE)
ARM_CPU_NAME("arm1136jf-s", AK_ARMV6, FK_VFPV2, true, ARM::AEK_NONE) ARM_CPU_NAME("arm1136jf-s", ARMV6, FK_VFPV2, true, ARM::AEK_NONE)
ARM_CPU_NAME("arm1136jz-s", AK_ARMV6, FK_NONE, false, ARM::AEK_NONE) ARM_CPU_NAME("arm1136jz-s", ARMV6, FK_NONE, false, ARM::AEK_NONE)
ARM_CPU_NAME("arm1176j-s", AK_ARMV6K, FK_NONE, true, ARM::AEK_NONE) ARM_CPU_NAME("arm1176j-s", ARMV6K, FK_NONE, true, ARM::AEK_NONE)
ARM_CPU_NAME("arm1176jz-s", AK_ARMV6KZ, FK_NONE, false, ARM::AEK_NONE) ARM_CPU_NAME("arm1176jz-s", ARMV6KZ, FK_NONE, false, ARM::AEK_NONE)
ARM_CPU_NAME("mpcore", AK_ARMV6K, FK_VFPV2, false, ARM::AEK_NONE) ARM_CPU_NAME("mpcore", ARMV6K, FK_VFPV2, false, ARM::AEK_NONE)
ARM_CPU_NAME("mpcorenovfp", AK_ARMV6K, FK_NONE, false, ARM::AEK_NONE) ARM_CPU_NAME("mpcorenovfp", ARMV6K, FK_NONE, false, ARM::AEK_NONE)
ARM_CPU_NAME("arm1176jzf-s", AK_ARMV6KZ, FK_VFPV2, true, ARM::AEK_NONE) ARM_CPU_NAME("arm1176jzf-s", ARMV6KZ, FK_VFPV2, true, ARM::AEK_NONE)
ARM_CPU_NAME("arm1156t2-s", AK_ARMV6T2, FK_NONE, true, ARM::AEK_NONE) ARM_CPU_NAME("arm1156t2-s", ARMV6T2, FK_NONE, true, ARM::AEK_NONE)
ARM_CPU_NAME("arm1156t2f-s", AK_ARMV6T2, FK_VFPV2, false, ARM::AEK_NONE) ARM_CPU_NAME("arm1156t2f-s", ARMV6T2, FK_VFPV2, false, ARM::AEK_NONE)
ARM_CPU_NAME("cortex-m0", AK_ARMV6M, FK_NONE, true, ARM::AEK_NONE) ARM_CPU_NAME("cortex-m0", ARMV6M, FK_NONE, true, ARM::AEK_NONE)
ARM_CPU_NAME("cortex-m0plus", AK_ARMV6M, FK_NONE, false, ARM::AEK_NONE) ARM_CPU_NAME("cortex-m0plus", ARMV6M, FK_NONE, false, ARM::AEK_NONE)
ARM_CPU_NAME("cortex-m1", AK_ARMV6M, FK_NONE, false, ARM::AEK_NONE) ARM_CPU_NAME("cortex-m1", ARMV6M, FK_NONE, false, ARM::AEK_NONE)
ARM_CPU_NAME("sc000", AK_ARMV6M, FK_NONE, false, ARM::AEK_NONE) ARM_CPU_NAME("sc000", ARMV6M, FK_NONE, false, ARM::AEK_NONE)
ARM_CPU_NAME("cortex-a5", AK_ARMV7A, FK_NEON_VFPV4, false, ARM_CPU_NAME("cortex-a5", ARMV7A, FK_NEON_VFPV4, false,
(ARM::AEK_SEC | ARM::AEK_MP)) (ARM::AEK_SEC | ARM::AEK_MP))
ARM_CPU_NAME("cortex-a7", AK_ARMV7A, FK_NEON_VFPV4, false, ARM_CPU_NAME("cortex-a7", ARMV7A, FK_NEON_VFPV4, false,
(ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
ARM::AEK_HWDIVTHUMB)) ARM::AEK_HWDIVTHUMB))
ARM_CPU_NAME("cortex-a8", AK_ARMV7A, FK_NEON, false, ARM::AEK_SEC) ARM_CPU_NAME("cortex-a8", ARMV7A, FK_NEON, false, ARM::AEK_SEC)
ARM_CPU_NAME("cortex-a9", AK_ARMV7A, FK_NEON_FP16, false, (ARM::AEK_SEC | ARM::AEK_MP)) ARM_CPU_NAME("cortex-a9", ARMV7A, FK_NEON_FP16, false, (ARM::AEK_SEC | ARM::AEK_MP))
ARM_CPU_NAME("cortex-a12", AK_ARMV7A, FK_NEON_VFPV4, false, ARM_CPU_NAME("cortex-a12", ARMV7A, FK_NEON_VFPV4, false,
(ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
ARM::AEK_HWDIVTHUMB)) ARM::AEK_HWDIVTHUMB))
ARM_CPU_NAME("cortex-a15", AK_ARMV7A, FK_NEON_VFPV4, false, ARM_CPU_NAME("cortex-a15", ARMV7A, FK_NEON_VFPV4, false,
(ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
ARM::AEK_HWDIVTHUMB)) ARM::AEK_HWDIVTHUMB))
ARM_CPU_NAME("cortex-a17", AK_ARMV7A, FK_NEON_VFPV4, false, ARM_CPU_NAME("cortex-a17", ARMV7A, FK_NEON_VFPV4, false,
(ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
ARM::AEK_HWDIVTHUMB)) ARM::AEK_HWDIVTHUMB))
ARM_CPU_NAME("krait", AK_ARMV7A, FK_NEON_VFPV4, false, ARM_CPU_NAME("krait", ARMV7A, FK_NEON_VFPV4, false,
(ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB)) (ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB))
ARM_CPU_NAME("cortex-r4", AK_ARMV7R, FK_NONE, true, ARM::AEK_NONE) ARM_CPU_NAME("cortex-r4", ARMV7R, FK_NONE, true, ARM::AEK_NONE)
ARM_CPU_NAME("cortex-r4f", AK_ARMV7R, FK_VFPV3_D16, false, ARM::AEK_NONE) ARM_CPU_NAME("cortex-r4f", ARMV7R, FK_VFPV3_D16, false, ARM::AEK_NONE)
ARM_CPU_NAME("cortex-r5", AK_ARMV7R, FK_VFPV3_D16, false, ARM_CPU_NAME("cortex-r5", ARMV7R, FK_VFPV3_D16, false,
(ARM::AEK_MP | ARM::AEK_HWDIVARM)) (ARM::AEK_MP | ARM::AEK_HWDIVARM))
ARM_CPU_NAME("cortex-r7", AK_ARMV7R, FK_VFPV3_D16_FP16, false, ARM_CPU_NAME("cortex-r7", ARMV7R, FK_VFPV3_D16_FP16, false,
(ARM::AEK_MP | ARM::AEK_HWDIVARM)) (ARM::AEK_MP | ARM::AEK_HWDIVARM))
ARM_CPU_NAME("cortex-r8", AK_ARMV7R, FK_VFPV3_D16_FP16, false, ARM_CPU_NAME("cortex-r8", ARMV7R, FK_VFPV3_D16_FP16, false,
(ARM::AEK_MP | ARM::AEK_HWDIVARM)) (ARM::AEK_MP | ARM::AEK_HWDIVARM))
ARM_CPU_NAME("cortex-r52", AK_ARMV8R, FK_NEON_FP_ARMV8, true, ARM::AEK_NONE) ARM_CPU_NAME("cortex-r52", ARMV8R, FK_NEON_FP_ARMV8, true, ARM::AEK_NONE)
ARM_CPU_NAME("sc300", AK_ARMV7M, FK_NONE, false, ARM::AEK_NONE) ARM_CPU_NAME("sc300", ARMV7M, FK_NONE, false, ARM::AEK_NONE)
ARM_CPU_NAME("cortex-m3", AK_ARMV7M, FK_NONE, true, ARM::AEK_NONE) ARM_CPU_NAME("cortex-m3", ARMV7M, FK_NONE, true, ARM::AEK_NONE)
ARM_CPU_NAME("cortex-m4", AK_ARMV7EM, FK_FPV4_SP_D16, true, ARM::AEK_NONE) ARM_CPU_NAME("cortex-m4", ARMV7EM, FK_FPV4_SP_D16, true, ARM::AEK_NONE)
ARM_CPU_NAME("cortex-m7", AK_ARMV7EM, FK_FPV5_D16, false, ARM::AEK_NONE) ARM_CPU_NAME("cortex-m7", ARMV7EM, FK_FPV5_D16, false, ARM::AEK_NONE)
ARM_CPU_NAME("cortex-m23", AK_ARMV8MBaseline, FK_NONE, false, ARM::AEK_NONE) ARM_CPU_NAME("cortex-m23", ARMV8MBaseline, FK_NONE, false, ARM::AEK_NONE)
ARM_CPU_NAME("cortex-m33", AK_ARMV8MMainline, FK_FPV5_SP_D16, false, ARM::AEK_DSP) ARM_CPU_NAME("cortex-m33", ARMV8MMainline, FK_FPV5_SP_D16, false, ARM::AEK_DSP)
ARM_CPU_NAME("cortex-a32", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC) ARM_CPU_NAME("cortex-a32", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
ARM_CPU_NAME("cortex-a35", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC) ARM_CPU_NAME("cortex-a35", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
ARM_CPU_NAME("cortex-a53", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC) ARM_CPU_NAME("cortex-a53", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
ARM_CPU_NAME("cortex-a57", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC) ARM_CPU_NAME("cortex-a57", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
ARM_CPU_NAME("cortex-a72", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC) ARM_CPU_NAME("cortex-a72", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
ARM_CPU_NAME("cortex-a73", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC) ARM_CPU_NAME("cortex-a73", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
ARM_CPU_NAME("cyclone", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC) ARM_CPU_NAME("cyclone", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
ARM_CPU_NAME("exynos-m1", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC) ARM_CPU_NAME("exynos-m1", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
ARM_CPU_NAME("exynos-m2", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC) ARM_CPU_NAME("exynos-m2", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
ARM_CPU_NAME("exynos-m3", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC) ARM_CPU_NAME("exynos-m3", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
ARM_CPU_NAME("kryo", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC) ARM_CPU_NAME("kryo", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
// Non-standard Arch names. // Non-standard Arch names.
ARM_CPU_NAME("iwmmxt", AK_IWMMXT, FK_NONE, true, ARM::AEK_NONE) ARM_CPU_NAME("iwmmxt", IWMMXT, FK_NONE, true, ARM::AEK_NONE)
ARM_CPU_NAME("xscale", AK_XSCALE, FK_NONE, true, ARM::AEK_NONE) ARM_CPU_NAME("xscale", XSCALE, FK_NONE, true, ARM::AEK_NONE)
ARM_CPU_NAME("swift", AK_ARMV7S, FK_NEON_VFPV4, true, ARM_CPU_NAME("swift", ARMV7S, FK_NEON_VFPV4, true,
(ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB)) (ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB))
// Invalid CPU // Invalid CPU
ARM_CPU_NAME("invalid", AK_INVALID, FK_INVALID, true, ARM::AEK_INVALID) ARM_CPU_NAME("invalid", INVALID, FK_INVALID, true, ARM::AEK_INVALID)
#undef ARM_CPU_NAME #undef ARM_CPU_NAME

include/llvm/Support/TargetParser.h

Show All 25 Lines
// Target specific information into their own namespaces. These should be // Target specific information into their own namespaces. These should be
// generated from TableGen because the information is already there, and there // generated from TableGen because the information is already there, and there
// is where new information about targets will be added. // is where new information about targets will be added.
// FIXME: To TableGen this we need to make some table generated files available // FIXME: To TableGen this we need to make some table generated files available
// even if the back-end is not compiled with LLVM, plus we need to create a new // even if the back-end is not compiled with LLVM, plus we need to create a new
// back-end to TableGen to create these clean tables. // back-end to TableGen to create these clean tables.
namespace ARM { namespace ARM {
// FPU names. // FPU Version
enum FPUKind { enum class FPUVersion {
#define ARM_FPU(NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION) KIND, NONE,
#include "ARMTargetParser.def" VFPV2,
FK_LAST VFPV3,
VFPV3_FP16,
VFPV4,
VFPV5
}; };
// FPU Version // An FPU name restricts the FPU in one of three ways:
enum FPUVersion { enum class FPURestriction {
FV_NONE = 0, None = 0, ///< No restriction
FV_VFPV2, D16, ///< Only 16 D registers
FV_VFPV3, SP_D16 ///< Only single-precision instructions, with 16 D registers
FV_VFPV3_FP16,
FV_VFPV4,
FV_VFPV5
}; };
// An FPU name implies one of three levels of Neon support: // An FPU name implies one of three levels of Neon support:
enum NeonSupportLevel { enum class NeonSupportLevel {
NS_None = 0, ///< No Neon None = 0, ///< No Neon
NS_Neon, ///< Neon Neon, ///< Neon
NS_Crypto ///< Neon with Crypto Crypto ///< Neon with Crypto
}; };
// An FPU name restricts the FPU in one of three ways: // FPU names.
enum FPURestriction { enum FPUKind {
FR_None = 0, ///< No restriction #define ARM_FPU(NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION) KIND,
FR_D16, ///< Only 16 D registers #include "ARMTargetParser.def"
FR_SP_D16 ///< Only single-precision instructions, with 16 D registers FK_LAST
}; };
// Arch names. // Arch names.
enum ArchKind { enum class ArchKind {
#define ARM_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) ID, #define ARM_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) ID,
#include "ARMTargetParser.def" #include "ARMTargetParser.def"
AK_LAST
}; };
// Arch extension modifiers for CPUs. // Arch extension modifiers for CPUs.
enum ArchExtKind : unsigned { enum ArchExtKind : unsigned {
AEK_INVALID = 0x0, AEK_INVALID = 0x0,
AEK_NONE = 0x1, AEK_NONE = 0x1,
AEK_CRC = 0x2, AEK_CRC = 0x2,
AEK_CRYPTO = 0x4, AEK_CRYPTO = 0x4,
Show All 12 Linesenum ArchExtKind : unsigned {
AEK_OS = 0x8000000, AEK_OS = 0x8000000,
AEK_IWMMXT = 0x10000000, AEK_IWMMXT = 0x10000000,
AEK_IWMMXT2 = 0x20000000, AEK_IWMMXT2 = 0x20000000,
AEK_MAVERICK = 0x40000000, AEK_MAVERICK = 0x40000000,
AEK_XSCALE = 0x80000000, AEK_XSCALE = 0x80000000,
}; };
// ISA kinds. // ISA kinds.
enum ISAKind { IK_INVALID = 0, IK_ARM, IK_THUMB, IK_AARCH64 }; enum class ISAKind { INVALID = 0, ARM, THUMB, AARCH64 };
// Endianness // Endianness
// FIXME: BE8 vs. BE32? // FIXME: BE8 vs. BE32?
enum EndianKind { EK_INVALID = 0, EK_LITTLE, EK_BIG }; enum class EndianKind { INVALID = 0, LITTLE, BIG };
// v6/v7/v8 Profile // v6/v7/v8 Profile
enum ProfileKind { PK_INVALID = 0, PK_A, PK_R, PK_M }; enum class ProfileKind { INVALID = 0, A, R, M };
StringRef getCanonicalArchName(StringRef Arch); StringRef getCanonicalArchName(StringRef Arch);
// Information by ID // Information by ID
StringRef getFPUName(unsigned FPUKind); StringRef getFPUName(unsigned FPUKind);
unsigned getFPUVersion(unsigned FPUKind); FPUVersion getFPUVersion(unsigned FPUKind);
unsigned getFPUNeonSupportLevel(unsigned FPUKind); NeonSupportLevel getFPUNeonSupportLevel(unsigned FPUKind);
unsigned getFPURestriction(unsigned FPUKind); FPURestriction getFPURestriction(unsigned FPUKind);
// FIXME: These should be moved to TargetTuple once it exists // FIXME: These should be moved to TargetTuple once it exists
bool getFPUFeatures(unsigned FPUKind, std::vector<StringRef> &Features); bool getFPUFeatures(unsigned FPUKind, std::vector<StringRef> &Features);
bool getHWDivFeatures(unsigned HWDivKind, std::vector<StringRef> &Features); bool getHWDivFeatures(unsigned HWDivKind, std::vector<StringRef> &Features);
bool getExtensionFeatures(unsigned Extensions, bool getExtensionFeatures(unsigned Extensions,
std::vector<StringRef> &Features); std::vector<StringRef> &Features);
StringRef getArchName(unsigned ArchKind); StringRef getArchName(ArchKind AK);
unsigned getArchAttr(unsigned ArchKind); unsigned getArchAttr(ArchKind AK);
StringRef getCPUAttr(unsigned ArchKind); StringRef getCPUAttr(ArchKind AK);
StringRef getSubArch(unsigned ArchKind); StringRef getSubArch(ArchKind AK);
StringRef getArchExtName(unsigned ArchExtKind); StringRef getArchExtName(unsigned ArchExtKind);
StringRef getArchExtFeature(StringRef ArchExt); StringRef getArchExtFeature(StringRef ArchExt);
StringRef getHWDivName(unsigned HWDivKind); StringRef getHWDivName(unsigned HWDivKind);
// Information by Name // Information by Name
unsigned getDefaultFPU(StringRef CPU, unsigned ArchKind); unsigned getDefaultFPU(StringRef CPU, ArchKind AK);
unsigned getDefaultExtensions(StringRef CPU, unsigned ArchKind); unsigned getDefaultExtensions(StringRef CPU, ArchKind AK);
StringRef getDefaultCPU(StringRef Arch); StringRef getDefaultCPU(StringRef Arch);
// Parser // Parser
unsigned parseHWDiv(StringRef HWDiv); unsigned parseHWDiv(StringRef HWDiv);
unsigned parseFPU(StringRef FPU); unsigned parseFPU(StringRef FPU);
unsigned parseArch(StringRef Arch); ArchKind parseArch(StringRef Arch);
unsigned parseArchExt(StringRef ArchExt); unsigned parseArchExt(StringRef ArchExt);
unsigned parseCPUArch(StringRef CPU); ArchKind parseCPUArch(StringRef CPU);
unsigned parseArchISA(StringRef Arch); ISAKind parseArchISA(StringRef Arch);
unsigned parseArchEndian(StringRef Arch); EndianKind parseArchEndian(StringRef Arch);
unsigned parseArchProfile(StringRef Arch); ProfileKind parseArchProfile(StringRef Arch);
unsigned parseArchVersion(StringRef Arch); unsigned parseArchVersion(StringRef Arch);
StringRef computeDefaultTargetABI(const Triple &TT, StringRef CPU); StringRef computeDefaultTargetABI(const Triple &TT, StringRef CPU);
} // namespace ARM } // namespace ARM
// FIXME:This should be made into class design,to avoid dupplication. // FIXME:This should be made into class design,to avoid dupplication.
namespace AArch64 { namespace AArch64 {
// Arch names. // Arch names.
enum class ArchKind { enum class ArchKind {
#define AARCH64_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) ID, #define AARCH64_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) ID,
#include "AArch64TargetParser.def" #include "AArch64TargetParser.def"
AK_LAST
}; };
// Arch extension modifiers for CPUs. // Arch extension modifiers for CPUs.
enum ArchExtKind : unsigned { enum ArchExtKind : unsigned {
AEK_INVALID = 0x0, AEK_INVALID = 0x0,
AEK_NONE = 0x1, AEK_NONE = 0x1,
AEK_CRC = 0x2, AEK_CRC = 0x2,
AEK_CRYPTO = 0x4, AEK_CRYPTO = 0x4,
AEK_FP = 0x8, AEK_FP = 0x8,
AEK_SIMD = 0x10, AEK_SIMD = 0x10,
AEK_FP16 = 0x20, AEK_FP16 = 0x20,
AEK_PROFILE = 0x40, AEK_PROFILE = 0x40,
AEK_RAS = 0x80, AEK_RAS = 0x80,
AEK_LSE = 0x100, AEK_LSE = 0x100,
AEK_SVE = 0x200 AEK_SVE = 0x200
}; };
StringRef getCanonicalArchName(StringRef Arch); StringRef getCanonicalArchName(StringRef Arch);
// Information by ID // Information by ID
StringRef getFPUName(unsigned FPUKind); StringRef getFPUName(unsigned FPUKind);
unsigned getFPUVersion(unsigned FPUKind); ARM::FPUVersion getFPUVersion(unsigned FPUKind);
unsigned getFPUNeonSupportLevel(unsigned FPUKind); ARM::NeonSupportLevel getFPUNeonSupportLevel(unsigned FPUKind);
unsigned getFPURestriction(unsigned FPUKind); ARM::FPURestriction getFPURestriction(unsigned FPUKind);
// FIXME: These should be moved to TargetTuple once it exists // FIXME: These should be moved to TargetTuple once it exists
bool getFPUFeatures(unsigned FPUKind, std::vector<StringRef> &Features); bool getFPUFeatures(unsigned FPUKind, std::vector<StringRef> &Features);
bool getExtensionFeatures(unsigned Extensions, bool getExtensionFeatures(unsigned Extensions,
std::vector<StringRef> &Features); std::vector<StringRef> &Features);
bool getArchFeatures(unsigned ArchKind, std::vector<StringRef> &Features); bool getArchFeatures(ArchKind AK, std::vector<StringRef> &Features);
StringRef getArchName(unsigned ArchKind); StringRef getArchName(ArchKind AK);
unsigned getArchAttr(unsigned ArchKind); unsigned getArchAttr(ArchKind AK);
StringRef getCPUAttr(unsigned ArchKind); StringRef getCPUAttr(ArchKind AK);
StringRef getSubArch(unsigned ArchKind); StringRef getSubArch(ArchKind AK);
StringRef getArchExtName(unsigned ArchExtKind); StringRef getArchExtName(unsigned ArchExtKind);
StringRef getArchExtFeature(StringRef ArchExt); StringRef getArchExtFeature(StringRef ArchExt);
unsigned checkArchVersion(StringRef Arch); unsigned checkArchVersion(StringRef Arch);
// Information by Name // Information by Name
unsigned getDefaultFPU(StringRef CPU, unsigned ArchKind); unsigned getDefaultFPU(StringRef CPU, ArchKind AK);
unsigned getDefaultExtensions(StringRef CPU, unsigned ArchKind); unsigned getDefaultExtensions(StringRef CPU, ArchKind AK);
StringRef getDefaultCPU(StringRef Arch); StringRef getDefaultCPU(StringRef Arch);
// Parser // Parser
unsigned parseFPU(StringRef FPU); unsigned parseFPU(StringRef FPU);
unsigned parseArch(StringRef Arch); AArch64::ArchKind parseArch(StringRef Arch);
unsigned parseArchExt(StringRef ArchExt); unsigned parseArchExt(StringRef ArchExt);
unsigned parseCPUArch(StringRef CPU); ArchKind parseCPUArch(StringRef CPU);
unsigned parseArchISA(StringRef Arch); ARM::ISAKind parseArchISA(StringRef Arch);
unsigned parseArchEndian(StringRef Arch); ARM::EndianKind parseArchEndian(StringRef Arch);
unsigned parseArchProfile(StringRef Arch); ARM::ProfileKind parseArchProfile(StringRef Arch);
unsigned parseArchVersion(StringRef Arch); unsigned parseArchVersion(StringRef Arch);
} // namespace AArch64 } // namespace AArch64
} // namespace llvm } // namespace llvm
#endif #endif

lib/Support/TargetParser.cpp

Show First 20 Lines • Show All 69 Lines • ▼ Show 20 Linestemplate <typename T> struct ArchNames {
StringRef getCPUAttr() const { return StringRef(CPUAttrCStr, CPUAttrLength); } StringRef getCPUAttr() const { return StringRef(CPUAttrCStr, CPUAttrLength); }
// Sub-Arch name. // Sub-Arch name.
StringRef getSubArch() const { return StringRef(SubArchCStr, SubArchLength); } StringRef getSubArch() const { return StringRef(SubArchCStr, SubArchLength); }
}; };
ArchNames<ARM::ArchKind> ARCHNames[] = { ArchNames<ARM::ArchKind> ARCHNames[] = {
#define ARM_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) \ #define ARM_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) \
{NAME, sizeof(NAME) - 1, CPU_ATTR, sizeof(CPU_ATTR) - 1, SUB_ARCH, \ {NAME, sizeof(NAME) - 1, CPU_ATTR, sizeof(CPU_ATTR) - 1, SUB_ARCH, \
sizeof(SUB_ARCH) - 1, ARCH_FPU, ARCH_BASE_EXT, ID, ARCH_ATTR}, sizeof(SUB_ARCH) - 1, ARCH_FPU, ARCH_BASE_EXT, ARM::ArchKind::ID, ARCH_ATTR},
#include "llvm/Support/ARMTargetParser.def" #include "llvm/Support/ARMTargetParser.def"
}; };
ArchNames<AArch64::ArchKind> AArch64ARCHNames[] = { ArchNames<AArch64::ArchKind> AArch64ARCHNames[] = {
#define AARCH64_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) \ #define AARCH64_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) \
{NAME, sizeof(NAME) - 1, CPU_ATTR, sizeof(CPU_ATTR) - 1, SUB_ARCH, \ {NAME, sizeof(NAME) - 1, CPU_ATTR, sizeof(CPU_ATTR) - 1, SUB_ARCH, \
sizeof(SUB_ARCH) - 1, ARCH_FPU, ARCH_BASE_EXT, AArch64::ArchKind::ID, ARCH_ATTR}, sizeof(SUB_ARCH) - 1, ARCH_FPU, ARCH_BASE_EXT, AArch64::ArchKind::ID, ARCH_ATTR},
#include "llvm/Support/AArch64TargetParser.def" #include "llvm/Support/AArch64TargetParser.def"
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Linestemplate <typename T> struct CpuNames {
T ArchID; T ArchID;
bool Default; // is $Name the default CPU for $ArchID ? bool Default; // is $Name the default CPU for $ArchID ?
unsigned DefaultExtensions; unsigned DefaultExtensions;
StringRef getName() const { return StringRef(NameCStr, NameLength); } StringRef getName() const { return StringRef(NameCStr, NameLength); }
}; };
CpuNames<ARM::ArchKind> CPUNames[] = { CpuNames<ARM::ArchKind> CPUNames[] = {
#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \ #define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
{ NAME, sizeof(NAME) - 1, ID, IS_DEFAULT, DEFAULT_EXT }, { NAME, sizeof(NAME) - 1, ARM::ArchKind::ID, IS_DEFAULT, DEFAULT_EXT },
#include "llvm/Support/ARMTargetParser.def" #include "llvm/Support/ARMTargetParser.def"
}; };
CpuNames<AArch64::ArchKind> AArch64CPUNames[] = { CpuNames<AArch64::ArchKind> AArch64CPUNames[] = {
#define AARCH64_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \ #define AARCH64_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
{ NAME, sizeof(NAME) - 1, AArch64::ArchKind::ID, IS_DEFAULT, DEFAULT_EXT }, { NAME, sizeof(NAME) - 1, AArch64::ArchKind::ID, IS_DEFAULT, DEFAULT_EXT },
#include "llvm/Support/AArch64TargetParser.def" #include "llvm/Support/AArch64TargetParser.def"
}; };
} // namespace } // namespace
// ======================================================= // // ======================================================= //
// Information by ID // Information by ID
// ======================================================= // // ======================================================= //
StringRef llvm::ARM::getFPUName(unsigned FPUKind) { StringRef ARM::getFPUName(unsigned FPUKind) {
if (FPUKind >= ARM::FK_LAST) if (FPUKind >= ARM::FK_LAST)
return StringRef(); return StringRef();
return FPUNames[FPUKind].getName(); return FPUNames[FPUKind].getName();
} }
unsigned llvm::ARM::getFPUVersion(unsigned FPUKind) { FPUVersion ARM::getFPUVersion(unsigned FPUKind) {
if (FPUKind >= ARM::FK_LAST) if (FPUKind >= ARM::FK_LAST)
return 0; return FPUVersion::NONE;
return FPUNames[FPUKind].FPUVersion; return FPUNames[FPUKind].FPUVersion;
} }
unsigned llvm::ARM::getFPUNeonSupportLevel(unsigned FPUKind) { ARM::NeonSupportLevel ARM::getFPUNeonSupportLevel(unsigned FPUKind) {
if (FPUKind >= ARM::FK_LAST) if (FPUKind >= ARM::FK_LAST)
return 0; return ARM::NeonSupportLevel::None;
return FPUNames[FPUKind].NeonSupport; return FPUNames[FPUKind].NeonSupport;
} }
unsigned llvm::ARM::getFPURestriction(unsigned FPUKind) { ARM::FPURestriction ARM::getFPURestriction(unsigned FPUKind) {
if (FPUKind >= ARM::FK_LAST) if (FPUKind >= ARM::FK_LAST)
return 0; return ARM::FPURestriction::None;
return FPUNames[FPUKind].Restriction; return FPUNames[FPUKind].Restriction;
} }
unsigned llvm::ARM::getDefaultFPU(StringRef CPU, unsigned ArchKind) { unsigned llvm::ARM::getDefaultFPU(StringRef CPU, ArchKind AK) {
if (CPU == "generic") if (CPU == "generic")
return ARCHNames[ArchKind].DefaultFPU; return ARCHNames[static_cast<unsigned>(AK)].DefaultFPU;
return StringSwitch<unsigned>(CPU) return StringSwitch<unsigned>(CPU)
#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \ #define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
.Case(NAME, DEFAULT_FPU) .Case(NAME, DEFAULT_FPU)
#include "llvm/Support/ARMTargetParser.def" #include "llvm/Support/ARMTargetParser.def"
.Default(ARM::FK_INVALID); .Default(ARM::FK_INVALID);
} }
unsigned llvm::ARM::getDefaultExtensions(StringRef CPU, unsigned ArchKind) { unsigned llvm::ARM::getDefaultExtensions(StringRef CPU, ArchKind AK) {
if (CPU == "generic") if (CPU == "generic")
return ARCHNames[ArchKind].ArchBaseExtensions; return ARCHNames[static_cast<unsigned>(AK)].ArchBaseExtensions;
return StringSwitch<unsigned>(CPU) return StringSwitch<unsigned>(CPU)
#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \ #define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
.Case(NAME, ARCHNames[ID].ArchBaseExtensions | DEFAULT_EXT) .Case(NAME, ARCHNames[static_cast<unsigned>(ARM::ArchKind::ID)]\
.ArchBaseExtensions | DEFAULT_EXT)
#include "llvm/Support/ARMTargetParser.def" #include "llvm/Support/ARMTargetParser.def"
.Default(ARM::AEK_INVALID); .Default(ARM::AEK_INVALID);
} }
bool llvm::ARM::getHWDivFeatures(unsigned HWDivKind, bool llvm::ARM::getHWDivFeatures(unsigned HWDivKind,
std::vector<StringRef> &Features) { std::vector<StringRef> &Features) {
if (HWDivKind == ARM::AEK_INVALID) if (HWDivKind == ARM::AEK_INVALID)
Show All 35 Linesbool llvm::ARM::getFPUFeatures(unsigned FPUKind,
std::vector<StringRef> &Features) { std::vector<StringRef> &Features) {
if (FPUKind >= ARM::FK_LAST || FPUKind == ARM::FK_INVALID) if (FPUKind >= ARM::FK_LAST || FPUKind == ARM::FK_INVALID)
return false; return false;
// fp-only-sp and d16 subtarget features are independent of each other, so we // fp-only-sp and d16 subtarget features are independent of each other, so we
// must enable/disable both. // must enable/disable both.
switch (FPUNames[FPUKind].Restriction) { switch (FPUNames[FPUKind].Restriction) {
case ARM::FR_SP_D16: case ARM::FPURestriction::SP_D16:
Features.push_back("+fp-only-sp"); Features.push_back("+fp-only-sp");
Features.push_back("+d16"); Features.push_back("+d16");
break; break;
case ARM::FR_D16: case ARM::FPURestriction::D16:
Features.push_back("-fp-only-sp"); Features.push_back("-fp-only-sp");
Features.push_back("+d16"); Features.push_back("+d16");
break; break;
case ARM::FR_None: case ARM::FPURestriction::None:
Features.push_back("-fp-only-sp"); Features.push_back("-fp-only-sp");
Features.push_back("-d16"); Features.push_back("-d16");
break; break;
} }
// FPU version subtarget features are inclusive of lower-numbered ones, so // FPU version subtarget features are inclusive of lower-numbered ones, so
// enable the one corresponding to this version and disable all that are // enable the one corresponding to this version and disable all that are
// higher. We also have to make sure to disable fp16 when vfp4 is disabled, // higher. We also have to make sure to disable fp16 when vfp4 is disabled,
// as +vfp4 implies +fp16 but -vfp4 does not imply -fp16. // as +vfp4 implies +fp16 but -vfp4 does not imply -fp16.
switch (FPUNames[FPUKind].FPUVersion) { switch (FPUNames[FPUKind].FPUVersion) {
case ARM::FV_VFPV5: case ARM::FPUVersion::VFPV5:
Features.push_back("+fp-armv8"); Features.push_back("+fp-armv8");
break; break;
case ARM::FV_VFPV4: case ARM::FPUVersion::VFPV4:
Features.push_back("+vfp4"); Features.push_back("+vfp4");
Features.push_back("-fp-armv8"); Features.push_back("-fp-armv8");
break; break;
case ARM::FV_VFPV3_FP16: case ARM::FPUVersion::VFPV3_FP16:
Features.push_back("+vfp3"); Features.push_back("+vfp3");
Features.push_back("+fp16"); Features.push_back("+fp16");
Features.push_back("-vfp4"); Features.push_back("-vfp4");
Features.push_back("-fp-armv8"); Features.push_back("-fp-armv8");
break; break;
case ARM::FV_VFPV3: case ARM::FPUVersion::VFPV3:
Features.push_back("+vfp3"); Features.push_back("+vfp3");
Features.push_back("-fp16"); Features.push_back("-fp16");
Features.push_back("-vfp4"); Features.push_back("-vfp4");
Features.push_back("-fp-armv8"); Features.push_back("-fp-armv8");
break; break;
case ARM::FV_VFPV2: case ARM::FPUVersion::VFPV2:
Features.push_back("+vfp2"); Features.push_back("+vfp2");
Features.push_back("-vfp3"); Features.push_back("-vfp3");
Features.push_back("-fp16"); Features.push_back("-fp16");
Features.push_back("-vfp4"); Features.push_back("-vfp4");
Features.push_back("-fp-armv8"); Features.push_back("-fp-armv8");
break; break;
case ARM::FV_NONE: case ARM::FPUVersion::NONE:
Features.push_back("-vfp2"); Features.push_back("-vfp2");
Features.push_back("-vfp3"); Features.push_back("-vfp3");
Features.push_back("-fp16"); Features.push_back("-fp16");
Features.push_back("-vfp4"); Features.push_back("-vfp4");
Features.push_back("-fp-armv8"); Features.push_back("-fp-armv8");
break; break;
} }
// crypto includes neon, so we handle this similarly to FPU version. // crypto includes neon, so we handle this similarly to FPU version.
switch (FPUNames[FPUKind].NeonSupport) { switch (FPUNames[FPUKind].NeonSupport) {
case ARM::NS_Crypto: case ARM::NeonSupportLevel::Crypto:
Features.push_back("+neon"); Features.push_back("+neon");
Features.push_back("+crypto"); Features.push_back("+crypto");
break; break;
case ARM::NS_Neon: case ARM::NeonSupportLevel::Neon:
Features.push_back("+neon"); Features.push_back("+neon");
Features.push_back("-crypto"); Features.push_back("-crypto");
break; break;
case ARM::NS_None: case ARM::NeonSupportLevel::None:
Features.push_back("-neon"); Features.push_back("-neon");
Features.push_back("-crypto"); Features.push_back("-crypto");
break; break;
} }
return true; return true;
} }
StringRef llvm::ARM::getArchName(unsigned ArchKind) { StringRef llvm::ARM::getArchName(ArchKind AK) {
if (ArchKind >= ARM::AK_LAST) return ARCHNames[static_cast<unsigned>(AK)].getName();
return StringRef();
return ARCHNames[ArchKind].getName();
} }
StringRef llvm::ARM::getCPUAttr(unsigned ArchKind) { StringRef llvm::ARM::getCPUAttr(ArchKind AK) {
if (ArchKind == ARM::AK_INVALID || ArchKind >= ARM::AK_LAST) return ARCHNames[static_cast<unsigned>(AK)].getCPUAttr();
return StringRef();
return ARCHNames[ArchKind].getCPUAttr();
} }
StringRef llvm::ARM::getSubArch(unsigned ArchKind) { StringRef llvm::ARM::getSubArch(ArchKind AK) {
if (ArchKind == ARM::AK_INVALID || ArchKind >= ARM::AK_LAST) return ARCHNames[static_cast<unsigned>(AK)].getSubArch();
return StringRef();
return ARCHNames[ArchKind].getSubArch();
} }
unsigned llvm::ARM::getArchAttr(unsigned ArchKind) { unsigned llvm::ARM::getArchAttr(ArchKind AK) {
if (ArchKind >= ARM::AK_LAST) return ARCHNames[static_cast<unsigned>(AK)].ArchAttr;
return ARMBuildAttrs::CPUArch::Pre_v4;
return ARCHNames[ArchKind].ArchAttr;
} }
StringRef llvm::ARM::getArchExtName(unsigned ArchExtKind) { StringRef llvm::ARM::getArchExtName(unsigned ArchExtKind) {
for (const auto AE : ARCHExtNames) { for (const auto AE : ARCHExtNames) {
if (ArchExtKind == AE.ID) if (ArchExtKind == AE.ID)
return AE.getName(); return AE.getName();
} }
return StringRef(); return StringRef();
Show All 19 LinesStringRef llvm::ARM::getHWDivName(unsigned HWDivKind) {
for (const auto D : HWDivNames) { for (const auto D : HWDivNames) {
if (HWDivKind == D.ID) if (HWDivKind == D.ID)
return D.getName(); return D.getName();
} }
return StringRef(); return StringRef();
} }
StringRef llvm::ARM::getDefaultCPU(StringRef Arch) { StringRef llvm::ARM::getDefaultCPU(StringRef Arch) {
unsigned AK = parseArch(Arch); ArchKind AK = parseArch(Arch);
if (AK == ARM::AK_INVALID)
rovkaUnsubmitted
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This can still return INVALID, I don't think you should remove the check just yet.

rovka: This can still return INVALID, I don't think you should remove the check just yet.
fhahnAuthorUnsubmitted
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I thought a change in the .def file made that unnecessary, but I was mistaken.

fhahn: I thought a change in the .def file made that unnecessary, but I was mistaken.
return StringRef();
// Look for multiple AKs to find the default for pair AK+Name. // Look for multiple AKs to find the default for pair AK+Name.
for (const auto CPU : CPUNames) { for (const auto CPU : CPUNames) {
if (CPU.ArchID == AK && CPU.Default) if (CPU.ArchID == AK && CPU.Default)
return CPU.getName(); return CPU.getName();
} }
// If we can't find a default then target the architecture instead // If we can't find a default then target the architecture instead
return "generic"; return "generic";
} }
StringRef llvm::AArch64::getFPUName(unsigned FPUKind) { StringRef llvm::AArch64::getFPUName(unsigned FPUKind) {
return ARM::getFPUName(FPUKind); return ARM::getFPUName(FPUKind);
} }
unsigned llvm::AArch64::getFPUVersion(unsigned FPUKind) { ARM::FPUVersion AArch64::getFPUVersion(unsigned FPUKind) {
return ARM::getFPUVersion(FPUKind); return ARM::getFPUVersion(FPUKind);
} }
unsigned llvm::AArch64::getFPUNeonSupportLevel(unsigned FPUKind) { ARM::NeonSupportLevel AArch64::getFPUNeonSupportLevel(unsigned FPUKind) {
return ARM::getFPUNeonSupportLevel( FPUKind); return ARM::getFPUNeonSupportLevel( FPUKind);
} }
unsigned llvm::AArch64::getFPURestriction(unsigned FPUKind) { ARM::FPURestriction AArch64::getFPURestriction(unsigned FPUKind) {
return ARM::getFPURestriction(FPUKind); return ARM::getFPURestriction(FPUKind);
} }
unsigned llvm::AArch64::getDefaultFPU(StringRef CPU, unsigned ArchKind) { unsigned llvm::AArch64::getDefaultFPU(StringRef CPU, ArchKind AK) {
if (CPU == "generic") if (CPU == "generic")
return AArch64ARCHNames[ArchKind].DefaultFPU; return AArch64ARCHNames[static_cast<unsigned>(AK)].DefaultFPU;
return StringSwitch<unsigned>(CPU) return StringSwitch<unsigned>(CPU)
#define AARCH64_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \ #define AARCH64_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
.Case(NAME, DEFAULT_FPU) .Case(NAME, DEFAULT_FPU)
#include "llvm/Support/AArch64TargetParser.def" #include "llvm/Support/AArch64TargetParser.def"
.Default(ARM::FK_INVALID); .Default(ARM::FK_INVALID);
} }
unsigned llvm::AArch64::getDefaultExtensions(StringRef CPU, unsigned ArchKind) { unsigned llvm::AArch64::getDefaultExtensions(StringRef CPU, ArchKind AK) {
if (CPU == "generic") if (CPU == "generic")
return AArch64ARCHNames[ArchKind].ArchBaseExtensions; return AArch64ARCHNames[static_cast<unsigned>(AK)].ArchBaseExtensions;
return StringSwitch<unsigned>(CPU) return StringSwitch<unsigned>(CPU)
#define AARCH64_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \ #define AARCH64_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
.Case(NAME, \ .Case(NAME, \
AArch64ARCHNames[(unsigned)AArch64::ArchKind::ID].ArchBaseExtensions | \ AArch64ARCHNames[static_cast<unsigned>(AArch64::ArchKind::ID)] \
.ArchBaseExtensions | \
DEFAULT_EXT) DEFAULT_EXT)
#include "llvm/Support/AArch64TargetParser.def" #include "llvm/Support/AArch64TargetParser.def"
.Default(AArch64::AEK_INVALID); .Default(AArch64::AEK_INVALID);
} }
bool llvm::AArch64::getExtensionFeatures(unsigned Extensions, bool llvm::AArch64::getExtensionFeatures(unsigned Extensions,
std::vector<StringRef> &Features) { std::vector<StringRef> &Features) {
Show All 22 Linesbool llvm::AArch64::getExtensionFeatures(unsigned Extensions,
return true; return true;
} }
bool llvm::AArch64::getFPUFeatures(unsigned FPUKind, bool llvm::AArch64::getFPUFeatures(unsigned FPUKind,
std::vector<StringRef> &Features) { std::vector<StringRef> &Features) {
return ARM::getFPUFeatures(FPUKind, Features); return ARM::getFPUFeatures(FPUKind, Features);
} }
bool llvm::AArch64::getArchFeatures(unsigned ArchKind, bool llvm::AArch64::getArchFeatures(AArch64::ArchKind AK,
std::vector<StringRef> &Features) { std::vector<StringRef> &Features) {
if (ArchKind == static_cast<unsigned>(AArch64::ArchKind::AK_ARMV8_1A)) if (AK == AArch64::ArchKind::ARMV8_1A)
Features.push_back("+v8.1a"); Features.push_back("+v8.1a");
if (ArchKind == static_cast<unsigned>(AArch64::ArchKind::AK_ARMV8_2A)) if (AK == AArch64::ArchKind::ARMV8_2A)
Features.push_back("+v8.2a"); Features.push_back("+v8.2a");
return ArchKind > static_cast<unsigned>(AArch64::ArchKind::AK_INVALID) && return AK != AArch64::ArchKind::INVALID;
ArchKind < static_cast<unsigned>(AArch64::ArchKind::AK_LAST);
} }
StringRef llvm::AArch64::getArchName(unsigned ArchKind) { StringRef llvm::AArch64::getArchName(ArchKind AK) {
if (ArchKind >= static_cast<unsigned>(AArch64::ArchKind::AK_LAST)) return AArch64ARCHNames[static_cast<unsigned>(AK)].getName();
return StringRef();
return AArch64ARCHNames[ArchKind].getName();
} }
StringRef llvm::AArch64::getCPUAttr(unsigned ArchKind) { StringRef llvm::AArch64::getCPUAttr(ArchKind AK) {
if (ArchKind == static_cast<unsigned>(AArch64::ArchKind::AK_INVALID) || return AArch64ARCHNames[static_cast<unsigned>(AK)].getCPUAttr();
ArchKind >= static_cast<unsigned>(AArch64::ArchKind::AK_LAST))
return StringRef();
return AArch64ARCHNames[ArchKind].getCPUAttr();
} }
StringRef llvm::AArch64::getSubArch(unsigned ArchKind) { StringRef llvm::AArch64::getSubArch(ArchKind AK) {
if (ArchKind == static_cast<unsigned>(AArch64::ArchKind::AK_INVALID) || return AArch64ARCHNames[static_cast<unsigned>(AK)].getSubArch();
ArchKind >= static_cast<unsigned>(AArch64::ArchKind::AK_LAST))
return StringRef();
return AArch64ARCHNames[ArchKind].getSubArch();
} }
unsigned llvm::AArch64::getArchAttr(unsigned ArchKind) { unsigned llvm::AArch64::getArchAttr(ArchKind AK) {
if (ArchKind >= static_cast<unsigned>(AArch64::ArchKind::AK_LAST)) return AArch64ARCHNames[static_cast<unsigned>(AK)].ArchAttr;
return ARMBuildAttrs::CPUArch::v8_A;
return AArch64ARCHNames[ArchKind].ArchAttr;
} }
StringRef llvm::AArch64::getArchExtName(unsigned ArchExtKind) { StringRef llvm::AArch64::getArchExtName(unsigned ArchExtKind) {
for (const auto &AE : AArch64ARCHExtNames) for (const auto &AE : AArch64ARCHExtNames)
if (ArchExtKind == AE.ID) if (ArchExtKind == AE.ID)
return AE.getName(); return AE.getName();
return StringRef(); return StringRef();
} }
Show All 9 LinesStringRef llvm::AArch64::getArchExtFeature(StringRef ArchExt) {
for (const auto &AE : AArch64ARCHExtNames) for (const auto &AE : AArch64ARCHExtNames)
if (AE.Feature && ArchExt == AE.getName()) if (AE.Feature && ArchExt == AE.getName())
return StringRef(AE.Feature); return StringRef(AE.Feature);
return StringRef(); return StringRef();
} }
StringRef llvm::AArch64::getDefaultCPU(StringRef Arch) { StringRef llvm::AArch64::getDefaultCPU(StringRef Arch) {
unsigned AK = parseArch(Arch); AArch64::ArchKind AK = parseArch(Arch);
if (AK == static_cast<unsigned>(AArch64::ArchKind::AK_INVALID)) if (AK == ArchKind::INVALID)
return StringRef(); return StringRef();
// Look for multiple AKs to find the default for pair AK+Name. // Look for multiple AKs to find the default for pair AK+Name.
for (const auto &CPU : AArch64CPUNames) for (const auto &CPU : AArch64CPUNames)
if (static_cast<unsigned>(CPU.ArchID) == AK && CPU.Default) if (CPU.ArchID == AK && CPU.Default)
return CPU.getName(); return CPU.getName();
// If we can't find a default then target the architecture instead // If we can't find a default then target the architecture instead
return "generic"; return "generic";
} }
unsigned llvm::AArch64::checkArchVersion(StringRef Arch) { unsigned llvm::AArch64::checkArchVersion(StringRef Arch) {
if (Arch[0] == 'v' && std::isdigit(Arch[1])) if (Arch[0] == 'v' && std::isdigit(Arch[1]))
▲ Show 20 Lines • Show All 116 Lines • ▼ Show 20 Linesunsigned llvm::ARM::parseFPU(StringRef FPU) {
for (const auto F : FPUNames) { for (const auto F : FPUNames) {
if (Syn == F.getName()) if (Syn == F.getName())
return F.ID; return F.ID;
} }
return ARM::FK_INVALID; return ARM::FK_INVALID;
} }
// Allows partial match, ex. "v7a" matches "armv7a". // Allows partial match, ex. "v7a" matches "armv7a".
unsigned llvm::ARM::parseArch(StringRef Arch) { ARM::ArchKind ARM::parseArch(StringRef Arch) {
Arch = getCanonicalArchName(Arch); Arch = getCanonicalArchName(Arch);
StringRef Syn = getArchSynonym(Arch); StringRef Syn = getArchSynonym(Arch);
for (const auto A : ARCHNames) { for (const auto A : ARCHNames) {
if (A.getName().endswith(Syn)) if (A.getName().endswith(Syn))
return A.ID; return A.ID;
} }
return ARM::AK_INVALID; return ARM::ArchKind::INVALID;
} }
unsigned llvm::ARM::parseArchExt(StringRef ArchExt) { unsigned llvm::ARM::parseArchExt(StringRef ArchExt) {
for (const auto A : ARCHExtNames) { for (const auto A : ARCHExtNames) {
if (ArchExt == A.getName()) if (ArchExt == A.getName())
return A.ID; return A.ID;
} }
return ARM::AEK_INVALID; return ARM::AEK_INVALID;
} }
unsigned llvm::ARM::parseCPUArch(StringRef CPU) { ARM::ArchKind llvm::ARM::parseCPUArch(StringRef CPU) {
for (const auto C : CPUNames) { for (const auto C : CPUNames) {
if (CPU == C.getName()) if (CPU == C.getName())
return C.ArchID; return C.ArchID;
} }
return ARM::AK_INVALID; return ARM::ArchKind::INVALID;
} }
// ARM, Thumb, AArch64 // ARM, Thumb, AArch64
unsigned llvm::ARM::parseArchISA(StringRef Arch) { ARM::ISAKind ARM::parseArchISA(StringRef Arch) {
return StringSwitch<unsigned>(Arch) return StringSwitch<ARM::ISAKind>(Arch)
.StartsWith("aarch64", ARM::IK_AARCH64) .StartsWith("aarch64", ARM::ISAKind::AARCH64)
.StartsWith("arm64", ARM::IK_AARCH64) .StartsWith("arm64", ARM::ISAKind::AARCH64)
.StartsWith("thumb", ARM::IK_THUMB) .StartsWith("thumb", ARM::ISAKind::THUMB)
.StartsWith("arm", ARM::IK_ARM) .StartsWith("arm", ARM::ISAKind::ARM)
.Default(ARM::IK_INVALID); .Default(ARM::ISAKind::INVALID);
} }
// Little/Big endian // Little/Big endian
unsigned llvm::ARM::parseArchEndian(StringRef Arch) { ARM::EndianKind ARM::parseArchEndian(StringRef Arch) {
if (Arch.startswith("armeb") || Arch.startswith("thumbeb") || if (Arch.startswith("armeb") || Arch.startswith("thumbeb") ||
Arch.startswith("aarch64_be")) Arch.startswith("aarch64_be"))
return ARM::EK_BIG; return ARM::EndianKind::BIG;
if (Arch.startswith("arm") || Arch.startswith("thumb")) { if (Arch.startswith("arm") || Arch.startswith("thumb")) {
if (Arch.endswith("eb")) if (Arch.endswith("eb"))
return ARM::EK_BIG; return ARM::EndianKind::BIG;
else else
return ARM::EK_LITTLE; return ARM::EndianKind::LITTLE;
} }
if (Arch.startswith("aarch64")) if (Arch.startswith("aarch64"))
return ARM::EK_LITTLE; return ARM::EndianKind::LITTLE;
return ARM::EK_INVALID; return ARM::EndianKind::INVALID;
} }
// Profile A/R/M // Profile A/R/M
unsigned llvm::ARM::parseArchProfile(StringRef Arch) { ARM::ProfileKind ARM::parseArchProfile(StringRef Arch) {
Arch = getCanonicalArchName(Arch); Arch = getCanonicalArchName(Arch);
switch (parseArch(Arch)) { switch (parseArch(Arch)) {
case ARM::AK_ARMV6M: case ARM::ArchKind::ARMV6M:
case ARM::AK_ARMV7M: case ARM::ArchKind::ARMV7M:
case ARM::AK_ARMV7EM: case ARM::ArchKind::ARMV7EM:
case ARM::AK_ARMV8MMainline: case ARM::ArchKind::ARMV8MMainline:
case ARM::AK_ARMV8MBaseline: case ARM::ArchKind::ARMV8MBaseline:
return ARM::PK_M; return ARM::ProfileKind::M;
case ARM::AK_ARMV7R: case ARM::ArchKind::ARMV7R:
case ARM::AK_ARMV8R: case ARM::ArchKind::ARMV8R:
return ARM::PK_R; return ARM::ProfileKind::R;
case ARM::AK_ARMV7A: case ARM::ArchKind::ARMV7A:
case ARM::AK_ARMV7VE: case ARM::ArchKind::ARMV7VE:
case ARM::AK_ARMV7K: case ARM::ArchKind::ARMV7K:
case ARM::AK_ARMV8A: case ARM::ArchKind::ARMV8A:
case ARM::AK_ARMV8_1A: case ARM::ArchKind::ARMV8_1A:
case ARM::AK_ARMV8_2A: case ARM::ArchKind::ARMV8_2A:
return ARM::PK_A; return ARM::ProfileKind::A;
default:
return ARM::ProfileKind::INVALID;
} }
return ARM::PK_INVALID;
} }
// Version number (ex. v7 = 7). // Version number (ex. v7 = 7).
unsigned llvm::ARM::parseArchVersion(StringRef Arch) { unsigned llvm::ARM::parseArchVersion(StringRef Arch) {
Arch = getCanonicalArchName(Arch); Arch = getCanonicalArchName(Arch);
switch (parseArch(Arch)) { switch (parseArch(Arch)) {
case ARM::AK_ARMV2: case ARM::ArchKind::ARMV2:
case ARM::AK_ARMV2A: case ARM::ArchKind::ARMV2A:
return 2; return 2;
case ARM::AK_ARMV3: case ARM::ArchKind::ARMV3:
case ARM::AK_ARMV3M: case ARM::ArchKind::ARMV3M:
return 3; return 3;
case ARM::AK_ARMV4: case ARM::ArchKind::ARMV4:
case ARM::AK_ARMV4T: case ARM::ArchKind::ARMV4T:
return 4; return 4;
case ARM::AK_ARMV5T: case ARM::ArchKind::ARMV5T:
case ARM::AK_ARMV5TE: case ARM::ArchKind::ARMV5TE:
case ARM::AK_IWMMXT: case ARM::ArchKind::IWMMXT:
case ARM::AK_IWMMXT2: case ARM::ArchKind::IWMMXT2:
case ARM::AK_XSCALE: case ARM::ArchKind::XSCALE:
case ARM::AK_ARMV5TEJ: case ARM::ArchKind::ARMV5TEJ:
return 5; return 5;
case ARM::AK_ARMV6: case ARM::ArchKind::ARMV6:
case ARM::AK_ARMV6K: case ARM::ArchKind::ARMV6K:
case ARM::AK_ARMV6T2: case ARM::ArchKind::ARMV6T2:
case ARM::AK_ARMV6KZ: case ARM::ArchKind::ARMV6KZ:
case ARM::AK_ARMV6M: case ARM::ArchKind::ARMV6M:
return 6; return 6;
case ARM::AK_ARMV7A: case ARM::ArchKind::ARMV7A:
case ARM::AK_ARMV7VE: case ARM::ArchKind::ARMV7VE:
case ARM::AK_ARMV7R: case ARM::ArchKind::ARMV7R:
case ARM::AK_ARMV7M: case ARM::ArchKind::ARMV7M:
case ARM::AK_ARMV7S: case ARM::ArchKind::ARMV7S:
case ARM::AK_ARMV7EM: case ARM::ArchKind::ARMV7EM:
case ARM::AK_ARMV7K: case ARM::ArchKind::ARMV7K:
return 7; return 7;
case ARM::AK_ARMV8A: case ARM::ArchKind::ARMV8A:
case ARM::AK_ARMV8_1A: case ARM::ArchKind::ARMV8_1A:
case ARM::AK_ARMV8_2A: case ARM::ArchKind::ARMV8_2A:
case ARM::AK_ARMV8R: case ARM::ArchKind::ARMV8R:
case ARM::AK_ARMV8MBaseline: case ARM::ArchKind::ARMV8MBaseline:
case ARM::AK_ARMV8MMainline: case ARM::ArchKind::ARMV8MMainline:
return 8; return 8;
} default:
rovkaUnsubmitted
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I'd rather make the switch fully covered than add a default. Also, you could add an unreachable before the end of the function.

rovka: I'd rather make the switch fully covered than add a default. Also, you could add an unreachable…
fhahnAuthorUnsubmitted
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Excellent point! I've removed the default case from this switch and the switch above in ARM::parseArchProfile.

fhahn: Excellent point! I've removed the default case from this switch and the switch above in ARM…
return 0; return 0;
} }
}
StringRef llvm::ARM::computeDefaultTargetABI(const Triple &TT, StringRef CPU) { StringRef llvm::ARM::computeDefaultTargetABI(const Triple &TT, StringRef CPU) {
StringRef ArchName = StringRef ArchName =
CPU.empty() ? TT.getArchName() : ARM::getArchName(ARM::parseCPUArch(CPU)); CPU.empty() ? TT.getArchName() : ARM::getArchName(ARM::parseCPUArch(CPU));
if (TT.isOSBinFormatMachO()) { if (TT.isOSBinFormatMachO()) {
if (TT.getEnvironment() == Triple::EABI || if (TT.getEnvironment() == Triple::EABI ||
TT.getOS() == Triple::UnknownOS || TT.getOS() == Triple::UnknownOS ||
llvm::ARM::parseArchProfile(ArchName) == ARM::PK_M) llvm::ARM::parseArchProfile(ArchName) == ARM::ProfileKind::M)
return "aapcs"; return "aapcs";
if (TT.isWatchABI()) if (TT.isWatchABI())
return "aapcs16"; return "aapcs16";
return "apcs-gnu"; return "apcs-gnu";
} else if (TT.isOSWindows()) } else if (TT.isOSWindows())
// FIXME: this is invalid for WindowsCE. // FIXME: this is invalid for WindowsCE.
return "aapcs"; return "aapcs";
Show All 21 LinesStringRef llvm::AArch64::getCanonicalArchName(StringRef Arch) {
return ARM::getCanonicalArchName(Arch); return ARM::getCanonicalArchName(Arch);
} }
unsigned llvm::AArch64::parseFPU(StringRef FPU) { unsigned llvm::AArch64::parseFPU(StringRef FPU) {
return ARM::parseFPU(FPU); return ARM::parseFPU(FPU);
} }
// Allows partial match, ex. "v8a" matches "armv8a". // Allows partial match, ex. "v8a" matches "armv8a".
unsigned llvm::AArch64::parseArch(StringRef Arch) { AArch64::ArchKind AArch64::parseArch(StringRef Arch) {
Arch = getCanonicalArchName(Arch); Arch = getCanonicalArchName(Arch);
if (checkArchVersion(Arch) < 8) if (checkArchVersion(Arch) < 8)
return static_cast<unsigned>(AArch64::ArchKind::AK_INVALID); return ArchKind::INVALID;
StringRef Syn = getArchSynonym(Arch); StringRef Syn = getArchSynonym(Arch);
for (const auto A : AArch64ARCHNames) { for (const auto A : AArch64ARCHNames) {
if (A.getName().endswith(Syn)) if (A.getName().endswith(Syn))
return static_cast<unsigned>(A.ID); return A.ID;
} }
return static_cast<unsigned>(AArch64::ArchKind::AK_INVALID); return ArchKind::INVALID;
} }
unsigned llvm::AArch64::parseArchExt(StringRef ArchExt) { unsigned llvm::AArch64::parseArchExt(StringRef ArchExt) {
for (const auto A : AArch64ARCHExtNames) { for (const auto A : AArch64ARCHExtNames) {
if (ArchExt == A.getName()) if (ArchExt == A.getName())
return A.ID; return A.ID;
} }
return AArch64::AEK_INVALID; return AArch64::AEK_INVALID;
} }
unsigned llvm::AArch64::parseCPUArch(StringRef CPU) { AArch64::ArchKind llvm::AArch64::parseCPUArch(StringRef CPU) {
for (const auto C : AArch64CPUNames) { for (const auto C : AArch64CPUNames) {
if (CPU == C.getName()) if (CPU == C.getName())
return static_cast<unsigned>(C.ArchID); return C.ArchID;
} }
return static_cast<unsigned>(AArch64::ArchKind::AK_INVALID); return ArchKind::INVALID;
} }
// ARM, Thumb, AArch64 // ARM, Thumb, AArch64
unsigned llvm::AArch64::parseArchISA(StringRef Arch) { ARM::ISAKind AArch64::parseArchISA(StringRef Arch) {
return ARM::parseArchISA(Arch); return ARM::parseArchISA(Arch);
} }
// Little/Big endian // Little/Big endian
unsigned llvm::AArch64::parseArchEndian(StringRef Arch) { ARM::EndianKind AArch64::parseArchEndian(StringRef Arch) {
return ARM::parseArchEndian(Arch); return ARM::parseArchEndian(Arch);
} }
// Profile A/R/M // Profile A/R/M
unsigned llvm::AArch64::parseArchProfile(StringRef Arch) { ARM::ProfileKind AArch64::parseArchProfile(StringRef Arch) {
return ARM::parseArchProfile(Arch); return ARM::parseArchProfile(Arch);
} }
// Version number (ex. v8 = 8). // Version number (ex. v8 = 8).
unsigned llvm::AArch64::parseArchVersion(StringRef Arch) { unsigned llvm::AArch64::parseArchVersion(StringRef Arch) {
return ARM::parseArchVersion(Arch); return ARM::parseArchVersion(Arch);
} }

lib/Support/Triple.cpp

Show First 20 Lines • Show All 301 Lines • ▼ Show 20 Lines return StringSwitch<Triple::ArchType>(Name)
.Case("wasm32", wasm32) .Case("wasm32", wasm32)
.Case("wasm64", wasm64) .Case("wasm64", wasm64)
.Case("renderscript32", renderscript32) .Case("renderscript32", renderscript32)
.Case("renderscript64", renderscript64) .Case("renderscript64", renderscript64)
.Default(UnknownArch); .Default(UnknownArch);
} }
static Triple::ArchType parseARMArch(StringRef ArchName) { static Triple::ArchType parseARMArch(StringRef ArchName) {
unsigned ISA = ARM::parseArchISA(ArchName); ARM::ISAKind ISA = ARM::parseArchISA(ArchName);
unsigned ENDIAN = ARM::parseArchEndian(ArchName); ARM::EndianKind ENDIAN = ARM::parseArchEndian(ArchName);
Triple::ArchType arch = Triple::UnknownArch; Triple::ArchType arch = Triple::UnknownArch;
switch (ENDIAN) { switch (ENDIAN) {
case ARM::EK_LITTLE: { case ARM::EndianKind::LITTLE: {
switch (ISA) { switch (ISA) {
case ARM::IK_ARM: case ARM::ISAKind::ARM:
arch = Triple::arm; arch = Triple::arm;
break; break;
case ARM::IK_THUMB: case ARM::ISAKind::THUMB:
arch = Triple::thumb; arch = Triple::thumb;
break; break;
case ARM::IK_AARCH64: case ARM::ISAKind::AARCH64:
arch = Triple::aarch64; arch = Triple::aarch64;
break; break;
case ARM::ISAKind::INVALID:
break;
} }
break; break;
} }
case ARM::EK_BIG: { case ARM::EndianKind::BIG: {
switch (ISA) { switch (ISA) {
case ARM::IK_ARM: case ARM::ISAKind::ARM:
arch = Triple::armeb; arch = Triple::armeb;
break; break;
case ARM::IK_THUMB: case ARM::ISAKind::THUMB:
arch = Triple::thumbeb; arch = Triple::thumbeb;
break; break;
case ARM::IK_AARCH64: case ARM::ISAKind::AARCH64:
arch = Triple::aarch64_be; arch = Triple::aarch64_be;
break; break;
case ARM::ISAKind::INVALID:
break;
}
break;
} }
case ARM::EndianKind::INVALID: {
break; break;
} }
} }
ArchName = ARM::getCanonicalArchName(ArchName); ArchName = ARM::getCanonicalArchName(ArchName);
if (ArchName.empty()) if (ArchName.empty())
return Triple::UnknownArch; return Triple::UnknownArch;
// Thumb only exists in v4+ // Thumb only exists in v4+
if (ISA == ARM::IK_THUMB && if (ISA == ARM::ISAKind::THUMB &&
(ArchName.startswith("v2") || ArchName.startswith("v3"))) (ArchName.startswith("v2") || ArchName.startswith("v3")))
return Triple::UnknownArch; return Triple::UnknownArch;
// Thumb only for v6m // Thumb only for v6m
unsigned Profile = ARM::parseArchProfile(ArchName); ARM::ProfileKind Profile = ARM::parseArchProfile(ArchName);
unsigned Version = ARM::parseArchVersion(ArchName); unsigned Version = ARM::parseArchVersion(ArchName);
if (Profile == ARM::PK_M && Version == 6) { if (Profile == ARM::ProfileKind::M && Version == 6) {
if (ENDIAN == ARM::EK_BIG) if (ENDIAN == ARM::EndianKind::BIG)
return Triple::thumbeb; return Triple::thumbeb;
else else
return Triple::thumb; return Triple::thumb;
} }
return arch; return arch;
} }
▲ Show 20 Lines • Show All 162 Lines • ▼ Show 20 Lines if (ARMSubArch.empty())
return StringSwitch<Triple::SubArchType>(SubArchName) return StringSwitch<Triple::SubArchType>(SubArchName)
.EndsWith("kalimba3", Triple::KalimbaSubArch_v3) .EndsWith("kalimba3", Triple::KalimbaSubArch_v3)
.EndsWith("kalimba4", Triple::KalimbaSubArch_v4) .EndsWith("kalimba4", Triple::KalimbaSubArch_v4)
.EndsWith("kalimba5", Triple::KalimbaSubArch_v5) .EndsWith("kalimba5", Triple::KalimbaSubArch_v5)
.Default(Triple::NoSubArch); .Default(Triple::NoSubArch);
// ARM sub arch. // ARM sub arch.
switch(ARM::parseArch(ARMSubArch)) { switch(ARM::parseArch(ARMSubArch)) {
case ARM::AK_ARMV4: case ARM::ArchKind::ARMV4:
return Triple::NoSubArch; return Triple::NoSubArch;
case ARM::AK_ARMV4T: case ARM::ArchKind::ARMV4T:
return Triple::ARMSubArch_v4t; return Triple::ARMSubArch_v4t;
case ARM::AK_ARMV5T: case ARM::ArchKind::ARMV5T:
return Triple::ARMSubArch_v5; return Triple::ARMSubArch_v5;
case ARM::AK_ARMV5TE: case ARM::ArchKind::ARMV5TE:
case ARM::AK_IWMMXT: case ARM::ArchKind::IWMMXT:
case ARM::AK_IWMMXT2: case ARM::ArchKind::IWMMXT2:
case ARM::AK_XSCALE: case ARM::ArchKind::XSCALE:
case ARM::AK_ARMV5TEJ: case ARM::ArchKind::ARMV5TEJ:
return Triple::ARMSubArch_v5te; return Triple::ARMSubArch_v5te;
case ARM::AK_ARMV6: case ARM::ArchKind::ARMV6:
return Triple::ARMSubArch_v6; return Triple::ARMSubArch_v6;
case ARM::AK_ARMV6K: case ARM::ArchKind::ARMV6K:
case ARM::AK_ARMV6KZ: case ARM::ArchKind::ARMV6KZ:
return Triple::ARMSubArch_v6k; return Triple::ARMSubArch_v6k;
case ARM::AK_ARMV6T2: case ARM::ArchKind::ARMV6T2:
return Triple::ARMSubArch_v6t2; return Triple::ARMSubArch_v6t2;
case ARM::AK_ARMV6M: case ARM::ArchKind::ARMV6M:
return Triple::ARMSubArch_v6m; return Triple::ARMSubArch_v6m;
case ARM::AK_ARMV7A: case ARM::ArchKind::ARMV7A:
case ARM::AK_ARMV7R: case ARM::ArchKind::ARMV7R:
return Triple::ARMSubArch_v7; return Triple::ARMSubArch_v7;
case ARM::AK_ARMV7VE: case ARM::ArchKind::ARMV7VE:
return Triple::ARMSubArch_v7ve; return Triple::ARMSubArch_v7ve;
case ARM::AK_ARMV7K: case ARM::ArchKind::ARMV7K:
return Triple::ARMSubArch_v7k; return Triple::ARMSubArch_v7k;
case ARM::AK_ARMV7M: case ARM::ArchKind::ARMV7M:
return Triple::ARMSubArch_v7m; return Triple::ARMSubArch_v7m;
case ARM::AK_ARMV7S: case ARM::ArchKind::ARMV7S:
return Triple::ARMSubArch_v7s; return Triple::ARMSubArch_v7s;
case ARM::AK_ARMV7EM: case ARM::ArchKind::ARMV7EM:
return Triple::ARMSubArch_v7em; return Triple::ARMSubArch_v7em;
case ARM::AK_ARMV8A: case ARM::ArchKind::ARMV8A:
return Triple::ARMSubArch_v8; return Triple::ARMSubArch_v8;
case ARM::AK_ARMV8_1A: case ARM::ArchKind::ARMV8_1A:
return Triple::ARMSubArch_v8_1a; return Triple::ARMSubArch_v8_1a;
case ARM::AK_ARMV8_2A: case ARM::ArchKind::ARMV8_2A:
return Triple::ARMSubArch_v8_2a; return Triple::ARMSubArch_v8_2a;
case ARM::AK_ARMV8R: case ARM::ArchKind::ARMV8R:
return Triple::ARMSubArch_v8r; return Triple::ARMSubArch_v8r;
case ARM::AK_ARMV8MBaseline: case ARM::ArchKind::ARMV8MBaseline:
return Triple::ARMSubArch_v8m_baseline; return Triple::ARMSubArch_v8m_baseline;
case ARM::AK_ARMV8MMainline: case ARM::ArchKind::ARMV8MMainline:
return Triple::ARMSubArch_v8m_mainline; return Triple::ARMSubArch_v8m_mainline;
default: default:
return Triple::NoSubArch; return Triple::NoSubArch;
} }
} }
static StringRef getObjectFormatTypeName(Triple::ObjectFormatType Kind) { static StringRef getObjectFormatTypeName(Triple::ObjectFormatType Kind) {
switch (Kind) { switch (Kind) {
▲ Show 20 Lines • Show All 955 Lines • ▼ Show 20 LinesStringRef Triple::getARMCPUForArch(StringRef MArch) const {
default: default:
break; break;
} }
if (MArch.empty()) if (MArch.empty())
return StringRef(); return StringRef();
StringRef CPU = ARM::getDefaultCPU(MArch); StringRef CPU = ARM::getDefaultCPU(MArch);
if (!CPU.empty()) if (!CPU.empty() && !CPU.equals("invalid"))
return CPU; return CPU;
// If no specific architecture version is requested, return the minimum CPU // If no specific architecture version is requested, return the minimum CPU
// required by the OS and environment. // required by the OS and environment.
switch (getOS()) { switch (getOS()) {
case llvm::Triple::NetBSD: case llvm::Triple::NetBSD:
switch (getEnvironment()) { switch (getEnvironment()) {
case llvm::Triple::GNUEABIHF: case llvm::Triple::GNUEABIHF:
Show All 23 Lines

lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

Show First 20 Lines • Show All 3,856 Lines • ▼ Show 20 Lines
/// ::= .arch token /// ::= .arch token
bool AArch64AsmParser::parseDirectiveArch(SMLoc L) { bool AArch64AsmParser::parseDirectiveArch(SMLoc L) {
SMLoc ArchLoc = getLoc(); SMLoc ArchLoc = getLoc();
StringRef Arch, ExtensionString; StringRef Arch, ExtensionString;
std::tie(Arch, ExtensionString) = std::tie(Arch, ExtensionString) =
getParser().parseStringToEndOfStatement().trim().split('+'); getParser().parseStringToEndOfStatement().trim().split('+');
unsigned ID = AArch64::parseArch(Arch); AArch64::ArchKind ID = AArch64::parseArch(Arch);
if (ID == static_cast<unsigned>(AArch64::ArchKind::AK_INVALID)) if (ID == AArch64::ArchKind::INVALID)
return Error(ArchLoc, "unknown arch name"); return Error(ArchLoc, "unknown arch name");
if (parseToken(AsmToken::EndOfStatement)) if (parseToken(AsmToken::EndOfStatement))
return true; return true;
// Get the architecture and extension features. // Get the architecture and extension features.
std::vector<StringRef> AArch64Features; std::vector<StringRef> AArch64Features;
AArch64::getArchFeatures(ID, AArch64Features); AArch64::getArchFeatures(ID, AArch64Features);
▲ Show 20 Lines • Show All 470 Lines • Show Last 20 Lines

lib/Target/ARM/ARMSubtarget.cpp

Show First 20 Lines • Show All 203 Lines • ▼ Show 20 Lines
} }
void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
if (CPUString.empty()) { if (CPUString.empty()) {
CPUString = "generic"; CPUString = "generic";
if (isTargetDarwin()) { if (isTargetDarwin()) {
StringRef ArchName = TargetTriple.getArchName(); StringRef ArchName = TargetTriple.getArchName();
unsigned ArchKind = ARM::parseArch(ArchName); ARM::ArchKind AK = ARM::parseArch(ArchName);
if (ArchKind == ARM::AK_ARMV7S) if (AK == ARM::ArchKind::ARMV7S)
// Default to the Swift CPU when targeting armv7s/thumbv7s. // Default to the Swift CPU when targeting armv7s/thumbv7s.
CPUString = "swift"; CPUString = "swift";
else if (ArchKind == ARM::AK_ARMV7K) else if (AK == ARM::ArchKind::ARMV7K)
// Default to the Cortex-a7 CPU when targeting armv7k/thumbv7k. // Default to the Cortex-a7 CPU when targeting armv7k/thumbv7k.
// ARMv7k does not use SjLj exception handling. // ARMv7k does not use SjLj exception handling.
CPUString = "cortex-a7"; CPUString = "cortex-a7";
} }
} }
// Insert the architecture feature derived from the target triple into the // Insert the architecture feature derived from the target triple into the
// feature string. This is important for setting features that are implied // feature string. This is important for setting features that are implied
▲ Show 20 Lines • Show All 220 Lines • Show Last 20 Lines

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 9,413 Lines • ▼ Show 20 Lines if (WasThumb != isThumb()) {
} }
} }
} }
/// parseDirectiveArch /// parseDirectiveArch
/// ::= .arch token /// ::= .arch token
bool ARMAsmParser::parseDirectiveArch(SMLoc L) { bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
StringRef Arch = getParser().parseStringToEndOfStatement().trim(); StringRef Arch = getParser().parseStringToEndOfStatement().trim();
unsigned ID = ARM::parseArch(Arch); ARM::ArchKind ID = ARM::parseArch(Arch);
if (ID == ARM::AK_INVALID) if (ID == ARM::ArchKind::INVALID)
return Error(L, "Unknown arch name"); return Error(L, "Unknown arch name");
bool WasThumb = isThumb(); bool WasThumb = isThumb();
Triple T; Triple T;
MCSubtargetInfo &STI = copySTI(); MCSubtargetInfo &STI = copySTI();
STI.setDefaultFeatures("", ("+" + ARM::getArchName(ID)).str()); STI.setDefaultFeatures("", ("+" + ARM::getArchName(ID)).str());
setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
FixModeAfterArchChange(WasThumb, L); FixModeAfterArchChange(WasThumb, L);
▲ Show 20 Lines • Show All 631 Lines • ▼ Show 20 Linesbool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) {
MCAsmParser &Parser = getParser(); MCAsmParser &Parser = getParser();
if (getLexer().isNot(AsmToken::Identifier)) if (getLexer().isNot(AsmToken::Identifier))
return Error(getLexer().getLoc(), "unexpected token"); return Error(getLexer().getLoc(), "unexpected token");
StringRef Arch = Parser.getTok().getString(); StringRef Arch = Parser.getTok().getString();
SMLoc ArchLoc = Parser.getTok().getLoc(); SMLoc ArchLoc = Parser.getTok().getLoc();
Lex(); Lex();
unsigned ID = ARM::parseArch(Arch); ARM::ArchKind ID = ARM::parseArch(Arch);
if (ID == ARM::AK_INVALID) if (ID == ARM::ArchKind::INVALID)
return Error(ArchLoc, "unknown architecture '" + Arch + "'"); return Error(ArchLoc, "unknown architecture '" + Arch + "'");
if (parseToken(AsmToken::EndOfStatement)) if (parseToken(AsmToken::EndOfStatement))
return true; return true;
getTargetStreamer().emitObjectArch(ID); getTargetStreamer().emitObjectArch(ID);
return false; return false;
} }
▲ Show 20 Lines • Show All 170 Lines • Show Last 20 Lines

lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp

Show First 20 Lines • Show All 1,121 Lines • ▼ Show 20 Lines for (int Idx = FloatRegCount - 1; Idx >= 0; --Idx) {
} }
CurOffset -= 8; CurOffset -= 8;
} }
return CompactUnwindEncoding | ((FloatRegCount - 1) << 8); return CompactUnwindEncoding | ((FloatRegCount - 1) << 8);
} }
static MachO::CPUSubTypeARM getMachOSubTypeFromArch(StringRef Arch) { static MachO::CPUSubTypeARM getMachOSubTypeFromArch(StringRef Arch) {
unsigned AK = ARM::parseArch(Arch); ARM::ArchKind AK = ARM::parseArch(Arch);
switch (AK) { switch (AK) {
default: default:
return MachO::CPU_SUBTYPE_ARM_V7; return MachO::CPU_SUBTYPE_ARM_V7;
case ARM::AK_ARMV4T: case ARM::ArchKind::ARMV4T:
return MachO::CPU_SUBTYPE_ARM_V4T; return MachO::CPU_SUBTYPE_ARM_V4T;
case ARM::AK_ARMV5T: case ARM::ArchKind::ARMV5T:
case ARM::AK_ARMV5TE: case ARM::ArchKind::ARMV5TE:
case ARM::AK_ARMV5TEJ: case ARM::ArchKind::ARMV5TEJ:
return MachO::CPU_SUBTYPE_ARM_V5; return MachO::CPU_SUBTYPE_ARM_V5;
case ARM::AK_ARMV6: case ARM::ArchKind::ARMV6:
case ARM::AK_ARMV6K: case ARM::ArchKind::ARMV6K:
return MachO::CPU_SUBTYPE_ARM_V6; return MachO::CPU_SUBTYPE_ARM_V6;
case ARM::AK_ARMV7A: case ARM::ArchKind::ARMV7A:
return MachO::CPU_SUBTYPE_ARM_V7; return MachO::CPU_SUBTYPE_ARM_V7;
case ARM::AK_ARMV7S: case ARM::ArchKind::ARMV7S:
return MachO::CPU_SUBTYPE_ARM_V7S; return MachO::CPU_SUBTYPE_ARM_V7S;
case ARM::AK_ARMV7K: case ARM::ArchKind::ARMV7K:
return MachO::CPU_SUBTYPE_ARM_V7K; return MachO::CPU_SUBTYPE_ARM_V7K;
case ARM::AK_ARMV6M: case ARM::ArchKind::ARMV6M:
return MachO::CPU_SUBTYPE_ARM_V6M; return MachO::CPU_SUBTYPE_ARM_V6M;
case ARM::AK_ARMV7M: case ARM::ArchKind::ARMV7M:
return MachO::CPU_SUBTYPE_ARM_V7M; return MachO::CPU_SUBTYPE_ARM_V7M;
case ARM::AK_ARMV7EM: case ARM::ArchKind::ARMV7EM:
return MachO::CPU_SUBTYPE_ARM_V7EM; return MachO::CPU_SUBTYPE_ARM_V7EM;
} }
} }
MCAsmBackend *llvm::createARMAsmBackend(const Target &T, MCAsmBackend *llvm::createARMAsmBackend(const Target &T,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
const Triple &TheTriple, StringRef CPU, const Triple &TheTriple, StringRef CPU,
const MCTargetOptions &Options, const MCTargetOptions &Options,
▲ Show 20 Lines • Show All 45 Lines • Show Last 20 Lines

lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp

Show First 20 Lines • Show All 86 Lines • ▼ Show 20 Linesclass ARMTargetAsmStreamer : public ARMTargetStreamer {
void emitUnwindRaw(int64_t Offset, void emitUnwindRaw(int64_t Offset,
const SmallVectorImpl<uint8_t> &Opcodes) override; const SmallVectorImpl<uint8_t> &Opcodes) override;
void switchVendor(StringRef Vendor) override; void switchVendor(StringRef Vendor) override;
void emitAttribute(unsigned Attribute, unsigned Value) override; void emitAttribute(unsigned Attribute, unsigned Value) override;
void emitTextAttribute(unsigned Attribute, StringRef String) override; void emitTextAttribute(unsigned Attribute, StringRef String) override;
void emitIntTextAttribute(unsigned Attribute, unsigned IntValue, void emitIntTextAttribute(unsigned Attribute, unsigned IntValue,
StringRef StringValue) override; StringRef StringValue) override;
void emitArch(unsigned Arch) override; void emitArch(ARM::ArchKind Arch) override;
void emitArchExtension(unsigned ArchExt) override; void emitArchExtension(unsigned ArchExt) override;
void emitObjectArch(unsigned Arch) override; void emitObjectArch(ARM::ArchKind Arch) override;
void emitFPU(unsigned FPU) override; void emitFPU(unsigned FPU) override;
void emitInst(uint32_t Inst, char Suffix = '\0') override; void emitInst(uint32_t Inst, char Suffix = '\0') override;
void finishAttributeSection() override; void finishAttributeSection() override;
void AnnotateTLSDescriptorSequence(const MCSymbolRefExpr *SRE) override; void AnnotateTLSDescriptorSequence(const MCSymbolRefExpr *SRE) override;
void emitThumbSet(MCSymbol *Symbol, const MCExpr *Value) override; void emitThumbSet(MCSymbol *Symbol, const MCExpr *Value) override;
public: public:
▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Lines if (!StringValue.empty())
OS << ", \"" << StringValue << "\""; OS << ", \"" << StringValue << "\"";
if (IsVerboseAsm) if (IsVerboseAsm)
OS << "\t@ " << ARMBuildAttrs::AttrTypeAsString(Attribute); OS << "\t@ " << ARMBuildAttrs::AttrTypeAsString(Attribute);
break; break;
} }
OS << "\n"; OS << "\n";
} }
void ARMTargetAsmStreamer::emitArch(unsigned Arch) { void ARMTargetAsmStreamer::emitArch(ARM::ArchKind Arch) {
OS << "\t.arch\t" << ARM::getArchName(Arch) << "\n"; OS << "\t.arch\t" << ARM::getArchName(Arch) << "\n";
} }
void ARMTargetAsmStreamer::emitArchExtension(unsigned ArchExt) { void ARMTargetAsmStreamer::emitArchExtension(unsigned ArchExt) {
OS << "\t.arch_extension\t" << ARM::getArchExtName(ArchExt) << "\n"; OS << "\t.arch_extension\t" << ARM::getArchExtName(ArchExt) << "\n";
} }
void ARMTargetAsmStreamer::emitObjectArch(unsigned Arch) { void ARMTargetAsmStreamer::emitObjectArch(ARM::ArchKind Arch) {
OS << "\t.object_arch\t" << ARM::getArchName(Arch) << '\n'; OS << "\t.object_arch\t" << ARM::getArchName(Arch) << '\n';
} }
void ARMTargetAsmStreamer::emitFPU(unsigned FPU) { void ARMTargetAsmStreamer::emitFPU(unsigned FPU) {
OS << "\t.fpu\t" << ARM::getFPUName(FPU) << "\n"; OS << "\t.fpu\t" << ARM::getFPUName(FPU) << "\n";
} }
void ARMTargetAsmStreamer::finishAttributeSection() {} void ARMTargetAsmStreamer::finishAttributeSection() {}
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines static bool LessTag(const AttributeItem &LHS, const AttributeItem &RHS) {
// attributes are sorted in finishAttributeSection(). // attributes are sorted in finishAttributeSection().
return (RHS.Tag != ARMBuildAttrs::conformance) && return (RHS.Tag != ARMBuildAttrs::conformance) &&
((LHS.Tag == ARMBuildAttrs::conformance) || (LHS.Tag < RHS.Tag)); ((LHS.Tag == ARMBuildAttrs::conformance) || (LHS.Tag < RHS.Tag));
} }
}; };
StringRef CurrentVendor; StringRef CurrentVendor;
unsigned FPU = ARM::FK_INVALID; unsigned FPU = ARM::FK_INVALID;
unsigned Arch = ARM::AK_INVALID; ARM::ArchKind Arch = ARM::ArchKind::INVALID;
unsigned EmittedArch = ARM::AK_INVALID; ARM::ArchKind EmittedArch = ARM::ArchKind::INVALID;
SmallVector<AttributeItem, 64> Contents; SmallVector<AttributeItem, 64> Contents;
MCSection *AttributeSection = nullptr; MCSection *AttributeSection = nullptr;
AttributeItem *getAttributeItem(unsigned Attribute) { AttributeItem *getAttributeItem(unsigned Attribute) {
for (size_t i = 0; i < Contents.size(); ++i) for (size_t i = 0; i < Contents.size(); ++i)
if (Contents[i].Tag == Attribute) if (Contents[i].Tag == Attribute)
return &Contents[i]; return &Contents[i];
▲ Show 20 Lines • Show All 83 Lines • ▼ Show 20 Linesprivate:
void emitUnwindRaw(int64_t Offset, void emitUnwindRaw(int64_t Offset,
const SmallVectorImpl<uint8_t> &Opcodes) override; const SmallVectorImpl<uint8_t> &Opcodes) override;
void switchVendor(StringRef Vendor) override; void switchVendor(StringRef Vendor) override;
void emitAttribute(unsigned Attribute, unsigned Value) override; void emitAttribute(unsigned Attribute, unsigned Value) override;
void emitTextAttribute(unsigned Attribute, StringRef String) override; void emitTextAttribute(unsigned Attribute, StringRef String) override;
void emitIntTextAttribute(unsigned Attribute, unsigned IntValue, void emitIntTextAttribute(unsigned Attribute, unsigned IntValue,
StringRef StringValue) override; StringRef StringValue) override;
void emitArch(unsigned Arch) override; void emitArch(ARM::ArchKind Arch) override;
void emitObjectArch(unsigned Arch) override; void emitObjectArch(ARM::ArchKind Arch) override;
void emitFPU(unsigned FPU) override; void emitFPU(unsigned FPU) override;
void emitInst(uint32_t Inst, char Suffix = '\0') override; void emitInst(uint32_t Inst, char Suffix = '\0') override;
void finishAttributeSection() override; void finishAttributeSection() override;
void emitLabel(MCSymbol *Symbol) override; void emitLabel(MCSymbol *Symbol) override;
void AnnotateTLSDescriptorSequence(const MCSymbolRefExpr *SRE) override; void AnnotateTLSDescriptorSequence(const MCSymbolRefExpr *SRE) override;
void emitThumbSet(MCSymbol *Symbol, const MCExpr *Value) override; void emitThumbSet(MCSymbol *Symbol, const MCExpr *Value) override;
▲ Show 20 Lines • Show All 354 Lines • ▼ Show 20 Lines
void ARMTargetELFStreamer::emitIntTextAttribute(unsigned Attribute, void ARMTargetELFStreamer::emitIntTextAttribute(unsigned Attribute,
unsigned IntValue, unsigned IntValue,
StringRef StringValue) { StringRef StringValue) {
setAttributeItems(Attribute, IntValue, StringValue, setAttributeItems(Attribute, IntValue, StringValue,
/* OverwriteExisting= */ true); /* OverwriteExisting= */ true);
} }
void ARMTargetELFStreamer::emitArch(unsigned Value) { void ARMTargetELFStreamer::emitArch(ARM::ArchKind Value) {
Arch = Value; Arch = Value;
} }
void ARMTargetELFStreamer::emitObjectArch(unsigned Value) { void ARMTargetELFStreamer::emitObjectArch(ARM::ArchKind Value) {
EmittedArch = Value; EmittedArch = Value;
} }
void ARMTargetELFStreamer::emitArchDefaultAttributes() { void ARMTargetELFStreamer::emitArchDefaultAttributes() {
using namespace ARMBuildAttrs; using namespace ARMBuildAttrs;
setAttributeItem(CPU_name, setAttributeItem(CPU_name,
ARM::getCPUAttr(Arch), ARM::getCPUAttr(Arch),
false); false);
if (EmittedArch == ARM::AK_INVALID) if (EmittedArch == ARM::ArchKind::INVALID)
setAttributeItem(CPU_arch, setAttributeItem(CPU_arch,
ARM::getArchAttr(Arch), ARM::getArchAttr(Arch),
false); false);
else else
setAttributeItem(CPU_arch, setAttributeItem(CPU_arch,
ARM::getArchAttr(EmittedArch), ARM::getArchAttr(EmittedArch),
false); false);
switch (Arch) { switch (Arch) {
case ARM::AK_ARMV2: case ARM::ArchKind::ARMV2:
case ARM::AK_ARMV2A: case ARM::ArchKind::ARMV2A:
case ARM::AK_ARMV3: case ARM::ArchKind::ARMV3:
case ARM::AK_ARMV3M: case ARM::ArchKind::ARMV3M:
case ARM::AK_ARMV4: case ARM::ArchKind::ARMV4:
setAttributeItem(ARM_ISA_use, Allowed, false); setAttributeItem(ARM_ISA_use, Allowed, false);
break; break;
case ARM::AK_ARMV4T: case ARM::ArchKind::ARMV4T:
case ARM::AK_ARMV5T: case ARM::ArchKind::ARMV5T:
case ARM::AK_ARMV5TE: case ARM::ArchKind::ARMV5TE:
case ARM::AK_ARMV6: case ARM::ArchKind::ARMV6:
setAttributeItem(ARM_ISA_use, Allowed, false); setAttributeItem(ARM_ISA_use, Allowed, false);
setAttributeItem(THUMB_ISA_use, Allowed, false); setAttributeItem(THUMB_ISA_use, Allowed, false);
break; break;
case ARM::AK_ARMV6T2: case ARM::ArchKind::ARMV6T2:
setAttributeItem(ARM_ISA_use, Allowed, false); setAttributeItem(ARM_ISA_use, Allowed, false);
setAttributeItem(THUMB_ISA_use, AllowThumb32, false); setAttributeItem(THUMB_ISA_use, AllowThumb32, false);
break; break;
case ARM::AK_ARMV6K: case ARM::ArchKind::ARMV6K:
case ARM::AK_ARMV6KZ: case ARM::ArchKind::ARMV6KZ:
setAttributeItem(ARM_ISA_use, Allowed, false); setAttributeItem(ARM_ISA_use, Allowed, false);
setAttributeItem(THUMB_ISA_use, Allowed, false); setAttributeItem(THUMB_ISA_use, Allowed, false);
setAttributeItem(Virtualization_use, AllowTZ, false); setAttributeItem(Virtualization_use, AllowTZ, false);
break; break;
case ARM::AK_ARMV6M: case ARM::ArchKind::ARMV6M:
setAttributeItem(THUMB_ISA_use, Allowed, false); setAttributeItem(THUMB_ISA_use, Allowed, false);
break; break;
case ARM::AK_ARMV7A: case ARM::ArchKind::ARMV7A:
setAttributeItem(CPU_arch_profile, ApplicationProfile, false); setAttributeItem(CPU_arch_profile, ApplicationProfile, false);
setAttributeItem(ARM_ISA_use, Allowed, false); setAttributeItem(ARM_ISA_use, Allowed, false);
setAttributeItem(THUMB_ISA_use, AllowThumb32, false); setAttributeItem(THUMB_ISA_use, AllowThumb32, false);
break; break;
case ARM::AK_ARMV7R: case ARM::ArchKind::ARMV7R:
setAttributeItem(CPU_arch_profile, RealTimeProfile, false); setAttributeItem(CPU_arch_profile, RealTimeProfile, false);
setAttributeItem(ARM_ISA_use, Allowed, false); setAttributeItem(ARM_ISA_use, Allowed, false);
setAttributeItem(THUMB_ISA_use, AllowThumb32, false); setAttributeItem(THUMB_ISA_use, AllowThumb32, false);
break; break;
case ARM::AK_ARMV7M: case ARM::ArchKind::ARMV7M:
setAttributeItem(CPU_arch_profile, MicroControllerProfile, false); setAttributeItem(CPU_arch_profile, MicroControllerProfile, false);
setAttributeItem(THUMB_ISA_use, AllowThumb32, false); setAttributeItem(THUMB_ISA_use, AllowThumb32, false);
break; break;
case ARM::AK_ARMV8A: case ARM::ArchKind::ARMV8A:
case ARM::AK_ARMV8_1A: case ARM::ArchKind::ARMV8_1A:
case ARM::AK_ARMV8_2A: case ARM::ArchKind::ARMV8_2A:
setAttributeItem(CPU_arch_profile, ApplicationProfile, false); setAttributeItem(CPU_arch_profile, ApplicationProfile, false);
setAttributeItem(ARM_ISA_use, Allowed, false); setAttributeItem(ARM_ISA_use, Allowed, false);
setAttributeItem(THUMB_ISA_use, AllowThumb32, false); setAttributeItem(THUMB_ISA_use, AllowThumb32, false);
setAttributeItem(MPextension_use, Allowed, false); setAttributeItem(MPextension_use, Allowed, false);
setAttributeItem(Virtualization_use, AllowTZVirtualization, false); setAttributeItem(Virtualization_use, AllowTZVirtualization, false);
break; break;
case ARM::AK_ARMV8MBaseline: case ARM::ArchKind::ARMV8MBaseline:
case ARM::AK_ARMV8MMainline: case ARM::ArchKind::ARMV8MMainline:
setAttributeItem(THUMB_ISA_use, AllowThumbDerived, false); setAttributeItem(THUMB_ISA_use, AllowThumbDerived, false);
setAttributeItem(CPU_arch_profile, MicroControllerProfile, false); setAttributeItem(CPU_arch_profile, MicroControllerProfile, false);
break; break;
case ARM::AK_IWMMXT: case ARM::ArchKind::IWMMXT:
setAttributeItem(ARM_ISA_use, Allowed, false); setAttributeItem(ARM_ISA_use, Allowed, false);
setAttributeItem(THUMB_ISA_use, Allowed, false); setAttributeItem(THUMB_ISA_use, Allowed, false);
setAttributeItem(WMMX_arch, AllowWMMXv1, false); setAttributeItem(WMMX_arch, AllowWMMXv1, false);
break; break;
case ARM::AK_IWMMXT2: case ARM::ArchKind::IWMMXT2:
setAttributeItem(ARM_ISA_use, Allowed, false); setAttributeItem(ARM_ISA_use, Allowed, false);
setAttributeItem(THUMB_ISA_use, Allowed, false); setAttributeItem(THUMB_ISA_use, Allowed, false);
setAttributeItem(WMMX_arch, AllowWMMXv2, false); setAttributeItem(WMMX_arch, AllowWMMXv2, false);
break; break;
default: default:
report_fatal_error("Unknown Arch: " + Twine(Arch)); report_fatal_error("Unknown Arch: " + Twine(ARM::getArchName(Arch)));
break; break;
} }
} }
void ARMTargetELFStreamer::emitFPU(unsigned Value) { void ARMTargetELFStreamer::emitFPU(unsigned Value) {
FPU = Value; FPU = Value;
} }
▲ Show 20 Lines • Show All 161 Lines • ▼ Show 20 Linesvoid ARMTargetELFStreamer::finishAttributeSection() {
// | <section-tag> <size> <section-number>* 0 <attribute>* // | <section-tag> <size> <section-number>* 0 <attribute>*
// | <symbol-tag> <size> <symbol-number>* 0 <attribute>* // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
// ]+ // ]+
// ]* // ]*
if (FPU != ARM::FK_INVALID) if (FPU != ARM::FK_INVALID)
emitFPUDefaultAttributes(); emitFPUDefaultAttributes();
if (Arch != ARM::AK_INVALID) if (Arch != ARM::ArchKind::INVALID)
emitArchDefaultAttributes(); emitArchDefaultAttributes();
if (Contents.empty()) if (Contents.empty())
return; return;
std::sort(Contents.begin(), Contents.end(), AttributeItem::LessTag); std::sort(Contents.begin(), Contents.end(), AttributeItem::LessTag);
ARMELFStreamer &Streamer = getStreamer(); ARMELFStreamer &Streamer = getStreamer();
▲ Show 20 Lines • Show All 435 Lines • Show Last 20 Lines

lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

Show First 20 Lines • Show All 130 Lines • ▼ Show 20 Lines
#include "ARMGenSubtargetInfo.inc" #include "ARMGenSubtargetInfo.inc"
std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) { std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
bool isThumb = bool isThumb =
TT.getArch() == Triple::thumb || TT.getArch() == Triple::thumbeb; TT.getArch() == Triple::thumb || TT.getArch() == Triple::thumbeb;
std::string ARMArchFeature; std::string ARMArchFeature;
unsigned ArchID = ARM::parseArch(TT.getArchName()); ARM::ArchKind ArchID = ARM::parseArch(TT.getArchName());
if (ArchID != ARM::AK_INVALID && (CPU.empty() || CPU == "generic")) if (ArchID != ARM::ArchKind::INVALID && (CPU.empty() || CPU == "generic"))
ARMArchFeature = (ARMArchFeature + "+" + ARM::getArchName(ArchID)).str(); ARMArchFeature = (ARMArchFeature + "+" + ARM::getArchName(ArchID)).str();
if (isThumb) { if (isThumb) {
if (ARMArchFeature.empty()) if (ARMArchFeature.empty())
ARMArchFeature = "+thumb-mode"; ARMArchFeature = "+thumb-mode";
else else
ARMArchFeature += ",+thumb-mode"; ARMArchFeature += ",+thumb-mode";
} }
▲ Show 20 Lines • Show All 205 Lines • Show Last 20 Lines

lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp

Show First 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
} }
void ARMTargetStreamer::switchVendor(StringRef Vendor) {} void ARMTargetStreamer::switchVendor(StringRef Vendor) {}
void ARMTargetStreamer::emitAttribute(unsigned Attribute, unsigned Value) {} void ARMTargetStreamer::emitAttribute(unsigned Attribute, unsigned Value) {}
void ARMTargetStreamer::emitTextAttribute(unsigned Attribute, void ARMTargetStreamer::emitTextAttribute(unsigned Attribute,
StringRef String) {} StringRef String) {}
void ARMTargetStreamer::emitIntTextAttribute(unsigned Attribute, void ARMTargetStreamer::emitIntTextAttribute(unsigned Attribute,
unsigned IntValue, unsigned IntValue,
StringRef StringValue) {} StringRef StringValue) {}
void ARMTargetStreamer::emitArch(unsigned Arch) {} void ARMTargetStreamer::emitArch(ARM::ArchKind Arch) {}
void ARMTargetStreamer::emitArchExtension(unsigned ArchExt) {} void ARMTargetStreamer::emitArchExtension(unsigned ArchExt) {}
void ARMTargetStreamer::emitObjectArch(unsigned Arch) {} void ARMTargetStreamer::emitObjectArch(ARM::ArchKind Arch) {}
void ARMTargetStreamer::emitFPU(unsigned FPU) {} void ARMTargetStreamer::emitFPU(unsigned FPU) {}
void ARMTargetStreamer::finishAttributeSection() {} void ARMTargetStreamer::finishAttributeSection() {}
void ARMTargetStreamer::emitInst(uint32_t Inst, char Suffix) {} void ARMTargetStreamer::emitInst(uint32_t Inst, char Suffix) {}
void void
ARMTargetStreamer::AnnotateTLSDescriptorSequence(const MCSymbolRefExpr *SRE) {} ARMTargetStreamer::AnnotateTLSDescriptorSequence(const MCSymbolRefExpr *SRE) {}
void ARMTargetStreamer::emitThumbSet(MCSymbol *Symbol, const MCExpr *Value) {} void ARMTargetStreamer::emitThumbSet(MCSymbol *Symbol, const MCExpr *Value) {}
static ARMBuildAttrs::CPUArch getArchForCPU(const MCSubtargetInfo &STI) { static ARMBuildAttrs::CPUArch getArchForCPU(const MCSubtargetInfo &STI) {
▲ Show 20 Lines • Show All 174 Lines • Show Last 20 Lines

unittests/Support/TargetParserTest.cpp

Show All 26 Linesconst char *ARMArch[] = {
"armv7e-m", "armv7em", "armv8-a", "armv8", "armv8a", "armv7e-m", "armv7em", "armv8-a", "armv8", "armv8a",
"armv8.1-a", "armv8.1a", "armv8.2-a", "armv8.2a", "armv8-r", "armv8.1-a", "armv8.1a", "armv8.2-a", "armv8.2a", "armv8-r",
"armv8r", "armv8-m.base", "armv8m.base", "armv8-m.main", "armv8m.main", "armv8r", "armv8-m.base", "armv8m.base", "armv8-m.main", "armv8m.main",
"iwmmxt", "iwmmxt2", "xscale"}; "iwmmxt", "iwmmxt2", "xscale"};
bool testARMCPU(StringRef CPUName, StringRef ExpectedArch, bool testARMCPU(StringRef CPUName, StringRef ExpectedArch,
StringRef ExpectedFPU, unsigned ExpectedFlags, StringRef ExpectedFPU, unsigned ExpectedFlags,
StringRef CPUAttr) { StringRef CPUAttr) {
unsigned ArchKind = ARM::parseCPUArch(CPUName); ARM::ArchKind AK = ARM::parseCPUArch(CPUName);
bool pass = ARM::getArchName(ArchKind).equals(ExpectedArch); bool pass = ARM::getArchName(AK).equals(ExpectedArch);
unsigned FPUKind = ARM::getDefaultFPU(CPUName, ArchKind); unsigned FPUKind = ARM::getDefaultFPU(CPUName, AK);
pass &= ARM::getFPUName(FPUKind).equals(ExpectedFPU); pass &= ARM::getFPUName(FPUKind).equals(ExpectedFPU);
unsigned ExtKind = ARM::getDefaultExtensions(CPUName, ArchKind); unsigned ExtKind = ARM::getDefaultExtensions(CPUName, AK);
if (ExtKind > 1 && (ExtKind & ARM::AEK_NONE)) if (ExtKind > 1 && (ExtKind & ARM::AEK_NONE))
pass &= ((ExtKind ^ ARM::AEK_NONE) == ExpectedFlags); pass &= ((ExtKind ^ ARM::AEK_NONE) == ExpectedFlags);
else else
pass &= (ExtKind == ExpectedFlags); pass &= (ExtKind == ExpectedFlags);
pass &= ARM::getCPUAttr(ArchKind).equals(CPUAttr); pass &= ARM::getCPUAttr(AK).equals(CPUAttr);
return pass; return pass;
} }
TEST(TargetParserTest, testARMCPU) { TEST(TargetParserTest, testARMCPU) {
EXPECT_TRUE(testARMCPU("invalid", "invalid", "invalid", EXPECT_TRUE(testARMCPU("invalid", "invalid", "invalid",
ARM::AEK_NONE, "")); ARM::AEK_NONE, ""));
EXPECT_TRUE(testARMCPU("generic", "invalid", "none", EXPECT_TRUE(testARMCPU("generic", "invalid", "none",
▲ Show 20 Lines • Show All 208 Lines • ▼ Show 20 Lines EXPECT_TRUE(testARMCPU("xscale", "xscale", "none",
ARM::AEK_NONE, "xscale")); ARM::AEK_NONE, "xscale"));
EXPECT_TRUE(testARMCPU("swift", "armv7s", "neon-vfpv4", EXPECT_TRUE(testARMCPU("swift", "armv7s", "neon-vfpv4",
ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP, ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
"7-S")); "7-S"));
} }
bool testARMArch(StringRef Arch, StringRef DefaultCPU, StringRef SubArch, bool testARMArch(StringRef Arch, StringRef DefaultCPU, StringRef SubArch,
unsigned ArchAttr) { unsigned ArchAttr) {
unsigned ArchKind = ARM::parseArch(Arch); ARM::ArchKind AK = ARM::parseArch(Arch);
return (ArchKind != ARM::AK_INVALID) & return (AK!= ARM::ArchKind::INVALID) &
ARM::getDefaultCPU(Arch).equals(DefaultCPU) & ARM::getDefaultCPU(Arch).equals(DefaultCPU) &
ARM::getSubArch(ArchKind).equals(SubArch) & ARM::getSubArch(AK).equals(SubArch) &
(ARM::getArchAttr(ArchKind) == ArchAttr); (ARM::getArchAttr(AK) == ArchAttr);
} }
TEST(TargetParserTest, testARMArch) { TEST(TargetParserTest, testARMArch) {
EXPECT_TRUE( EXPECT_TRUE(
testARMArch("armv2", "arm2", "v2", testARMArch("armv2", "arm2", "v2",
ARMBuildAttrs::CPUArch::Pre_v4)); ARMBuildAttrs::CPUArch::Pre_v4));
EXPECT_TRUE( EXPECT_TRUE(
testARMArch("armv2a", "arm3", "v2a", testARMArch("armv2a", "arm3", "v2a",
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 LinesTEST(TargetParserTest, testARMArch) {
EXPECT_TRUE( EXPECT_TRUE(
testARMArch("armv7s", "swift", "v7s", testARMArch("armv7s", "swift", "v7s",
ARMBuildAttrs::CPUArch::v7)); ARMBuildAttrs::CPUArch::v7));
EXPECT_TRUE( EXPECT_TRUE(
testARMArch("armv7k", "generic", "v7k", testARMArch("armv7k", "generic", "v7k",
ARMBuildAttrs::CPUArch::v7)); ARMBuildAttrs::CPUArch::v7));
} }
bool testARMExtension(StringRef CPUName, unsigned ArchKind, StringRef ArchExt) { bool testARMExtension(StringRef CPUName,ARM::ArchKind ArchKind, StringRef ArchExt) {
return ARM::getDefaultExtensions(CPUName, ArchKind) & return ARM::getDefaultExtensions(CPUName, ArchKind) &
ARM::parseArchExt(ArchExt); ARM::parseArchExt(ArchExt);
} }
TEST(TargetParserTest, testARMExtension) { TEST(TargetParserTest, testARMExtension) {
EXPECT_FALSE(testARMExtension("arm2", 0, "thumb")); EXPECT_FALSE(testARMExtension("arm2", ARM::ArchKind::INVALID, "thumb"));
EXPECT_FALSE(testARMExtension("arm3", 0, "thumb")); EXPECT_FALSE(testARMExtension("arm3", ARM::ArchKind::INVALID, "thumb"));
EXPECT_FALSE(testARMExtension("arm6", 0, "thumb")); EXPECT_FALSE(testARMExtension("arm6", ARM::ArchKind::INVALID, "thumb"));
EXPECT_FALSE(testARMExtension("arm7m", 0, "thumb")); EXPECT_FALSE(testARMExtension("arm7m", ARM::ArchKind::INVALID, "thumb"));
EXPECT_FALSE(testARMExtension("strongarm", 0, "dsp")); EXPECT_FALSE(testARMExtension("strongarm", ARM::ArchKind::INVALID, "dsp"));
EXPECT_FALSE(testARMExtension("arm7tdmi", 0, "dsp")); EXPECT_FALSE(testARMExtension("arm7tdmi", ARM::ArchKind::INVALID, "dsp"));
EXPECT_FALSE(testARMExtension("arm10tdmi", 0, "simd")); EXPECT_FALSE(testARMExtension("arm10tdmi",
EXPECT_FALSE(testARMExtension("arm1022e", 0, "simd")); ARM::ArchKind::INVALID, "simd"));
EXPECT_FALSE(testARMExtension("arm926ej-s", 0, "simd")); EXPECT_FALSE(testARMExtension("arm1022e", ARM::ArchKind::INVALID, "simd"));
EXPECT_FALSE(testARMExtension("arm1136jf-s", 0, "crypto")); EXPECT_FALSE(testARMExtension("arm926ej-s",
EXPECT_FALSE(testARMExtension("arm1176j-s", 0, "crypto")); ARM::ArchKind::INVALID, "simd"));
EXPECT_FALSE(testARMExtension("arm1156t2-s", 0, "crypto")); EXPECT_FALSE(testARMExtension("arm1136jf-s",
EXPECT_FALSE(testARMExtension("arm1176jzf-s", 0, "crypto")); ARM::ArchKind::INVALID, "crypto"));
EXPECT_FALSE(testARMExtension("cortex-m0", 0, "crypto")); EXPECT_FALSE(testARMExtension("arm1176j-s",
EXPECT_FALSE(testARMExtension("cortex-a8", 0, "crypto")); ARM::ArchKind::INVALID, "crypto"));
EXPECT_FALSE(testARMExtension("cortex-r4", 0, "crypto")); EXPECT_FALSE(testARMExtension("arm1156t2-s",
EXPECT_FALSE(testARMExtension("cortex-m3", 0, "crypto")); ARM::ArchKind::INVALID, "crypto"));
EXPECT_FALSE(testARMExtension("cortex-a53", 0, "ras")); EXPECT_FALSE(testARMExtension("arm1176jzf-s",
EXPECT_FALSE(testARMExtension("cortex-r52", 0, "ras")); ARM::ArchKind::INVALID, "crypto"));
EXPECT_FALSE(testARMExtension("iwmmxt", 0, "crc")); EXPECT_FALSE(testARMExtension("cortex-m0",
EXPECT_FALSE(testARMExtension("xscale", 0, "crc")); ARM::ArchKind::INVALID, "crypto"));
EXPECT_FALSE(testARMExtension("swift", 0, "crc")); EXPECT_FALSE(testARMExtension("cortex-a8",
ARM::ArchKind::INVALID, "crypto"));
EXPECT_FALSE(testARMExtension("generic", ARM::AK_ARMV2, "thumb")); EXPECT_FALSE(testARMExtension("cortex-r4",
EXPECT_FALSE(testARMExtension("generic", ARM::AK_ARMV2A, "thumb")); ARM::ArchKind::INVALID, "crypto"));
EXPECT_FALSE(testARMExtension("generic", ARM::AK_ARMV3, "thumb")); EXPECT_FALSE(testARMExtension("cortex-m3",
EXPECT_FALSE(testARMExtension("generic", ARM::AK_ARMV3M, "thumb")); ARM::ArchKind::INVALID, "crypto"));
EXPECT_FALSE(testARMExtension("generic", ARM::AK_ARMV4, "dsp")); EXPECT_FALSE(testARMExtension("cortex-a53",
EXPECT_FALSE(testARMExtension("generic", ARM::AK_ARMV4T, "dsp")); ARM::ArchKind::INVALID, "ras"));
EXPECT_FALSE(testARMExtension("generic", ARM::AK_ARMV5T, "simd")); EXPECT_FALSE(testARMExtension("cortex-r52",
EXPECT_FALSE(testARMExtension("generic", ARM::AK_ARMV5TE, "simd")); ARM::ArchKind::INVALID, "ras"));
EXPECT_FALSE(testARMExtension("generic", ARM::AK_ARMV5TEJ, "simd")); EXPECT_FALSE(testARMExtension("iwmmxt", ARM::ArchKind::INVALID, "crc"));
EXPECT_FALSE(testARMExtension("generic", ARM::AK_ARMV6, "crypto")); EXPECT_FALSE(testARMExtension("xscale", ARM::ArchKind::INVALID, "crc"));
EXPECT_FALSE(testARMExtension("generic", ARM::AK_ARMV6K, "crypto")); EXPECT_FALSE(testARMExtension("swift", ARM::ArchKind::INVALID, "crc"));
EXPECT_FALSE(testARMExtension("generic", ARM::AK_ARMV6T2, "crypto"));
EXPECT_FALSE(testARMExtension("generic", ARM::AK_ARMV6KZ, "crypto")); EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV2, "thumb"));
EXPECT_FALSE(testARMExtension("generic", ARM::AK_ARMV6M, "crypto")); EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV2A, "thumb"));
EXPECT_FALSE(testARMExtension("generic", ARM::AK_ARMV7A, "crypto")); EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV3, "thumb"));
EXPECT_FALSE(testARMExtension("generic", ARM::AK_ARMV7R, "crypto")); EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV3M, "thumb"));
EXPECT_FALSE(testARMExtension("generic", ARM::AK_ARMV7M, "crypto")); EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV4, "dsp"));
EXPECT_FALSE(testARMExtension("generic", ARM::AK_ARMV7EM, "crypto")); EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV4T, "dsp"));
EXPECT_FALSE(testARMExtension("generic", ARM::AK_ARMV8A, "ras")); EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV5T, "simd"));
EXPECT_FALSE(testARMExtension("generic", ARM::AK_ARMV8_1A, "ras")); EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV5TE, "simd"));
EXPECT_FALSE(testARMExtension("generic", ARM::AK_ARMV8_2A, "spe")); EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV5TEJ, "simd"));
EXPECT_FALSE(testARMExtension("generic", ARM::AK_ARMV8R, "ras")); EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV6, "crypto"));
EXPECT_FALSE(testARMExtension("generic", ARM::AK_ARMV8MBaseline, "crc")); EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV6K, "crypto"));
EXPECT_FALSE(testARMExtension("generic", ARM::AK_ARMV8MMainline, "crc")); EXPECT_FALSE(testARMExtension("generic",
EXPECT_FALSE(testARMExtension("generic", ARM::AK_IWMMXT, "crc")); ARM::ArchKind::ARMV6T2, "crypto"));
EXPECT_FALSE(testARMExtension("generic", ARM::AK_IWMMXT2, "crc")); EXPECT_FALSE(testARMExtension("generic",
EXPECT_FALSE(testARMExtension("generic", ARM::AK_XSCALE, "crc")); ARM::ArchKind::ARMV6KZ, "crypto"));
EXPECT_FALSE(testARMExtension("generic", ARM::AK_ARMV7S, "crypto")); EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV6M, "crypto"));
EXPECT_FALSE(testARMExtension("generic", ARM::AK_ARMV7K, "crypto")); EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV7A, "crypto"));
EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV7R, "crypto"));
EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV7M, "crypto"));
EXPECT_FALSE(testARMExtension("generic",
ARM::ArchKind::ARMV7EM, "crypto"));
EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV8A, "ras"));
EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV8_1A, "ras"));
EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV8_2A, "spe"));
EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV8R, "ras"));
EXPECT_FALSE(testARMExtension("generic",
ARM::ArchKind::ARMV8MBaseline, "crc"));
EXPECT_FALSE(testARMExtension("generic",
ARM::ArchKind::ARMV8MMainline, "crc"));
EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::IWMMXT, "crc"));
EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::IWMMXT2, "crc"));
EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::XSCALE, "crc"));
EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV7S, "crypto"));
EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV7K, "crypto"));
} }
TEST(TargetParserTest, ARMFPUVersion) { TEST(TargetParserTest, ARMFPUVersion) {
for (ARM::FPUKind FK = static_cast<ARM::FPUKind>(0); for (ARM::FPUKind FK = static_cast<ARM::FPUKind>(0);
FK <= ARM::FPUKind::FK_LAST; FK <= ARM::FPUKind::FK_LAST;
FK = static_cast<ARM::FPUKind>(static_cast<unsigned>(FK) + 1)) FK = static_cast<ARM::FPUKind>(static_cast<unsigned>(FK) + 1))
if (FK == ARM::FK_LAST) if (FK == ARM::FK_LAST || ARM::getFPUName(FK) == "invalid" ||
rovkaUnsubmitted
Not Done
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Are the extra checks necessary?

rovka: Are the extra checks necessary?
fhahnAuthorUnsubmitted
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Unfortunately yes, but I am not sure if that test adds much value.

It seems like the previous test just checked if "0 <= ARM::getFPUVersion(FK)" for all FK holds. I think the intention was to check that it always returns an element in the enum, but wouldn't the condition be always true, because ARM::getFPUVersion(FK) used to return unsigned?

I think the tests in ARMFPUNeonSupportLevel and ARMFPURestriction have the same problem.

fhahn: Unfortunately yes, but I am not sure if that test adds much value. It seems like the previous…
rovkaUnsubmitted
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You're right, these tests were a bit iffy to begin with.

rovka: You're right, these tests were a bit iffy to begin with.
EXPECT_EQ(0U, ARM::getFPUVersion(FK)); ARM::getFPUName(FK) == "none" || ARM::getFPUName(FK) == "softvfp")
EXPECT_EQ(ARM::FPUVersion::NONE, ARM::getFPUVersion(FK));
else else
EXPECT_LE(0U, ARM::getFPUVersion(FK)); EXPECT_NE(ARM::FPUVersion::NONE, ARM::getFPUVersion(FK));
} }
TEST(TargetParserTest, ARMFPUNeonSupportLevel) { TEST(TargetParserTest, ARMFPUNeonSupportLevel) {
for (ARM::FPUKind FK = static_cast<ARM::FPUKind>(0); for (ARM::FPUKind FK = static_cast<ARM::FPUKind>(0);
FK <= ARM::FPUKind::FK_LAST; FK <= ARM::FPUKind::FK_LAST;
FK = static_cast<ARM::FPUKind>(static_cast<unsigned>(FK) + 1)) FK = static_cast<ARM::FPUKind>(static_cast<unsigned>(FK) + 1))
if (FK == ARM::FK_LAST) if (FK == ARM::FK_LAST ||
EXPECT_EQ(0U, ARM::getFPUNeonSupportLevel(FK)); ARM::getFPUName(FK).find("neon") == std::string::npos)
EXPECT_EQ(ARM::NeonSupportLevel::None,
ARM::getFPUNeonSupportLevel(FK));
else else
EXPECT_LE(0U, ARM::getFPUNeonSupportLevel(FK)); EXPECT_NE(ARM::NeonSupportLevel::None,
ARM::getFPUNeonSupportLevel(FK));
} }
TEST(TargetParserTest, ARMFPURestriction) { TEST(TargetParserTest, ARMFPURestriction) {
for (ARM::FPUKind FK = static_cast<ARM::FPUKind>(0); for (ARM::FPUKind FK = static_cast<ARM::FPUKind>(0);
FK <= ARM::FPUKind::FK_LAST; FK <= ARM::FPUKind::FK_LAST;
FK = static_cast<ARM::FPUKind>(static_cast<unsigned>(FK) + 1)) FK = static_cast<ARM::FPUKind>(static_cast<unsigned>(FK) + 1)) {
if (FK == ARM::FK_LAST) if (FK == ARM::FK_LAST ||
EXPECT_EQ(0U, ARM::getFPURestriction(FK)); (ARM::getFPUName(FK).find("d16") == std::string::npos &&
ARM::getFPUName(FK).find("vfpv3xd") == std::string::npos))
EXPECT_EQ(ARM::FPURestriction::None, ARM::getFPURestriction(FK));
else else
EXPECT_LE(0U, ARM::getFPURestriction(FK)); EXPECT_NE(ARM::FPURestriction::None, ARM::getFPURestriction(FK));
}
} }
TEST(TargetParserTest, ARMExtensionFeatures) { TEST(TargetParserTest, ARMExtensionFeatures) {
std::vector<StringRef> Features; std::vector<StringRef> Features;
unsigned Extensions = ARM::AEK_CRC | ARM::AEK_CRYPTO | ARM::AEK_DSP | unsigned Extensions = ARM::AEK_CRC | ARM::AEK_CRYPTO | ARM::AEK_DSP |
ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_MP | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_MP |
ARM::AEK_SEC | ARM::AEK_VIRT | ARM::AEK_RAS; ARM::AEK_SEC | ARM::AEK_VIRT | ARM::AEK_RAS;
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 LinesTEST(TargetParserTest, ARMparseArchEndianAndISA) {
for (unsigned i = 0; i < array_lengthof(Arch); i++) { for (unsigned i = 0; i < array_lengthof(Arch); i++) {
std::string arm_1 = "armeb" + (std::string)(Arch[i]); std::string arm_1 = "armeb" + (std::string)(Arch[i]);
std::string arm_2 = "arm" + (std::string)(Arch[i]) + "eb"; std::string arm_2 = "arm" + (std::string)(Arch[i]) + "eb";
std::string arm_3 = "arm" + (std::string)(Arch[i]); std::string arm_3 = "arm" + (std::string)(Arch[i]);
std::string thumb_1 = "thumbeb" + (std::string)(Arch[i]); std::string thumb_1 = "thumbeb" + (std::string)(Arch[i]);
std::string thumb_2 = "thumb" + (std::string)(Arch[i]) + "eb"; std::string thumb_2 = "thumb" + (std::string)(Arch[i]) + "eb";
std::string thumb_3 = "thumb" + (std::string)(Arch[i]); std::string thumb_3 = "thumb" + (std::string)(Arch[i]);
EXPECT_EQ(ARM::EK_BIG, ARM::parseArchEndian(arm_1)); EXPECT_EQ(ARM::EndianKind::BIG, ARM::parseArchEndian(arm_1));
EXPECT_EQ(ARM::EK_BIG, ARM::parseArchEndian(arm_2)); EXPECT_EQ(ARM::EndianKind::BIG, ARM::parseArchEndian(arm_2));
EXPECT_EQ(ARM::EK_LITTLE, ARM::parseArchEndian(arm_3)); EXPECT_EQ(ARM::EndianKind::LITTLE, ARM::parseArchEndian(arm_3));
EXPECT_EQ(ARM::IK_ARM, ARM::parseArchISA(arm_1)); EXPECT_EQ(ARM::ISAKind::ARM, ARM::parseArchISA(arm_1));
EXPECT_EQ(ARM::IK_ARM, ARM::parseArchISA(arm_2)); EXPECT_EQ(ARM::ISAKind::ARM, ARM::parseArchISA(arm_2));
EXPECT_EQ(ARM::IK_ARM, ARM::parseArchISA(arm_3)); EXPECT_EQ(ARM::ISAKind::ARM, ARM::parseArchISA(arm_3));
if (i >= 4) { if (i >= 4) {
EXPECT_EQ(ARM::EK_BIG, ARM::parseArchEndian(thumb_1)); EXPECT_EQ(ARM::EndianKind::BIG, ARM::parseArchEndian(thumb_1));
EXPECT_EQ(ARM::EK_BIG, ARM::parseArchEndian(thumb_2)); EXPECT_EQ(ARM::EndianKind::BIG, ARM::parseArchEndian(thumb_2));
EXPECT_EQ(ARM::EK_LITTLE, ARM::parseArchEndian(thumb_3)); EXPECT_EQ(ARM::EndianKind::LITTLE, ARM::parseArchEndian(thumb_3));
EXPECT_EQ(ARM::IK_THUMB, ARM::parseArchISA(thumb_1)); EXPECT_EQ(ARM::ISAKind::THUMB, ARM::parseArchISA(thumb_1));
EXPECT_EQ(ARM::IK_THUMB, ARM::parseArchISA(thumb_2)); EXPECT_EQ(ARM::ISAKind::THUMB, ARM::parseArchISA(thumb_2));
EXPECT_EQ(ARM::IK_THUMB, ARM::parseArchISA(thumb_3)); EXPECT_EQ(ARM::ISAKind::THUMB, ARM::parseArchISA(thumb_3));
} }
} }
EXPECT_EQ(ARM::EK_LITTLE, ARM::parseArchEndian("aarch64")); EXPECT_EQ(ARM::EndianKind::LITTLE, ARM::parseArchEndian("aarch64"));
EXPECT_EQ(ARM::EK_BIG, ARM::parseArchEndian("aarch64_be")); EXPECT_EQ(ARM::EndianKind::BIG, ARM::parseArchEndian("aarch64_be"));
EXPECT_EQ(ARM::IK_AARCH64, ARM::parseArchISA("aarch64")); EXPECT_EQ(ARM::ISAKind::AARCH64, ARM::parseArchISA("aarch64"));
EXPECT_EQ(ARM::IK_AARCH64, ARM::parseArchISA("aarch64_be")); EXPECT_EQ(ARM::ISAKind::AARCH64, ARM::parseArchISA("aarch64_be"));
EXPECT_EQ(ARM::IK_AARCH64, ARM::parseArchISA("arm64")); EXPECT_EQ(ARM::ISAKind::AARCH64, ARM::parseArchISA("arm64"));
EXPECT_EQ(ARM::IK_AARCH64, ARM::parseArchISA("arm64_be")); EXPECT_EQ(ARM::ISAKind::AARCH64, ARM::parseArchISA("arm64_be"));
} }
TEST(TargetParserTest, ARMparseArchProfile) { TEST(TargetParserTest, ARMparseArchProfile) {
for (unsigned i = 0; i < array_lengthof(ARMArch); i++) { for (unsigned i = 0; i < array_lengthof(ARMArch); i++) {
switch (ARM::parseArch(ARMArch[i])) { switch (ARM::parseArch(ARMArch[i])) {
case ARM::AK_ARMV6M: case ARM::ArchKind::ARMV6M:
case ARM::AK_ARMV7M: case ARM::ArchKind::ARMV7M:
case ARM::AK_ARMV7EM: case ARM::ArchKind::ARMV7EM:
case ARM::AK_ARMV8MMainline: case ARM::ArchKind::ARMV8MMainline:
case ARM::AK_ARMV8MBaseline: case ARM::ArchKind::ARMV8MBaseline:
EXPECT_EQ(ARM::PK_M, ARM::parseArchProfile(ARMArch[i])); EXPECT_EQ(ARM::ProfileKind::M, ARM::parseArchProfile(ARMArch[i]));
continue; break;
case ARM::AK_ARMV7R: case ARM::ArchKind::ARMV7R:
case ARM::AK_ARMV8R: case ARM::ArchKind::ARMV8R:
EXPECT_EQ(ARM::PK_R, ARM::parseArchProfile(ARMArch[i])); EXPECT_EQ(ARM::ProfileKind::R, ARM::parseArchProfile(ARMArch[i]));
continue; break;
case ARM::AK_ARMV7A: case ARM::ArchKind::ARMV7A:
case ARM::AK_ARMV7VE: case ARM::ArchKind::ARMV7VE:
case ARM::AK_ARMV7K: case ARM::ArchKind::ARMV7K:
case ARM::AK_ARMV8A: case ARM::ArchKind::ARMV8A:
case ARM::AK_ARMV8_1A: case ARM::ArchKind::ARMV8_1A:
case ARM::AK_ARMV8_2A: case ARM::ArchKind::ARMV8_2A:
EXPECT_EQ(ARM::PK_A, ARM::parseArchProfile(ARMArch[i])); EXPECT_EQ(ARM::ProfileKind::A, ARM::parseArchProfile(ARMArch[i]));
continue; break;
default:
EXPECT_EQ(ARM::ProfileKind::INVALID, ARM::parseArchProfile(ARMArch[i]));
break;
} }
EXPECT_EQ(ARM::PK_INVALID, ARM::parseArchProfile(ARMArch[i]));
} }
} }
TEST(TargetParserTest, ARMparseArchVersion) { TEST(TargetParserTest, ARMparseArchVersion) {
for (unsigned i = 0; i < array_lengthof(ARMArch); i++) for (unsigned i = 0; i < array_lengthof(ARMArch); i++)
if (((std::string)ARMArch[i]).substr(0, 4) == "armv") if (((std::string)ARMArch[i]).substr(0, 4) == "armv")
EXPECT_EQ((ARMArch[i][4] - 48u), ARM::parseArchVersion(ARMArch[i])); EXPECT_EQ((ARMArch[i][4] - 48u), ARM::parseArchVersion(ARMArch[i]));
else else
EXPECT_EQ(5u, ARM::parseArchVersion(ARMArch[i])); EXPECT_EQ(5u, ARM::parseArchVersion(ARMArch[i]));
} }
bool testAArch64CPU(StringRef CPUName, StringRef ExpectedArch, bool testAArch64CPU(StringRef CPUName, StringRef ExpectedArch,
StringRef ExpectedFPU, unsigned ExpectedFlags, StringRef ExpectedFPU, unsigned ExpectedFlags,
StringRef CPUAttr) { StringRef CPUAttr) {
unsigned ArchKind = AArch64::parseCPUArch(CPUName); AArch64::ArchKind AK = AArch64::parseCPUArch(CPUName);
bool pass = AArch64::getArchName(ArchKind).equals(ExpectedArch); bool pass = AArch64::getArchName(AK).equals(ExpectedArch);
unsigned FPUKind = AArch64::getDefaultFPU(CPUName, ArchKind); unsigned FPUKind = AArch64::getDefaultFPU(CPUName, AK);
pass &= AArch64::getFPUName(FPUKind).equals(ExpectedFPU); pass &= AArch64::getFPUName(FPUKind).equals(ExpectedFPU);
unsigned ExtKind = AArch64::getDefaultExtensions(CPUName, ArchKind); unsigned ExtKind = AArch64::getDefaultExtensions(CPUName, AK);
if (ExtKind > 1 && (ExtKind & AArch64::AEK_NONE)) if (ExtKind > 1 && (ExtKind & AArch64::AEK_NONE))
pass &= ((ExtKind ^ AArch64::AEK_NONE) == ExpectedFlags); pass &= ((ExtKind ^ AArch64::AEK_NONE) == ExpectedFlags);
else else
pass &= (ExtKind == ExpectedFlags); pass &= (ExtKind == ExpectedFlags);
pass &= AArch64::getCPUAttr(ArchKind).equals(CPUAttr); pass &= AArch64::getCPUAttr(AK).equals(CPUAttr);
return pass; return pass;
} }
TEST(TargetParserTest, testAArch64CPU) { TEST(TargetParserTest, testAArch64CPU) {
EXPECT_TRUE(testAArch64CPU( EXPECT_TRUE(testAArch64CPU(
"invalid", "invalid", "invalid", "invalid", "invalid", "invalid",
AArch64::AEK_NONE, "")); AArch64::AEK_NONE, ""));
▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Lines EXPECT_TRUE(testAArch64CPU(
"thunderxt88", "armv8-a", "crypto-neon-fp-armv8", "thunderxt88", "armv8-a", "crypto-neon-fp-armv8",
AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_SIMD | AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_SIMD |
AArch64::AEK_FP | AArch64::AEK_PROFILE, AArch64::AEK_FP | AArch64::AEK_PROFILE,
"8-A")); "8-A"));
} }
bool testAArch64Arch(StringRef Arch, StringRef DefaultCPU, StringRef SubArch, bool testAArch64Arch(StringRef Arch, StringRef DefaultCPU, StringRef SubArch,
unsigned ArchAttr) { unsigned ArchAttr) {
unsigned ArchKind = AArch64::parseArch(Arch); AArch64::ArchKind AK = AArch64::parseArch(Arch);
return (ArchKind != static_cast<unsigned>(AArch64::ArchKind::AK_INVALID)) & return (AK != AArch64::ArchKind::INVALID) &
AArch64::getDefaultCPU(Arch).equals(DefaultCPU) & AArch64::getDefaultCPU(Arch).equals(DefaultCPU) &
AArch64::getSubArch(ArchKind).equals(SubArch) & AArch64::getSubArch(AK).equals(SubArch) &
(AArch64::getArchAttr(ArchKind) == ArchAttr); (AArch64::getArchAttr(AK) == ArchAttr);
} }
TEST(TargetParserTest, testAArch64Arch) { TEST(TargetParserTest, testAArch64Arch) {
EXPECT_TRUE(testAArch64Arch("armv8-a", "cortex-a53", "v8", EXPECT_TRUE(testAArch64Arch("armv8-a", "cortex-a53", "v8",
ARMBuildAttrs::CPUArch::v8_A)); ARMBuildAttrs::CPUArch::v8_A));
EXPECT_TRUE(testAArch64Arch("armv8.1-a", "generic", "v8.1a", EXPECT_TRUE(testAArch64Arch("armv8.1-a", "generic", "v8.1a",
ARMBuildAttrs::CPUArch::v8_A)); ARMBuildAttrs::CPUArch::v8_A));
EXPECT_TRUE(testAArch64Arch("armv8.2-a", "generic", "v8.2a", EXPECT_TRUE(testAArch64Arch("armv8.2-a", "generic", "v8.2a",
ARMBuildAttrs::CPUArch::v8_A)); ARMBuildAttrs::CPUArch::v8_A));
} }
bool testAArch64Extension(StringRef CPUName, unsigned ArchKind, bool testAArch64Extension(StringRef CPUName, AArch64::ArchKind AK,
StringRef ArchExt) { StringRef ArchExt) {
return AArch64::getDefaultExtensions(CPUName, ArchKind) & return AArch64::getDefaultExtensions(CPUName, AK) &
AArch64::parseArchExt(ArchExt); AArch64::parseArchExt(ArchExt);
} }
TEST(TargetParserTest, testAArch64Extension) { TEST(TargetParserTest, testAArch64Extension) {
EXPECT_FALSE(testAArch64Extension("cortex-a35", 0, "ras")); EXPECT_FALSE(testAArch64Extension("cortex-a35",
EXPECT_FALSE(testAArch64Extension("cortex-a53", 0, "ras")); AArch64::ArchKind::INVALID, "ras"));
EXPECT_FALSE(testAArch64Extension("cortex-a57", 0, "ras")); EXPECT_FALSE(testAArch64Extension("cortex-a53",
EXPECT_FALSE(testAArch64Extension("cortex-a72", 0, "ras")); AArch64::ArchKind::INVALID, "ras"));
EXPECT_FALSE(testAArch64Extension("cortex-a73", 0, "ras")); EXPECT_FALSE(testAArch64Extension("cortex-a57",
EXPECT_FALSE(testAArch64Extension("cyclone", 0, "ras")); AArch64::ArchKind::INVALID, "ras"));
EXPECT_FALSE(testAArch64Extension("exynos-m1", 0, "ras")); EXPECT_FALSE(testAArch64Extension("cortex-a72",
EXPECT_FALSE(testAArch64Extension("kryo", 0, "ras")); AArch64::ArchKind::INVALID, "ras"));
EXPECT_FALSE(testAArch64Extension("thunderx2t99", 0, "ras")); EXPECT_FALSE(testAArch64Extension("cortex-a73",
EXPECT_FALSE(testAArch64Extension("thunderx", 0, "lse")); AArch64::ArchKind::INVALID, "ras"));
EXPECT_FALSE(testAArch64Extension("thunderxt81", 0, "lse")); EXPECT_FALSE(testAArch64Extension("cyclone",
EXPECT_FALSE(testAArch64Extension("thunderxt83", 0, "lse")); AArch64::ArchKind::INVALID, "ras"));
EXPECT_FALSE(testAArch64Extension("thunderxt88", 0, "lse")); EXPECT_FALSE(testAArch64Extension("exynos-m1",
AArch64::ArchKind::INVALID, "ras"));
EXPECT_FALSE(testAArch64Extension("kryo",
AArch64::ArchKind::INVALID, "ras"));
EXPECT_FALSE(testAArch64Extension("thunderx2t99",
AArch64::ArchKind::INVALID, "ras"));
EXPECT_FALSE(testAArch64Extension("thunderx",
AArch64::ArchKind::INVALID, "lse"));
EXPECT_FALSE(testAArch64Extension("thunderxt81",
AArch64::ArchKind::INVALID, "lse"));
EXPECT_FALSE(testAArch64Extension("thunderxt83",
AArch64::ArchKind::INVALID, "lse"));
EXPECT_FALSE(testAArch64Extension("thunderxt88",
AArch64::ArchKind::INVALID, "lse"));
EXPECT_FALSE(testAArch64Extension( EXPECT_FALSE(testAArch64Extension(
"generic", static_cast<unsigned>(AArch64::ArchKind::AK_ARMV8A), "ras")); "generic", AArch64::ArchKind::ARMV8A, "ras"));
EXPECT_FALSE(testAArch64Extension( EXPECT_FALSE(testAArch64Extension(
"generic", static_cast<unsigned>(AArch64::ArchKind::AK_ARMV8_1A), "ras")); "generic", AArch64::ArchKind::ARMV8_1A, "ras"));
EXPECT_FALSE(testAArch64Extension( EXPECT_FALSE(testAArch64Extension(
"generic", static_cast<unsigned>(AArch64::ArchKind::AK_ARMV8_2A), "spe")); "generic", AArch64::ArchKind::ARMV8_2A, "spe"));
} }
TEST(TargetParserTest, AArch64ExtensionFeatures) { TEST(TargetParserTest, AArch64ExtensionFeatures) {
std::vector<StringRef> Features; std::vector<StringRef> Features;
unsigned Extensions = AArch64::AEK_CRC | AArch64::AEK_CRYPTO | unsigned Extensions = AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
AArch64::AEK_FP | AArch64::AEK_SIMD | AArch64::AEK_FP | AArch64::AEK_SIMD |
AArch64::AEK_FP16 | AArch64::AEK_PROFILE | AArch64::AEK_FP16 | AArch64::AEK_PROFILE |
AArch64::AEK_RAS | AArch64::AEK_SVE; AArch64::AEK_RAS | AArch64::AEK_SVE;
for (unsigned i = 0; i <= Extensions; i++) for (unsigned i = 0; i <= Extensions; i++)
EXPECT_TRUE(i == 0 ? !AArch64::getExtensionFeatures(i, Features) EXPECT_TRUE(i == 0 ? !AArch64::getExtensionFeatures(i, Features)
: AArch64::getExtensionFeatures(i, Features)); : AArch64::getExtensionFeatures(i, Features));
} }
TEST(TargetParserTest, AArch64ArchFeatures) { TEST(TargetParserTest, AArch64ArchFeatures) {
std::vector<StringRef> Features; std::vector<StringRef> Features;
for (unsigned AK = 0; AK < static_cast<unsigned>(AArch64::ArchKind::AK_LAST); for (unsigned i = 0;
AK++) i <= static_cast<unsigned>(AArch64::ArchKind::ARMV8_2A);
rovkaUnsubmitted
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This kind of iteration was sort of ok when there was an AK_LAST, but I think with that gone there's the chance that this test won't get updated when someone adds something after ARMV8_2A.

One alternative would be to add the enum values to a vector (you can just #define AARCH64_ARCH(NAME, ID [...]) to push_back and include AArch64TargetParser.def) and iterate over the vector instead.

rovka: This kind of iteration was sort of ok when there was an AK_LAST, but I think with that gone…
fhahnAuthorUnsubmitted
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Agreed, thanks for the vector tip! :)

fhahn: Agreed, thanks for the vector tip! :)
rovkaUnsubmitted
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That's even nicer :)

rovka: That's even nicer :)
EXPECT_TRUE((AK == static_cast<unsigned>(AArch64::ArchKind::AK_INVALID) || i++) {
AK == static_cast<unsigned>(AArch64::ArchKind::AK_LAST)) AArch64::ArchKind AK = static_cast<AArch64::ArchKind>(i);
EXPECT_TRUE((AK == AArch64::ArchKind::INVALID)
? !AArch64::getArchFeatures(AK, Features) ? !AArch64::getArchFeatures(AK, Features)
: AArch64::getArchFeatures(AK, Features)); : AArch64::getArchFeatures(AK, Features));
} }
}
TEST(TargetParserTest, AArch64ArchExtFeature) { TEST(TargetParserTest, AArch64ArchExtFeature) {
const char *ArchExt[][4] = {{"crc", "nocrc", "+crc", "-crc"}, const char *ArchExt[][4] = {{"crc", "nocrc", "+crc", "-crc"},
{"crypto", "nocrypto", "+crypto", "-crypto"}, {"crypto", "nocrypto", "+crypto", "-crypto"},
{"fp", "nofp", "+fp-armv8", "-fp-armv8"}, {"fp", "nofp", "+fp-armv8", "-fp-armv8"},
{"simd", "nosimd", "+neon", "-neon"}, {"simd", "nosimd", "+neon", "-neon"},
{"fp16", "nofp16", "+fullfp16", "-fullfp16"}, {"fp16", "nofp16", "+fullfp16", "-fullfp16"},
{"profile", "noprofile", "+spe", "-spe"}, {"profile", "noprofile", "+spe", "-spe"},
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