Following the docs, we need at least 5 wait states between an EXEC write
and an instruction that uses DPP.
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Buildable 8328 Build 8328: arc lint + arc unit
Event Timeline
test/CodeGen/AMDGPU/inserted-wait-states.mir | ||
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495 | Should check the NOP argument is 0. Ideally these would be combined into one nop with the right value later. Also why not use VI-NEXT for all of them? |
test/CodeGen/AMDGPU/inserted-wait-states.mir | ||
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495 | Sure, I can check that it's 0. Btw, the rest of this file is inconsistent about whether it checks for a 0 argument or not. I didn't use VI-NEXT to be consistent with the rest of the file which doesn't either, but I can change that too. And yeah, all these NOP's are combined into one by a later pass; I don't remember exactly which one. |
- Check for correct S_NOP argument and use VI-NEXT
- Only check for VALU EXEC write as per the docs, and update test
Should check the NOP argument is 0. Ideally these would be combined into one nop with the right value later. Also why not use VI-NEXT for all of them?