[AMDGPU] Add missing hazard for DPP-after-EXEC-write

[cwabbott]

Summary

Following the docs, we need at least 5 wait states between an EXEC write
and an instruction that uses DPP.

[arsenm]

Needs test

[cwabbott]

Add a test for the problem as well as a missing test for DPP-after-VGPR-write.

[cwabbott]

Ping.

[arsenm]

test/CodeGen/AMDGPU/inserted-wait-states.mir

495 ↗

(On Diff #104793)

Should check the NOP argument is 0. Ideally these would be combined into one nop with the right value later. Also why not use VI-NEXT for all of them?

[cwabbott]

test/CodeGen/AMDGPU/inserted-wait-states.mir

495 ↗

(On Diff #104793)

Sure, I can check that it's 0. Btw, the rest of this file is inconsistent about whether it checks for a 0 argument or not. I didn't use VI-NEXT to be consistent with the rest of the file which doesn't either, but I can change that too.

And yeah, all these NOP's are combined into one by a later pass; I don't remember exactly which one.

[cwabbott]

• Check for correct S_NOP argument and use VI-NEXT
• Only check for VALU EXEC write as per the docs, and update test

[cwabbott]

Ping.

lib/Target/AMDGPU/GCNHazardRecognizer.cpp

for (const MachineOperand &Use : VMEM->uses()) {
     WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse);
   }
   return WaitStatesNeeded;
 }
 
 int GCNHazardRecognizer::checkDPPHazards(MachineInstr *DPP) {
   const SIRegisterInfo *TRI = ST.getRegisterInfo();
 
-  // Check for DPP VGPR read after VALU VGPR write.
+  // Check for DPP VGPR read after VALU VGPR write and EXEC write.
   int DppVgprWaitStates = 2;
+  int DppExecWaitStates = 5;
   int WaitStatesNeeded = 0;
 
   for (const MachineOperand &Use : DPP->uses()) {
     if (!Use.isReg() || !TRI->isVGPR(MF.getRegInfo(), Use.getReg()))
       continue;
     int WaitStatesNeededForUse =
         DppVgprWaitStates - getWaitStatesSinceDef(Use.getReg());
     WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse);
   }
 
+  WaitStatesNeeded =
+      std::max(WaitStatesNeeded,
+               DppExecWaitStates - getWaitStatesSinceDef(AMDGPU::EXEC));
+
   return WaitStatesNeeded;
 }
 
 int GCNHazardRecognizer::checkDivFMasHazards(MachineInstr *DivFMas) {
   const SIInstrInfo *TII = ST.getInstrInfo();
 
   // v_div_fmas requires 4 wait states after a write to vcc from a VALU
   // instruction.