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[AMDGPU] Add missing hazard for DPP-after-EXEC-write
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Authored by cwabbott on Jun 29 2017, 5:00 PM.

Details

Summary

Following the docs, we need at least 5 wait states between an EXEC write
and an instruction that uses DPP.

Diff Detail

Repository
rL LLVM

Event Timeline

cwabbott created this revision.Jun 29 2017, 5:00 PM
arsenm edited edge metadata.Jun 29 2017, 5:06 PM

Needs test

cwabbott updated this revision to Diff 104793.Jun 29 2017, 5:32 PM

Add a test for the problem as well as a missing test for DPP-after-VGPR-write.

arsenm added inline comments.Jul 10 2017, 3:14 PM
test/CodeGen/AMDGPU/inserted-wait-states.mir
495 ↗(On Diff #104793)

Should check the NOP argument is 0. Ideally these would be combined into one nop with the right value later. Also why not use VI-NEXT for all of them?

cwabbott added inline comments.Jul 17 2017, 6:18 PM
test/CodeGen/AMDGPU/inserted-wait-states.mir
495 ↗(On Diff #104793)

Sure, I can check that it's 0. Btw, the rest of this file is inconsistent about whether it checks for a 0 argument or not. I didn't use VI-NEXT to be consistent with the rest of the file which doesn't either, but I can change that too.

And yeah, all these NOP's are combined into one by a later pass; I don't remember exactly which one.

cwabbott updated this revision to Diff 107011.Jul 17 2017, 7:02 PM
  • Check for correct S_NOP argument and use VI-NEXT
  • Only check for VALU EXEC write as per the docs, and update test
tstellar accepted this revision.Aug 2 2017, 2:43 PM
This revision is now accepted and ready to land.Aug 2 2017, 2:43 PM
This revision was automatically updated to reflect the committed changes.