[llvm-objdump] Handle invalid instruction gracefully on ARM

[evgeny777]

Summary

I have several stripped ARM binaries, which can't be correctly disassembled by llvm-objdump, because they intermix code with data. For instance compiling and disassembling this file:

.text
  b l0
  .inst 0xffffffff
l0:

results in this output:

$a.0:
       0:	00 00 00 ea 	b	#0 <l0>
       4:	ff  <unknown>
       5:	ff ff ff 00 	ldrshteq	pc, [pc], #255

and after applying this patch the result is the same as GNU objdump has:

$a.0:
       0:	00 00 00 ea 	b	#0 <l0>
       4:	ff ff ff ff  <unknown>

This happens because ARMDisasembler returns zero size when it fails to parse an instruction. On the contrary AArch64Disassembler always returns 4, so aarch64 binaries are disassembled correctly.

[t.p.northover]

Looks fine to me. Next step, enable the crystal ball for Thumb!

lib/Target/ARM/Disassembler/ARMDisassembler.cpp

if (Result != MCDisassembler::Fail) {
       // Add a fake predicate operand, because we share these instruction
       // definitions with Thumb2 where these instructions are predicable.
       if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this))
         return MCDisassembler::Fail;
       return Result;
     }
   }
 
-  Size = 0;
+  Size = 4;
   return MCDisassembler::Fail;
 }
 
 namespace llvm {
 
 extern const MCInstrDesc ARMInsts[];
 
 } // end namespace llvm

test/tools/llvm-objdump/ARM/invalid-instruction.s

+@RUN: llvm-mc -triple arm-unknown-linux -filetype=obj %s | llvm-objdump -d - | FileCheck %s
+
+.text
+  b l0
+  .inst 0xffffffff
+l0:
+
+@CHECK:            0: 00 00 00 ea   b #0 <l0>
+@CHECK-NEXT:       4: ff ff ff ff  <unknown>