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Differential D34655

[AMDGPU] Add 2 new alignbit patterns
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Authored by rampitec on Jun 26 2017, 5:13 PM.

Details

Reviewers
arsenm
msearles
vpykhtin
Commits
rGe8bf6c962900: [AMDGPU] Add 2 new alignbit patterns
rL306449: [AMDGPU] Add 2 new alignbit patterns

Diff Detail

Repository
rL LLVM

Event Timeline

rampitec created this revision.Jun 26 2017, 5:13 PM
Herald added subscribers: t-tye, tpr, dstuttard and 4 others. · View Herald TranscriptJun 26 2017, 5:13 PM
arsenm added inline comments.Jun 26 2017, 5:16 PM
test/CodeGen/AMDGPU/alignbit-pat.ll
18 ↗(On Diff #104047)

Needs negative tests with different values for the constants etc.

Also tests where src1 is a VGPR vs. SGPR

rampitec added inline comments.Jun 26 2017, 5:20 PM
test/CodeGen/AMDGPU/alignbit-pat.ll
18 ↗(On Diff #104047)

I'm not sure what kind of negative test do you want to see here? Pattern is only valid in presence of "& 31", and then matches always.

arsenm added inline comments.Jun 26 2017, 5:29 PM
test/CodeGen/AMDGPU/alignbit-pat.ll
18 ↗(On Diff #104047)

I mean if it was 30 or some other non-31 constant

rampitec updated this revision to Diff 104055.Jun 26 2017, 5:39 PM
rampitec marked 3 inline comments as done.

Added more tests.

vpykhtin accepted this revision.Jun 27 2017, 3:13 AM

LGTM.

This revision is now accepted and ready to land.Jun 27 2017, 3:13 AM
Closed by commit rL306449: [AMDGPU] Add 2 new alignbit patterns (authored by rampitec). · Explain WhyJun 27 2017, 12:11 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AMDGPU/
9 lines
test/
CodeGen/
AMDGPU/
142 lines

Diff 104233

llvm/trunk/lib/Target/AMDGPU/SIInstructions.td

Show First 20 Lines • Show All 923 Lines • ▼ Show 20 Lines
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def : IMad24Pat<V_MAD_I32_I24>; def : IMad24Pat<V_MAD_I32_I24>;
def : UMad24Pat<V_MAD_U32_U24>; def : UMad24Pat<V_MAD_U32_U24>;
defm : BFIPatterns <V_BFI_B32, S_MOV_B32, SReg_64>; defm : BFIPatterns <V_BFI_B32, S_MOV_B32, SReg_64>;
def : ROTRPattern <V_ALIGNBIT_B32>; def : ROTRPattern <V_ALIGNBIT_B32>;
def : Pat<(i32 (trunc (srl i64:$src0, (and i32:$src1, (i32 31))))),
(V_ALIGNBIT_B32 (i32 (EXTRACT_SUBREG (i64 $src0), sub1)),
(i32 (EXTRACT_SUBREG (i64 $src0), sub0)), $src1)>;
def : Pat<(i32 (trunc (shl i64:$src0, (and i32:$src1, (i32 31))))),
(V_ALIGNBIT_B32 (i32 (EXTRACT_SUBREG (i64 $src0), sub1)),
(i32 (EXTRACT_SUBREG (i64 $src0), sub0)),
(S_SUB_I32 (i32 32), $src1))>;
/********** ====================== **********/ /********** ====================== **********/
/********** Indirect addressing **********/ /********** Indirect addressing **********/
/********** ====================== **********/ /********** ====================== **********/
multiclass SI_INDIRECT_Pattern <ValueType vt, ValueType eltvt, string VecSize> { multiclass SI_INDIRECT_Pattern <ValueType vt, ValueType eltvt, string VecSize> {
// Extract with offset // Extract with offset
def : Pat< def : Pat<
(eltvt (extractelt vt:$src, (MOVRELOffset i32:$idx, (i32 imm:$offset)))), (eltvt (extractelt vt:$src, (MOVRELOffset i32:$idx, (i32 imm:$offset)))),
▲ Show 20 Lines • Show All 360 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AMDGPU/alignbit-pat.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}alignbit_shr_pat:
; GCN-DAG: s_load_dword s[[SHR:[0-9]+]]
; GCN-DAG: load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
; GCN: v_alignbit_b32 v{{[0-9]+}}, v[[HI]], v[[LO]], s[[SHR]]
define amdgpu_kernel void @alignbit_shr_pat(i64 addrspace(1)* nocapture readonly %arg, i32 addrspace(1)* nocapture %arg1, i32 %arg2) {
bb:
%tmp = load i64, i64 addrspace(1)* %arg, align 8
%tmp3 = and i32 %arg2, 31
%tmp4 = zext i32 %tmp3 to i64
%tmp5 = lshr i64 %tmp, %tmp4
%tmp6 = trunc i64 %tmp5 to i32
store i32 %tmp6, i32 addrspace(1)* %arg1, align 4
ret void
}
; GCN-LABEL: {{^}}alignbit_shl_pat:
; GCN-DAG: s_load_dword s[[SHL:[0-9]+]]
; GCN-DAG: load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
; GCN-DAG: s_sub_i32 s[[SHR:[0-9]+]], 32, s[[SHL]]
; GCN: v_alignbit_b32 v{{[0-9]+}}, v[[HI]], v[[LO]], s[[SHR]]
define amdgpu_kernel void @alignbit_shl_pat(i64 addrspace(1)* nocapture readonly %arg, i32 addrspace(1)* nocapture %arg1, i32 %arg2) {
bb:
%tmp = load i64, i64 addrspace(1)* %arg, align 8
%tmp3 = and i32 %arg2, 31
%tmp4 = zext i32 %tmp3 to i64
%tmp5 = shl i64 %tmp, %tmp4
%tmp6 = trunc i64 %tmp5 to i32
store i32 %tmp6, i32 addrspace(1)* %arg1, align 4
ret void
}
; GCN-LABEL: {{^}}alignbit_shr_pat_v:
; GCN-DAG: load_dword v[[SHR:[0-9]+]],
; GCN-DAG: load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
; GCN: v_alignbit_b32 v{{[0-9]+}}, v[[HI]], v[[LO]], v[[SHR]]
define amdgpu_kernel void @alignbit_shr_pat_v(i64 addrspace(1)* nocapture readonly %arg, i32 addrspace(1)* nocapture %arg1) {
bb:
%tid = tail call i32 @llvm.amdgcn.workitem.id.x()
%gep1 = getelementptr inbounds i64, i64 addrspace(1)* %arg, i32 %tid
%tmp = load i64, i64 addrspace(1)* %gep1, align 8
%gep2 = getelementptr inbounds i32, i32 addrspace(1)* %arg1, i32 %tid
%amt = load i32, i32 addrspace(1)* %gep2, align 4
%tmp3 = and i32 %amt, 31
%tmp4 = zext i32 %tmp3 to i64
%tmp5 = lshr i64 %tmp, %tmp4
%tmp6 = trunc i64 %tmp5 to i32
store i32 %tmp6, i32 addrspace(1)* %gep2, align 4
ret void
}
; GCN-LABEL: {{^}}alignbit_shl_pat_v:
; GCN-DAG: load_dword v[[SHL:[0-9]+]],
; GCN-DAG: load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
; GCN-DAG: v_sub_i32_e32 v[[SHR:[0-9]+]], {{[^,]+}}, 32, v[[SHL]]
; GCN: v_alignbit_b32 v{{[0-9]+}}, v[[HI]], v[[LO]], v[[SHR]]
define amdgpu_kernel void @alignbit_shl_pat_v(i64 addrspace(1)* nocapture readonly %arg, i32 addrspace(1)* nocapture %arg1) {
bb:
%tid = tail call i32 @llvm.amdgcn.workitem.id.x()
%gep1 = getelementptr inbounds i64, i64 addrspace(1)* %arg, i32 %tid
%tmp = load i64, i64 addrspace(1)* %gep1, align 8
%gep2 = getelementptr inbounds i32, i32 addrspace(1)* %arg1, i32 %tid
%amt = load i32, i32 addrspace(1)* %gep2, align 4
%tmp3 = and i32 %amt, 31
%tmp4 = zext i32 %tmp3 to i64
%tmp5 = shl i64 %tmp, %tmp4
%tmp6 = trunc i64 %tmp5 to i32
store i32 %tmp6, i32 addrspace(1)* %gep2, align 4
ret void
}
; GCN-LABEL: {{^}}alignbit_shr_pat_wrong_and30:
; Negative test, wrong constant
; GCN: v_lshr_b64
; GCN-NOT: v_alignbit_b32
define amdgpu_kernel void @alignbit_shr_pat_wrong_and30(i64 addrspace(1)* nocapture readonly %arg, i32 addrspace(1)* nocapture %arg1, i32 %arg2) {
bb:
%tmp = load i64, i64 addrspace(1)* %arg, align 8
%tmp3 = and i32 %arg2, 30
%tmp4 = zext i32 %tmp3 to i64
%tmp5 = lshr i64 %tmp, %tmp4
%tmp6 = trunc i64 %tmp5 to i32
store i32 %tmp6, i32 addrspace(1)* %arg1, align 4
ret void
}
; GCN-LABEL: {{^}}alignbit_shl_pat_wrong_and30:
; Negative test, wrong constant
; GCN: v_lshl_b64
; GCN-NOT: v_alignbit_b32
define amdgpu_kernel void @alignbit_shl_pat_wrong_and30(i64 addrspace(1)* nocapture readonly %arg, i32 addrspace(1)* nocapture %arg1, i32 %arg2) {
bb:
%tmp = load i64, i64 addrspace(1)* %arg, align 8
%tmp3 = and i32 %arg2, 30
%tmp4 = zext i32 %tmp3 to i64
%tmp5 = shl i64 %tmp, %tmp4
%tmp6 = trunc i64 %tmp5 to i32
store i32 %tmp6, i32 addrspace(1)* %arg1, align 4
ret void
}
; GCN-LABEL: {{^}}alignbit_shr_pat_wrong_and63:
; Negative test, wrong constant
; GCN: v_lshr_b64
; GCN-NOT: v_alignbit_b32
define amdgpu_kernel void @alignbit_shr_pat_wrong_and63(i64 addrspace(1)* nocapture readonly %arg, i32 addrspace(1)* nocapture %arg1, i32 %arg2) {
bb:
%tmp = load i64, i64 addrspace(1)* %arg, align 8
%tmp3 = and i32 %arg2, 63
%tmp4 = zext i32 %tmp3 to i64
%tmp5 = lshr i64 %tmp, %tmp4
%tmp6 = trunc i64 %tmp5 to i32
store i32 %tmp6, i32 addrspace(1)* %arg1, align 4
ret void
}
; GCN-LABEL: {{^}}alignbit_shl_pat_wrong_and63:
; Negative test, wrong constant
; GCN: v_lshl_b64
; GCN-NOT: v_alignbit_b32
define amdgpu_kernel void @alignbit_shl_pat_wrong_and63(i64 addrspace(1)* nocapture readonly %arg, i32 addrspace(1)* nocapture %arg1, i32 %arg2) {
bb:
%tmp = load i64, i64 addrspace(1)* %arg, align 8
%tmp3 = and i32 %arg2, 63
%tmp4 = zext i32 %tmp3 to i64
%tmp5 = shl i64 %tmp, %tmp4
%tmp6 = trunc i64 %tmp5 to i32
store i32 %tmp6, i32 addrspace(1)* %arg1, align 4
ret void
}
declare i32 @llvm.amdgcn.workitem.id.x() #0
attributes #0 = { nounwind readnone speculatable }