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[GlobalISel][X86] Get correct RegClass for given RegBank.
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Authored by igorb on Jun 6 2017, 1:36 PM.

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Summary

In some cases RegClass depends on target feature. Hight (16-31) vector registers exist only if AVX512f available.
Split from https://reviews.llvm.org/D33665

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rL LLVM

Event Timeline

igorb created this revision.Jun 6 2017, 1:36 PM
t.p.northover accepted this revision.Jun 19 2017, 9:15 AM

This looks fine to me, but I'll understand if anyone wants someone more x86y to have a look too.

This revision is now accepted and ready to land.Jun 19 2017, 9:15 AM
This revision was automatically updated to reflect the committed changes.