[GlobalISel][X86] Get correct RegClass for given RegBank.

[igorb]

Summary

In some cases RegClass depends on target feature. Hight (16-31) vector registers exist only if AVX512f available.
Split from https://reviews.llvm.org/D33665

[t.p.northover]

This looks fine to me, but I'll understand if anyone wants someone more x86y to have a look too.

[guyblank]

LGTM

llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp

private:
   bool selectConstant(MachineInstr &I, MachineRegisterInfo &MRI,
                       MachineFunction &MF) const;
   bool selectTrunc(MachineInstr &I, MachineRegisterInfo &MRI,
                    MachineFunction &MF) const;
   bool selectZext(MachineInstr &I, MachineRegisterInfo &MRI,
                   MachineFunction &MF) const;
   bool selectCmp(MachineInstr &I, MachineRegisterInfo &MRI,
                  MachineFunction &MF) const;
-
   bool selectUadde(MachineInstr &I, MachineRegisterInfo &MRI,
                    MachineFunction &MF) const;
+  bool selectCopy(MachineInstr &I, MachineRegisterInfo &MRI) const;
+
+  const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank &RB) const;
+  const TargetRegisterClass *getRegClass(LLT Ty, unsigned Reg,
+                                         MachineRegisterInfo &MRI) const;
 
   const X86TargetMachine &TM;
   const X86Subtarget &STI;
   const X86InstrInfo &TII;
   const X86RegisterInfo &TRI;
   const X86RegisterBankInfo &RBI;
 
 #define GET_GLOBALISEL_PREDICATES_DECL

 #define GET_GLOBALISEL_TEMPORARIES_INIT
 #include "X86GenGlobalISel.inc"
 #undef GET_GLOBALISEL_TEMPORARIES_INIT
 {
 }
 
 // FIXME: This should be target-independent, inferred from the types declared
 // for each class in the bank.
-static const TargetRegisterClass *
-getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB) {
+const TargetRegisterClass *
+X86InstructionSelector::getRegClass(LLT Ty, const RegisterBank &RB) const {
   if (RB.getID() == X86::GPRRegBankID) {
     if (Ty.getSizeInBits() <= 8)
       return &X86::GR8RegClass;
     if (Ty.getSizeInBits() == 16)
       return &X86::GR16RegClass;
     if (Ty.getSizeInBits() == 32)
       return &X86::GR32RegClass;
     if (Ty.getSizeInBits() == 64)
       return &X86::GR64RegClass;
   }
   if (RB.getID() == X86::VECRRegBankID) {
     if (Ty.getSizeInBits() == 32)
-      return &X86::FR32XRegClass;
+      return STI.hasAVX512() ? &X86::FR32XRegClass : &X86::FR32RegClass;
     if (Ty.getSizeInBits() == 64)
-      return &X86::FR64XRegClass;
+      return STI.hasAVX512() ? &X86::FR64XRegClass : &X86::FR64RegClass;
     if (Ty.getSizeInBits() == 128)
-      return &X86::VR128XRegClass;
+      return STI.hasAVX512() ? &X86::VR128XRegClass : &X86::VR128RegClass;
     if (Ty.getSizeInBits() == 256)
-      return &X86::VR256XRegClass;
+      return STI.hasAVX512() ? &X86::VR256XRegClass : &X86::VR256RegClass;
     if (Ty.getSizeInBits() == 512)
       return &X86::VR512RegClass;
   }
 
   llvm_unreachable("Unknown RegBank!");
 }
 
+const TargetRegisterClass *
+X86InstructionSelector::getRegClass(LLT Ty, unsigned Reg,
+                                    MachineRegisterInfo &MRI) const {
+  const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI);
+  return getRegClass(Ty, RegBank);
+}
+
 // Set X86 Opcode and constrain DestReg.
-static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
-                       MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
-                       const RegisterBankInfo &RBI) {
+bool X86InstructionSelector::selectCopy(MachineInstr &I,
+                                        MachineRegisterInfo &MRI) const {
 
   unsigned DstReg = I.getOperand(0).getReg();
   if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
     assert(I.isCopy() && "Generic operators do not allow physical registers");
     return true;
   }
 
   const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI);
assert((DstSize == SrcSize ||
            DstSize <= RBI.getSizeInBits(SrcReg, MRI, TRI))) &&
          "Copy with different width?!");
 
   const TargetRegisterClass *RC = nullptr;
 
   switch (RegBank.getID()) {
   case X86::GPRRegBankID:
     assert((DstSize <= 64) && "GPRs cannot get more than 64-bit width values.");
-    RC = getRegClassForTypeOnBank(MRI.getType(DstReg), RegBank);
+    RC = getRegClass(MRI.getType(DstReg), RegBank);
 
     // Change the physical register
     if (SrcSize > DstSize && TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
       if (RC == &X86::GR32RegClass)
         I.getOperand(1).setSubReg(X86::sub_32bit);
       else if (RC == &X86::GR16RegClass)
         I.getOperand(1).setSubReg(X86::sub_16bit);
       else if (RC == &X86::GR8RegClass)
         I.getOperand(1).setSubReg(X86::sub_8bit);
 
       I.getOperand(1).substPhysReg(SrcReg, TRI);
     }
     break;
   case X86::VECRRegBankID:
-    RC = getRegClassForTypeOnBank(MRI.getType(DstReg), RegBank);
+    RC = getRegClass(MRI.getType(DstReg), RegBank);
     break;
   default:
     llvm_unreachable("Unknown RegBank!");
   }
 
   // No need to constrain SrcReg. It will get constrained when
   // we hit another of its use or its defs.
   // Copies do not have constraints.
bool X86InstructionSelector::select(MachineInstr &I) const {
   MachineFunction &MF = *MBB.getParent();
   MachineRegisterInfo &MRI = MF.getRegInfo();
 
   unsigned Opcode = I.getOpcode();
   if (!isPreISelGenericOpcode(Opcode)) {
     // Certain non-generic instructions also need some special handling.
 
     if (I.isCopy())
-      return selectCopy(I, TII, MRI, TRI, RBI);
+      return selectCopy(I, MRI);
 
     // TODO: handle more cases - LOAD_STACK_GUARD, PHI
     return true;
   }
 
   assert(I.getNumOperands() == I.getNumExplicitOperands() &&
          "Generic instruction has unexpected implicit operands\n");
 
bool X86InstructionSelector::selectTrunc(MachineInstr &I,
   if (DstRB.getID() != SrcRB.getID()) {
     DEBUG(dbgs() << "G_TRUNC input/output on different banks\n");
     return false;
   }
 
   if (DstRB.getID() != X86::GPRRegBankID)
     return false;
 
-  const TargetRegisterClass *DstRC = getRegClassForTypeOnBank(DstTy, DstRB);
+  const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB);
   if (!DstRC)
     return false;
 
-  const TargetRegisterClass *SrcRC = getRegClassForTypeOnBank(SrcTy, SrcRB);
+  const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB);
   if (!SrcRC)
     return false;
 
   unsigned SubIdx;
   if (DstRC == SrcRC) {
     // Nothing to be done
     SubIdx = X86::NoSubRegister;
   } else if (DstRC == &X86::GR32RegClass) {
if (SrcTy == LLT::scalar(1)) {
     if (DstTy == LLT::scalar(32))
       AndOpc = X86::AND32ri8;
     else if (DstTy == LLT::scalar(64))
       AndOpc = X86::AND64ri8;
     else
       return false;
 
     const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI);
-    unsigned DefReg =
-        MRI.createVirtualRegister(getRegClassForTypeOnBank(DstTy, RegBank));
+    unsigned DefReg = MRI.createVirtualRegister(getRegClass(DstTy, RegBank));
 
     BuildMI(*I.getParent(), I, I.getDebugLoc(),
             TII.get(TargetOpcode::SUBREG_TO_REG), DefReg)
         .addImm(0)
         .addReg(SrcReg)
         .addImm(X86::sub_8bit);
 
     MachineInstr &AndInst =

llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir

 
 ...
 ---
 # ALL-LABEL: name:            test_store_float
 name:            test_store_float
 alignment:       4
 legalized:       true
 regBankSelected: true
+# NO_AVX512F:       registers:
+# NO_AVX512F-NEXT:    - { id: 0, class: fr32, preferred-register: '' }
+# NO_AVX512F-NEXT:    - { id: 1, class: gr64, preferred-register: '' }
+# NO_AVX512F-NEXT:    - { id: 2, class: gr32, preferred-register: '' }
+#
+# AVX512ALL:        registers:
+# AVX512ALL-NEXT:     - { id: 0, class: fr32x, preferred-register: '' }
+# AVX512ALL-NEXT:     - { id: 1, class: gr64, preferred-register: '' }
+# AVX512ALL-NEXT:     - { id: 2, class: gr32, preferred-register: '' }
 registers:
-# ALL:   - { id: 0, class: fr32x, preferred-register: '' }
-# ALL:   - { id: 1, class: gr64, preferred-register: '' }
-# ALL:   - { id: 2, class: gr32, preferred-register: '' }
   - { id: 0, class: vecr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 # ALL:     %0 = COPY %xmm0
 # ALL:     %1 = COPY %rdi
 # ALL:     %2 = COPY %0
 # ALL:     MOV32mr %1, 1, _, 0, _, %2 :: (store 4 into %ir.p1)
 # ALL:     %rax = COPY %1

 
 ...
 ---
 # ALL-LABEL: name:            test_store_double
 name:            test_store_double
 alignment:       4
 legalized:       true
 regBankSelected: true
+# NO_AVX512F:       registers:
+# NO_AVX512F-NEXT:    - { id: 0, class: fr64, preferred-register: '' }
+# NO_AVX512F-NEXT:    - { id: 1, class: gr64, preferred-register: '' }
+# NO_AVX512F-NEXT:    - { id: 2, class: gr64, preferred-register: '' }
+#
+# AVX512ALL:        registers:
+# AVX512ALL-NEXT:     - { id: 0, class: fr64x, preferred-register: '' }
+# AVX512ALL-NEXT:     - { id: 1, class: gr64, preferred-register: '' }
+# AVX512ALL-NEXT:     - { id: 2, class: gr64, preferred-register: '' }
 registers:
-# ALL:   - { id: 0, class: fr64x, preferred-register: '' }
-# ALL:   - { id: 1, class: gr64, preferred-register: '' }
-# ALL:   - { id: 2, class: gr64, preferred-register: '' }
   - { id: 0, class: vecr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 # ALL:     %0 = COPY %xmm0
 # ALL:     %1 = COPY %rdi
 # ALL:     %2 = COPY %0
 # ALL:     MOV64mr %1, 1, _, 0, _, %2 :: (store 8 into %ir.p1)
 # ALL:     %rax = COPY %1