This is an archive of the discontinued LLVM Phabricator instance.

Differential D33553

[AMDGPU][MC][GFX9] Corrected encoding of flat_scratch* in SDWA opcodes
ClosedPublic

Authored by dp on May 25 2017, 9:18 AM.

Details

Reviewers
vpykhtin
artem.tamazov
SamWot
Commits
rG6a2431df0b4e: [AMDGPU][MC][GFX9] Corrected encoding of flat_scratch* for SDWA opcodes
rL304015: [AMDGPU][MC][GFX9] Corrected encoding of flat_scratch* for SDWA opcodes
Summary

See bug 33171: https://bugs.llvm.org/show_bug.cgi?id=33171

Diff Detail

Event Timeline

dp created this revision.May 25 2017, 9:18 AM
Herald added subscribers: t-tye, tpr, dstuttard and 5 others. · View Herald TranscriptMay 25 2017, 9:18 AM
SamWot accepted this revision.May 25 2017, 9:50 PM

LGTM
I think it's better if you submit this change. I will close my review (https://reviews.llvm.org/D33556).

This revision is now accepted and ready to land.May 25 2017, 9:50 PM
artem.tamazov accepted this revision.May 26 2017, 5:56 AM
Closed by commit rL304015: [AMDGPU][MC][GFX9] Corrected encoding of flat_scratch* for SDWA opcodes (authored by dpreobra). · Explain WhyMay 26 2017, 11:01 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
AMDGPU/
MCTargetDesc/
2 lines
test/
MC/
AMDGPU/
4 lines

Diff 100258

lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp

Show First 20 Lines • Show All 332 Lines • ▼ Show 20 LinesSIMCCodeEmitter::getSDWA9SrcEncoding(const MCInst &MI, unsigned OpNo,
const MCSubtargetInfo &STI) const { const MCSubtargetInfo &STI) const {
uint64_t RegEnc = 0; uint64_t RegEnc = 0;
const MCOperand &MO = MI.getOperand(OpNo); const MCOperand &MO = MI.getOperand(OpNo);
unsigned Reg = MO.getReg(); unsigned Reg = MO.getReg();
RegEnc |= MRI.getEncodingValue(Reg); RegEnc |= MRI.getEncodingValue(Reg);
RegEnc &= SDWA9_SRC_REG_MASK; RegEnc &= SDWA9_SRC_REG_MASK;
if (AMDGPU::isSGPR(Reg, &MRI)) { if (AMDGPU::isSGPR(AMDGPU::mc2PseudoReg(Reg), &MRI)) {
RegEnc |= SDWA9_SRC_SGPR_MASK; RegEnc |= SDWA9_SRC_SGPR_MASK;
} }
return RegEnc; return RegEnc;
} }
unsigned unsigned
SIMCCodeEmitter::getSDWA9VopcDstEncoding(const MCInst &MI, unsigned OpNo, SIMCCodeEmitter::getSDWA9VopcDstEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups, SmallVectorImpl<MCFixup> &Fixups,
▲ Show 20 Lines • Show All 50 Lines • Show Last 20 Lines

test/MC/AMDGPU/vop_sdwa.s

Show First 20 Lines • Show All 680 Lines • ▼ Show 20 Lines
// GFX9: v_cmp_eq_f32_sdwa vcc, v1, s22 src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x2c,0x84,0x7c,0x01,0x00,0x05,0x82] // GFX9: v_cmp_eq_f32_sdwa vcc, v1, s22 src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x2c,0x84,0x7c,0x01,0x00,0x05,0x82]
v_cmp_eq_f32_sdwa vcc, v1, s22 src0_sel:WORD_1 src1_sel:BYTE_2 v_cmp_eq_f32_sdwa vcc, v1, s22 src0_sel:WORD_1 src1_sel:BYTE_2
// NOSICI: error: // NOSICI: error:
// NOVI: error: // NOVI: error:
// NOGFX9: error: invalid operand (violates constant bus restrictions) // NOGFX9: error: invalid operand (violates constant bus restrictions)
v_cmp_eq_f32_sdwa vcc, exec, vcc src0_sel:WORD_1 src1_sel:BYTE_2 v_cmp_eq_f32_sdwa vcc, exec, vcc src0_sel:WORD_1 src1_sel:BYTE_2
// NOSICI: error:
// NOVI: error:
// GFX9: v_ceil_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x8a,0x0a,0x7e,0x66,0x06,0x86,0x06]
v_ceil_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// VOPC with arbitrary SGPR destination // VOPC with arbitrary SGPR destination
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// NOSICI: error: // NOSICI: error:
// NOVI: error: // NOVI: error:
// GFX9: v_cmp_eq_f32_sdwa s[2:3], v1, v2 src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x04,0x84,0x7c,0x01,0x82,0x05,0x02] // GFX9: v_cmp_eq_f32_sdwa s[2:3], v1, v2 src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x04,0x84,0x7c,0x01,0x82,0x05,0x02]
Show All 27 Lines
// NOVI: error: // NOVI: error:
// GFX9: v_add_f32_sdwa v0, v0, v0 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x00,0x00,0x02,0x00,0x46,0x05,0x02] // GFX9: v_add_f32_sdwa v0, v0, v0 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x00,0x00,0x02,0x00,0x46,0x05,0x02]
v_add_f32 v0, v0, v0 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 v_add_f32 v0, v0, v0 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
// NOSICI: error: // NOSICI: error:
// NOVI: error: // NOVI: error:
// GFX9: v_add_f32_sdwa v0, v0, v0 clamp div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x00,0x00,0x02,0x00,0xe6,0x05,0x02] // GFX9: v_add_f32_sdwa v0, v0, v0 clamp div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x00,0x00,0x02,0x00,0xe6,0x05,0x02]
v_add_f32 v0, v0, v0 clamp div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 v_add_f32 v0, v0, v0 clamp div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
No newline at end of file No newline at end of file