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Differential D33459

Allow armv{7,7s,7k,7m,7em} builds
ClosedPublic

Authored by jroelofs on May 23 2017, 2:02 PM.

Details

Reviewers
compnerd
t.p.northover

Diff Detail

Event Timeline

jroelofs created this revision.May 23 2017, 2:02 PM
Herald added subscribers: javed.absar, mgorny, rengolin, aemerson. · View Herald TranscriptMay 23 2017, 2:02 PM
jroelofs added a child revision: D33259: Don't defer to the GCC driver for linking arm-baremetal.May 23 2017, 2:24 PM
compnerd accepted this revision.May 23 2017, 5:26 PM

Modulo the IT block macros, LGTM.

cmake/builtin-config-ix.cmake
27

Probably should add armv7 as well.

lib/builtins/arm/aeabi_cdcmp.S
103

We have macros for the IT blocks, can you use those, please? Similar throughout.

This revision is now accepted and ready to land.May 23 2017, 5:26 PM
jroelofs updated this revision to Diff 100101.May 24 2017, 8:42 AM
jroelofs retitled this revision from Allow armv7m and armv7em builds to Allow armv{7,7s,7k,7m,7em} builds.

implement feedback

jroelofs closed this revision.May 24 2017, 8:53 AM

r303765

Revision Contents

PathSize
cmake/
2 lines
lib/
builtins/
arm/
11 lines
11 lines
1 line
1 line
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2 lines

Diff 100101

cmake/builtin-config-ix.cmake

Show All 18 Lines
int foo(int x, int y) { int foo(int x, int y) {
_Atomic int result = x * y; _Atomic int result = x * y;
return result; return result;
} }
") ")
set(ARM64 aarch64) set(ARM64 aarch64)
set(ARM32 arm armhf armv6m) set(ARM32 arm armhf armv6m armv7m armv7em armv7 armv7s armv7k)
compnerdUnsubmitted
Not Done
ReplyInline Actions

Probably should add armv7 as well.

compnerd: Probably should add `armv7` as well.
set(X86 i386 i686) set(X86 i386 i686)
set(X86_64 x86_64) set(X86_64 x86_64)
set(MIPS32 mips mipsel) set(MIPS32 mips mipsel)
set(MIPS64 mips64 mips64el) set(MIPS64 mips64 mips64el)
set(PPC64 powerpc64 powerpc64le) set(PPC64 powerpc64 powerpc64le)
set(WASM32 wasm32) set(WASM32 wasm32)
set(WASM64 wasm64) set(WASM64 wasm64)
▲ Show 20 Lines • Show All 143 Lines • Show Last 20 Lines

lib/builtins/arm/aeabi_cdcmp.S

Show First 20 Lines • Show All 42 Lines • ▼ Show 20 Lines1:
lsls r0, r0, #31 lsls r0, r0, #31
pop {r0-r3, pc} pop {r0-r3, pc}
#else #else
pop {r0-r3, lr} pop {r0-r3, lr}
// NaN has been ruled out, so __aeabi_cdcmple can't trap // NaN has been ruled out, so __aeabi_cdcmple can't trap
bne __aeabi_cdcmple bne __aeabi_cdcmple
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
mov ip, #APSR_C
msr APSR_nzcvq, ip
#else
msr CPSR_f, #APSR_C msr CPSR_f, #APSR_C
#endif
JMP(lr) JMP(lr)
#endif #endif
END_COMPILERRT_FUNCTION(__aeabi_cdcmpeq) END_COMPILERRT_FUNCTION(__aeabi_cdcmpeq)
// void __aeabi_cdcmple(double a, double b) { // void __aeabi_cdcmple(double a, double b) {
// if (__aeabi_dcmplt(a, b)) { // if (__aeabi_dcmplt(a, b)) {
// Z = 0; C = 0; // Z = 0; C = 0;
Show All 30 Lines1:
lsls r0, r0, #31 lsls r0, r0, #31
pop {r0-r3, pc} pop {r0-r3, pc}
2: 2:
// Z = 0, C = 1 // Z = 0, C = 1
movs r0, #0xF movs r0, #0xF
lsls r0, r0, #31 lsls r0, r0, #31
pop {r0-r3, pc} pop {r0-r3, pc}
#else #else
ITT(eq)
compnerdUnsubmitted
Not Done
ReplyInline Actions

We have macros for the IT blocks, can you use those, please? Similar throughout.

compnerd: We have macros for the IT blocks, can you use those, please? Similar throughout.
moveq ip, #0 moveq ip, #0
beq 1f beq 1f
ldm sp, {r0-r3} ldm sp, {r0-r3}
bl __aeabi_dcmpeq bl __aeabi_dcmpeq
cmp r0, #1 cmp r0, #1
ITE(eq)
moveq ip, #(APSR_C | APSR_Z) moveq ip, #(APSR_C | APSR_Z)
movne ip, #(APSR_C) movne ip, #(APSR_C)
1: 1:
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
msr APSR_nzcvq, ip
#else
msr CPSR_f, ip msr CPSR_f, ip
#endif
pop {r0-r3} pop {r0-r3}
POP_PC() POP_PC()
#endif #endif
END_COMPILERRT_FUNCTION(__aeabi_cdcmple) END_COMPILERRT_FUNCTION(__aeabi_cdcmple)
// int __aeabi_cdrcmple(double a, double b) { // int __aeabi_cdrcmple(double a, double b) {
// return __aeabi_cdcmple(b, a); // return __aeabi_cdcmple(b, a);
// } // }
Show All 19 Lines

lib/builtins/arm/aeabi_cfcmp.S

Show First 20 Lines • Show All 42 Lines • ▼ Show 20 Lines1:
lsls r0, r0, #31 lsls r0, r0, #31
pop {r0-r3, pc} pop {r0-r3, pc}
#else #else
pop {r0-r3, lr} pop {r0-r3, lr}
// NaN has been ruled out, so __aeabi_cfcmple can't trap // NaN has been ruled out, so __aeabi_cfcmple can't trap
bne __aeabi_cfcmple bne __aeabi_cfcmple
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
mov ip, #APSR_C
msr APSR_nzcvq, ip
#else
msr CPSR_f, #APSR_C msr CPSR_f, #APSR_C
#endif
JMP(lr) JMP(lr)
#endif #endif
END_COMPILERRT_FUNCTION(__aeabi_cfcmpeq) END_COMPILERRT_FUNCTION(__aeabi_cfcmpeq)
// void __aeabi_cfcmple(float a, float b) { // void __aeabi_cfcmple(float a, float b) {
// if (__aeabi_fcmplt(a, b)) { // if (__aeabi_fcmplt(a, b)) {
// Z = 0; C = 0; // Z = 0; C = 0;
Show All 30 Lines1:
lsls r0, r0, #31 lsls r0, r0, #31
pop {r0-r3, pc} pop {r0-r3, pc}
2: 2:
// Z = 0, C = 1 // Z = 0, C = 1
movs r0, #0xF movs r0, #0xF
lsls r0, r0, #31 lsls r0, r0, #31
pop {r0-r3, pc} pop {r0-r3, pc}
#else #else
ITT(eq)
moveq ip, #0 moveq ip, #0
beq 1f beq 1f
ldm sp, {r0-r3} ldm sp, {r0-r3}
bl __aeabi_fcmpeq bl __aeabi_fcmpeq
cmp r0, #1 cmp r0, #1
ITE(eq)
moveq ip, #(APSR_C | APSR_Z) moveq ip, #(APSR_C | APSR_Z)
movne ip, #(APSR_C) movne ip, #(APSR_C)
1: 1:
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
msr APSR_nzcvq, ip
#else
msr CPSR_f, ip msr CPSR_f, ip
#endif
pop {r0-r3} pop {r0-r3}
POP_PC() POP_PC()
#endif #endif
END_COMPILERRT_FUNCTION(__aeabi_cfcmple) END_COMPILERRT_FUNCTION(__aeabi_cfcmple)
// int __aeabi_cfrcmple(float a, float b) { // int __aeabi_cfrcmple(float a, float b) {
// return __aeabi_cfcmple(b, a); // return __aeabi_cfcmple(b, a);
// } // }
Show All 14 Lines

lib/builtins/arm/eqdf2vfp.S

Show All 21 Lines
#if defined(COMPILER_RT_ARMHF_TARGET) #if defined(COMPILER_RT_ARMHF_TARGET)
vcmp.f64 d0, d1 vcmp.f64 d0, d1
#else #else
vmov d6, r0, r1 // load r0/r1 pair in double register vmov d6, r0, r1 // load r0/r1 pair in double register
vmov d7, r2, r3 // load r2/r3 pair in double register vmov d7, r2, r3 // load r2/r3 pair in double register
vcmp.f64 d6, d7 vcmp.f64 d6, d7
#endif #endif
vmrs apsr_nzcv, fpscr vmrs apsr_nzcv, fpscr
ITE(eq)
moveq r0, #1 // set result register to 1 if equal moveq r0, #1 // set result register to 1 if equal
movne r0, #0 movne r0, #0
bx lr bx lr
END_COMPILERRT_FUNCTION(__eqdf2vfp) END_COMPILERRT_FUNCTION(__eqdf2vfp)
NO_EXEC_STACK_DIRECTIVE NO_EXEC_STACK_DIRECTIVE

lib/builtins/arm/eqsf2vfp.S

Show All 21 Lines
#if defined(COMPILER_RT_ARMHF_TARGET) #if defined(COMPILER_RT_ARMHF_TARGET)
vcmp.f32 s0, s1 vcmp.f32 s0, s1
#else #else
vmov s14, r0 // move from GPR 0 to float register vmov s14, r0 // move from GPR 0 to float register
vmov s15, r1 // move from GPR 1 to float register vmov s15, r1 // move from GPR 1 to float register
vcmp.f32 s14, s15 vcmp.f32 s14, s15
#endif #endif
vmrs apsr_nzcv, fpscr vmrs apsr_nzcv, fpscr
ITE(eq)
moveq r0, #1 // set result register to 1 if equal moveq r0, #1 // set result register to 1 if equal
movne r0, #0 movne r0, #0
bx lr bx lr
END_COMPILERRT_FUNCTION(__eqsf2vfp) END_COMPILERRT_FUNCTION(__eqsf2vfp)
NO_EXEC_STACK_DIRECTIVE NO_EXEC_STACK_DIRECTIVE

lib/builtins/arm/gedf2vfp.S

Show All 21 Lines
#if defined(COMPILER_RT_ARMHF_TARGET) #if defined(COMPILER_RT_ARMHF_TARGET)
vcmp.f64 d0, d1 vcmp.f64 d0, d1
#else #else
vmov d6, r0, r1 // load r0/r1 pair in double register vmov d6, r0, r1 // load r0/r1 pair in double register
vmov d7, r2, r3 // load r2/r3 pair in double register vmov d7, r2, r3 // load r2/r3 pair in double register
vcmp.f64 d6, d7 vcmp.f64 d6, d7
#endif #endif
vmrs apsr_nzcv, fpscr vmrs apsr_nzcv, fpscr
ITE(ge)
movge r0, #1 // set result register to 1 if greater than or equal movge r0, #1 // set result register to 1 if greater than or equal
movlt r0, #0 movlt r0, #0
bx lr bx lr
END_COMPILERRT_FUNCTION(__gedf2vfp) END_COMPILERRT_FUNCTION(__gedf2vfp)
NO_EXEC_STACK_DIRECTIVE NO_EXEC_STACK_DIRECTIVE

lib/builtins/arm/gesf2vfp.S

Show All 21 Lines
#if defined(COMPILER_RT_ARMHF_TARGET) #if defined(COMPILER_RT_ARMHF_TARGET)
vcmp.f32 s0, s1 vcmp.f32 s0, s1
#else #else
vmov s14, r0 // move from GPR 0 to float register vmov s14, r0 // move from GPR 0 to float register
vmov s15, r1 // move from GPR 1 to float register vmov s15, r1 // move from GPR 1 to float register
vcmp.f32 s14, s15 vcmp.f32 s14, s15
#endif #endif
vmrs apsr_nzcv, fpscr vmrs apsr_nzcv, fpscr
ITE(ge)
movge r0, #1 // set result register to 1 if greater than or equal movge r0, #1 // set result register to 1 if greater than or equal
movlt r0, #0 movlt r0, #0
bx lr bx lr
END_COMPILERRT_FUNCTION(__gesf2vfp) END_COMPILERRT_FUNCTION(__gesf2vfp)
NO_EXEC_STACK_DIRECTIVE NO_EXEC_STACK_DIRECTIVE

lib/builtins/arm/gtdf2vfp.S

Show All 21 Lines
#if defined(COMPILER_RT_ARMHF_TARGET) #if defined(COMPILER_RT_ARMHF_TARGET)
vcmp.f64 d0, d1 vcmp.f64 d0, d1
#else #else
vmov d6, r0, r1 // load r0/r1 pair in double register vmov d6, r0, r1 // load r0/r1 pair in double register
vmov d7, r2, r3 // load r2/r3 pair in double register vmov d7, r2, r3 // load r2/r3 pair in double register
vcmp.f64 d6, d7 vcmp.f64 d6, d7
#endif #endif
vmrs apsr_nzcv, fpscr vmrs apsr_nzcv, fpscr
ITE(gt)
movgt r0, #1 // set result register to 1 if equal movgt r0, #1 // set result register to 1 if equal
movle r0, #0 movle r0, #0
bx lr bx lr
END_COMPILERRT_FUNCTION(__gtdf2vfp) END_COMPILERRT_FUNCTION(__gtdf2vfp)
NO_EXEC_STACK_DIRECTIVE NO_EXEC_STACK_DIRECTIVE

lib/builtins/arm/gtsf2vfp.S

Show All 21 Lines
#if defined(COMPILER_RT_ARMHF_TARGET) #if defined(COMPILER_RT_ARMHF_TARGET)
vcmp.f32 s0, s1 vcmp.f32 s0, s1
#else #else
vmov s14, r0 // move from GPR 0 to float register vmov s14, r0 // move from GPR 0 to float register
vmov s15, r1 // move from GPR 1 to float register vmov s15, r1 // move from GPR 1 to float register
vcmp.f32 s14, s15 vcmp.f32 s14, s15
#endif #endif
vmrs apsr_nzcv, fpscr vmrs apsr_nzcv, fpscr
ITE(gt)
movgt r0, #1 // set result register to 1 if equal movgt r0, #1 // set result register to 1 if equal
movle r0, #0 movle r0, #0
bx lr bx lr
END_COMPILERRT_FUNCTION(__gtsf2vfp) END_COMPILERRT_FUNCTION(__gtsf2vfp)
NO_EXEC_STACK_DIRECTIVE NO_EXEC_STACK_DIRECTIVE

lib/builtins/arm/ledf2vfp.S

Show All 21 Lines
#if defined(COMPILER_RT_ARMHF_TARGET) #if defined(COMPILER_RT_ARMHF_TARGET)
vcmp.f64 d0, d1 vcmp.f64 d0, d1
#else #else
vmov d6, r0, r1 // load r0/r1 pair in double register vmov d6, r0, r1 // load r0/r1 pair in double register
vmov d7, r2, r3 // load r2/r3 pair in double register vmov d7, r2, r3 // load r2/r3 pair in double register
vcmp.f64 d6, d7 vcmp.f64 d6, d7
#endif #endif
vmrs apsr_nzcv, fpscr vmrs apsr_nzcv, fpscr
ITE(ls)
movls r0, #1 // set result register to 1 if equal movls r0, #1 // set result register to 1 if equal
movhi r0, #0 movhi r0, #0
bx lr bx lr
END_COMPILERRT_FUNCTION(__ledf2vfp) END_COMPILERRT_FUNCTION(__ledf2vfp)
NO_EXEC_STACK_DIRECTIVE NO_EXEC_STACK_DIRECTIVE

lib/builtins/arm/lesf2vfp.S

Show All 21 Lines
#if defined(COMPILER_RT_ARMHF_TARGET) #if defined(COMPILER_RT_ARMHF_TARGET)
vcmp.f32 s0, s1 vcmp.f32 s0, s1
#else #else
vmov s14, r0 // move from GPR 0 to float register vmov s14, r0 // move from GPR 0 to float register
vmov s15, r1 // move from GPR 1 to float register vmov s15, r1 // move from GPR 1 to float register
vcmp.f32 s14, s15 vcmp.f32 s14, s15
#endif #endif
vmrs apsr_nzcv, fpscr vmrs apsr_nzcv, fpscr
ITE(ls)
movls r0, #1 // set result register to 1 if equal movls r0, #1 // set result register to 1 if equal
movhi r0, #0 movhi r0, #0
bx lr bx lr
END_COMPILERRT_FUNCTION(__lesf2vfp) END_COMPILERRT_FUNCTION(__lesf2vfp)
NO_EXEC_STACK_DIRECTIVE NO_EXEC_STACK_DIRECTIVE

lib/builtins/arm/ltdf2vfp.S

Show All 21 Lines
#if defined(COMPILER_RT_ARMHF_TARGET) #if defined(COMPILER_RT_ARMHF_TARGET)
vcmp.f64 d0, d1 vcmp.f64 d0, d1
#else #else
vmov d6, r0, r1 // load r0/r1 pair in double register vmov d6, r0, r1 // load r0/r1 pair in double register
vmov d7, r2, r3 // load r2/r3 pair in double register vmov d7, r2, r3 // load r2/r3 pair in double register
vcmp.f64 d6, d7 vcmp.f64 d6, d7
#endif #endif
vmrs apsr_nzcv, fpscr vmrs apsr_nzcv, fpscr
ITE(mi)
movmi r0, #1 // set result register to 1 if equal movmi r0, #1 // set result register to 1 if equal
movpl r0, #0 movpl r0, #0
bx lr bx lr
END_COMPILERRT_FUNCTION(__ltdf2vfp) END_COMPILERRT_FUNCTION(__ltdf2vfp)
NO_EXEC_STACK_DIRECTIVE NO_EXEC_STACK_DIRECTIVE

lib/builtins/arm/ltsf2vfp.S

Show All 21 Lines
#if defined(COMPILER_RT_ARMHF_TARGET) #if defined(COMPILER_RT_ARMHF_TARGET)
vcmp.f32 s0, s1 vcmp.f32 s0, s1
#else #else
vmov s14, r0 // move from GPR 0 to float register vmov s14, r0 // move from GPR 0 to float register
vmov s15, r1 // move from GPR 1 to float register vmov s15, r1 // move from GPR 1 to float register
vcmp.f32 s14, s15 vcmp.f32 s14, s15
#endif #endif
vmrs apsr_nzcv, fpscr vmrs apsr_nzcv, fpscr
ITE(mi)
movmi r0, #1 // set result register to 1 if equal movmi r0, #1 // set result register to 1 if equal
movpl r0, #0 movpl r0, #0
bx lr bx lr
END_COMPILERRT_FUNCTION(__ltsf2vfp) END_COMPILERRT_FUNCTION(__ltsf2vfp)
NO_EXEC_STACK_DIRECTIVE NO_EXEC_STACK_DIRECTIVE

lib/builtins/arm/nedf2vfp.S

Show All 21 Lines
#if defined(COMPILER_RT_ARMHF_TARGET) #if defined(COMPILER_RT_ARMHF_TARGET)
vcmp.f64 d0, d1 vcmp.f64 d0, d1
#else #else
vmov d6, r0, r1 // load r0/r1 pair in double register vmov d6, r0, r1 // load r0/r1 pair in double register
vmov d7, r2, r3 // load r2/r3 pair in double register vmov d7, r2, r3 // load r2/r3 pair in double register
vcmp.f64 d6, d7 vcmp.f64 d6, d7
#endif #endif
vmrs apsr_nzcv, fpscr vmrs apsr_nzcv, fpscr
ITE(ne)
movne r0, #1 // set result register to 0 if unequal movne r0, #1 // set result register to 0 if unequal
moveq r0, #0 moveq r0, #0
bx lr bx lr
END_COMPILERRT_FUNCTION(__nedf2vfp) END_COMPILERRT_FUNCTION(__nedf2vfp)
NO_EXEC_STACK_DIRECTIVE NO_EXEC_STACK_DIRECTIVE

lib/builtins/arm/nesf2vfp.S

Show All 21 Lines
#if defined(COMPILER_RT_ARMHF_TARGET) #if defined(COMPILER_RT_ARMHF_TARGET)
vcmp.f32 s0, s1 vcmp.f32 s0, s1
#else #else
vmov s14, r0 // move from GPR 0 to float register vmov s14, r0 // move from GPR 0 to float register
vmov s15, r1 // move from GPR 1 to float register vmov s15, r1 // move from GPR 1 to float register
vcmp.f32 s14, s15 vcmp.f32 s14, s15
#endif #endif
vmrs apsr_nzcv, fpscr vmrs apsr_nzcv, fpscr
ITE(ne)
movne r0, #1 // set result register to 1 if unequal movne r0, #1 // set result register to 1 if unequal
moveq r0, #0 moveq r0, #0
bx lr bx lr
END_COMPILERRT_FUNCTION(__nesf2vfp) END_COMPILERRT_FUNCTION(__nesf2vfp)
NO_EXEC_STACK_DIRECTIVE NO_EXEC_STACK_DIRECTIVE

lib/builtins/arm/unorddf2vfp.S

Show All 21 Lines
#if defined(COMPILER_RT_ARMHF_TARGET) #if defined(COMPILER_RT_ARMHF_TARGET)
vcmp.f64 d0, d1 vcmp.f64 d0, d1
#else #else
vmov d6, r0, r1 // load r0/r1 pair in double register vmov d6, r0, r1 // load r0/r1 pair in double register
vmov d7, r2, r3 // load r2/r3 pair in double register vmov d7, r2, r3 // load r2/r3 pair in double register
vcmp.f64 d6, d7 vcmp.f64 d6, d7
#endif #endif
vmrs apsr_nzcv, fpscr vmrs apsr_nzcv, fpscr
ITE(vs)
movvs r0, #1 // set result register to 1 if "overflow" (any NaNs) movvs r0, #1 // set result register to 1 if "overflow" (any NaNs)
movvc r0, #0 movvc r0, #0
bx lr bx lr
END_COMPILERRT_FUNCTION(__unorddf2vfp) END_COMPILERRT_FUNCTION(__unorddf2vfp)
NO_EXEC_STACK_DIRECTIVE NO_EXEC_STACK_DIRECTIVE

lib/builtins/arm/unordsf2vfp.S

Show All 21 Lines
#if defined(COMPILER_RT_ARMHF_TARGET) #if defined(COMPILER_RT_ARMHF_TARGET)
vcmp.f32 s0, s1 vcmp.f32 s0, s1
#else #else
vmov s14, r0 // move from GPR 0 to float register vmov s14, r0 // move from GPR 0 to float register
vmov s15, r1 // move from GPR 1 to float register vmov s15, r1 // move from GPR 1 to float register
vcmp.f32 s14, s15 vcmp.f32 s14, s15
#endif #endif
vmrs apsr_nzcv, fpscr vmrs apsr_nzcv, fpscr
ITE(vs)
movvs r0, #1 // set result register to 1 if "overflow" (any NaNs) movvs r0, #1 // set result register to 1 if "overflow" (any NaNs)
movvc r0, #0 movvc r0, #0
bx lr bx lr
END_COMPILERRT_FUNCTION(__unordsf2vfp) END_COMPILERRT_FUNCTION(__unordsf2vfp)
NO_EXEC_STACK_DIRECTIVE NO_EXEC_STACK_DIRECTIVE

lib/builtins/assembly.h

Show First 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
#define POP_PC() \ #define POP_PC() \
pop {ip}; \ pop {ip}; \
JMP(ip) JMP(ip)
#endif #endif
#if __ARM_ARCH_ISA_THUMB == 2 #if __ARM_ARCH_ISA_THUMB == 2
#define IT(cond) it cond #define IT(cond) it cond
#define ITT(cond) itt cond #define ITT(cond) itt cond
#define ITE(cond) ite cond
#else #else
#define IT(cond) #define IT(cond)
#define ITT(cond) #define ITT(cond)
#define ITE(cond)
#endif #endif
#if __ARM_ARCH_ISA_THUMB == 2 #if __ARM_ARCH_ISA_THUMB == 2
#define WIDE(op) op.w #define WIDE(op) op.w
#else #else
#define WIDE(op) op #define WIDE(op) op
#endif #endif
#endif #endif
▲ Show 20 Lines • Show All 61 Lines • Show Last 20 Lines