[PowerPC] Implement vec_xxsldwi builtin.

[jtony]

Summary

Note this patch is based on the infrastructure in patch https://reviews.llvm.org/D33053 . The vec_xxsldwi builtin is also missing from altivec.h. This has been requested by developers working on libvpx for VP9 support for Google ( PR: https://bugs.llvm.org/show_bug.cgi?id=32653). This patch implements the vec_xxsldwi builtin by using the existing shuffleVector instruction just in the FE. The implementation here is similar to vec_xxpermdi in the patch D33053.

And we currently won't emit XXSLDWI in the assembly, subsequent BE optimization work (see patch D33225) needed to identify the correct shuffles so that we can emit XXSLDWI.

[nemanjai]

The changes required for this patch aren't too different from those required for the other patch. Just basically a bit more testing and making the code a bit more readable.

lib/CodeGen/CGBuiltin.cpp

8517

We don't want to clamp this. We should just use the low order two bits. A simple
int64_t Index = ArgCI->getSExtValue() & 0x3;
Should suffice. (although it seems like unsigned and getZExtValue() should be used, but it doesn't really make a difference here).

8529

The indentation of the code in all the cases is off. It should be indented from the case label. In any case, I feel once again that a switch statement is a bit overkill and doesn't really provide additional insight into where the numbers came from.

For example, say you had expressions like this for the elements:

ElemIdx0 = (8 - Index) % 8;
ElemIdx1 = (9 - Index) % 8;
ElemIdx2 = (10 - Index) % 8;
ElemIdx3 = (11 - Index) % 8;

That is easy enough to explain in a comment such as:

// Little endian element N comes from element 8+N-Index of the 
// concatenated wide vector (of course, using modulo arithmetic on
// the total number of elements).

8556

Of course, the expressions to replace the switch here are rather obvious...
ElemIdx<N> = Index + N

8593

This will require the same type conversion as the other patch. I imagine it would crash on something like this:

vector double test(vector double a, vector double b) {
  return vec_xxsldwi(a, b, 1);
}

And of course, add that as a test case.

[jtony]

Address comments from Nemanja.

[nemanjai]

LGTM other than the test case.

test/CodeGen/builtins-ppc-error.c

36

Test for non-vector arguments.

[inouehrs]

lib/CodeGen/CGBuiltin.cpp

8514

minor: uint64_t (or unsigned) for zext value?

8519

minor: unsigned is more common than unsigned int

test/CodeGen/builtins-ppc-error.c

32

Adding const is good here. (https://reviews.llvm.org/D33053#759232)

[jtony]

Address minor comments from Nemanja and Hiroshi.

[nemanjai]

Aside from the minor nit, this LGTM.

lib/CodeGen/CGBuiltin.cpp

8533

Minor nit: no need for the + 0.

[echristo]

Sadly I think constant checking plus the shift makes it hard to do with just __builtin_shufflevector in altivec.h.

LGTM.

-eric

include/clang/Basic/BuiltinsPPC.def

 // Vector Test Data Class builtins
 BUILTIN(__builtin_vsx_xvtstdcdp, "V2ULLiV2dIi", "")
 BUILTIN(__builtin_vsx_xvtstdcsp, "V4UiV4fIi", "")
 
 BUILTIN(__builtin_vsx_insertword, "V16UcV4UiV16UcIi", "")
 BUILTIN(__builtin_vsx_extractuword, "V2ULLiV16UcIi", "")
 
 BUILTIN(__builtin_vsx_xxpermdi, "v.", "t")
+BUILTIN(__builtin_vsx_xxsldwi, "v.", "t")
 
 // HTM builtins
 BUILTIN(__builtin_tbegin, "UiUIi", "")
 BUILTIN(__builtin_tend, "UiUIi", "")
 
 BUILTIN(__builtin_tabort, "UiUi", "")
 BUILTIN(__builtin_tabortdc, "UiUiUiUi", "")
 BUILTIN(__builtin_tabortdci, "UiUiUii", "")

lib/CodeGen/CGBuiltin.cpp

case PPC::BI__builtin_vsx_xxpermdi: {
     Constant *ShuffleElts[2] = {ConstantInt::get(Int32Ty, ElemIdx0),
                                 ConstantInt::get(Int32Ty, ElemIdx1)};
     Constant *ShuffleMask = llvm::ConstantVector::get(ShuffleElts);
 
     Value *ShuffleCall =
         Builder.CreateShuffleVector(Ops[0], Ops[1], ShuffleMask);
     return ShuffleCall;
   }
+
+  case PPC::BI__builtin_vsx_xxsldwi: {
+    // Third argument is a compile time constant int. It must be clamped to
+    // to the range [0, 3].
+    ConstantInt *ArgCI = dyn_cast<ConstantInt>(Ops[2]);
+    assert(ArgCI && "Third arg must be constant integer!");
+    const int64_t MaxIndex = 3;
+    int64_t Index = clamp(ArgCI->getSExtValue(), 0, MaxIndex);
+    Ops[0] = Builder.CreateBitCast(Ops[0], llvm::VectorType::get(Int32Ty, 4));
+    Ops[1] = Builder.CreateBitCast(Ops[1], llvm::VectorType::get(Int32Ty, 4));
+
+    // Create a shuffle mask(ElemIdx0, ElemIdx1)
+    unsigned int ElemIdx0;
+    unsigned int ElemIdx1;
+    unsigned int ElemIdx2;
+    unsigned int ElemIdx3;
+    if (getTarget().isLittleEndian()) {
+      switch (Index) {
+      case 0:
+      ElemIdx0 = 0;
+      ElemIdx1 = 1;
+      ElemIdx2 = 2;
+      ElemIdx3 = 3;
+      break;
+      case 1:
+      ElemIdx0 = 7;
+      ElemIdx1 = 0;
+      ElemIdx2 = 1;
+      ElemIdx3 = 2;
+      break;
+      case 2:
+      ElemIdx0 = 6;
+      ElemIdx1 = 7;
+      ElemIdx2 = 0;
+      ElemIdx3 = 1;
+      break;
+      case 3:
+      ElemIdx0 = 5;
+      ElemIdx1 = 6;
+      ElemIdx2 = 7;
+      ElemIdx3 = 0;
+      break;
+      default:
+        llvm_unreachable("Wrong argument value!");
+      }
+    } else { // BigEndian
+      switch (Index) {
+      case 0:
+      ElemIdx0 = 0;
+      ElemIdx1 = 1;
+      ElemIdx2 = 2;
+      ElemIdx3 = 3;
+      break;
+      case 1:
+      ElemIdx0 = 1;
+      ElemIdx1 = 2;
+      ElemIdx2 = 3;
+      ElemIdx3 = 4;
+      break;
+      case 2:
+      ElemIdx0 = 2;
+      ElemIdx1 = 3;
+      ElemIdx2 = 4;
+      ElemIdx3 = 5;
+      break;
+      case 3:
+      ElemIdx0 = 3;
+      ElemIdx1 = 4;
+      ElemIdx2 = 5;
+      ElemIdx3 = 6;
+      break;
+      default:
+        llvm_unreachable("Wrong argument value!");
+      }
+    }
+
+    Constant *ShuffleElts[4] = { ConstantInt::get(Int32Ty, ElemIdx0),
+                                 ConstantInt::get(Int32Ty, ElemIdx1),
+                                 ConstantInt::get(Int32Ty, ElemIdx2),
+                                 ConstantInt::get(Int32Ty, ElemIdx3)
+                               };
+    Constant *ShuffleMask = llvm::ConstantVector::get(ShuffleElts);
+
+      Value *ShuffleCall = Builder.CreateShuffleVector(Ops[0], Ops[1],  ShuffleMask);
+      return ShuffleCall;
+  }
   }
 }
 
 Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned BuiltinID,
                                               const CallExpr *E) {
   switch (BuiltinID) {
   case AMDGPU::BI__builtin_amdgcn_div_scale:
   case AMDGPU::BI__builtin_amdgcn_div_scalef: {

lib/Headers/altivec.h

static __inline__ void __ATTRS_o_ai vec_vsx_st(vector unsigned char __a,
                                                int __b, unsigned char *__c) {
   __builtin_vsx_stxvw4x((vector int)__a, __b, __c);
 }
 
 #endif
 
 #ifdef __VSX__
 #define vec_xxpermdi __builtin_vsx_xxpermdi
+#define vec_xxsldwi __builtin_vsx_xxsldwi
 #endif
 
 /* vec_xor */
 
 #define __builtin_altivec_vxor vec_xor
 
 static __inline__ vector signed char __ATTRS_o_ai
 vec_xor(vector signed char __a, vector signed char __b) {

lib/Sema/SemaChecking.cpp

bool Sema::CheckPPCBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
   case PPC::BI__builtin_tsr: i = 0; l = 0; u = 7; break;
   case PPC::BI__builtin_tabortwc:
   case PPC::BI__builtin_tabortdc: i = 0; l = 0; u = 31; break;
   case PPC::BI__builtin_tabortwci:
   case PPC::BI__builtin_tabortdci:
     return SemaBuiltinConstantArgRange(TheCall, 0, 0, 31) ||
            SemaBuiltinConstantArgRange(TheCall, 2, 0, 31);
   case PPC::BI__builtin_vsx_xxpermdi:
+  case PPC::BI__builtin_vsx_xxsldwi:
     return SemaBuiltinVSX(TheCall, 3);
   }
   return SemaBuiltinConstantArgRange(TheCall, i, l, u);
 }
 
 bool Sema::CheckSystemZBuiltinFunctionCall(unsigned BuiltinID,
                                            CallExpr *TheCall) {
   if (BuiltinID == SystemZ::BI__builtin_tabort) {

test/CodeGen/builtins-ppc-error.c

 void testXXPERMDI(void) {
   int index = 5;
   vec_xxpermdi(vsi); //expected-error {{too few arguments to function call, expected at least 3, have 1}}
   vec_xxpermdi(vsi, vsi, 2, 4); //expected-error {{too many arguments to function call, expected at most 3, have 4}}
   vec_xxpermdi(vsi, vsi, index); //expected-error {{third argument to '__builtin_vsx_xxpermdi' must be a constant integer between 0-3}}
   vec_xxpermdi(vsi, vsi, -1); //expected-error {{third argument to '__builtin_vsx_xxpermdi' must be a constant integer between 0-3}}
   vec_xxpermdi(vsi, vuc, 2); //expected-error {{first two arguments to '__builtin_vsx_xxpermdi' must be the same type}}
 }
+
+void testXXSLDWI(void) {
+  int index = 5;
+  vec_xxsldwi(vsi); //expected-error {{too few arguments to function call, expected at least 3, have 1}}
+  vec_xxsldwi(vsi, vsi, 2, 4); //expected-error {{too many arguments to function call, expected at most 3, have 4}}
+  vec_xxsldwi(vsi, vsi, index); //expected-error {{third argument to '__builtin_vsx_xxsldwi' must be a constant integer between 0-3}}
+  vec_xxsldwi(vsi, vsi, -1); //expected-error {{third argument to '__builtin_vsx_xxsldwi' must be a constant integer between 0-3}}
+  vec_xxsldwi(vsi, vuc, 2); //expected-error {{first two arguments to '__builtin_vsx_xxsldwi' must be the same type}}
+}

test/CodeGen/builtins-ppc-vsx.c

 
 res_vsc = vec_xxpermdi(vsc, vsc, 0);
 // CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 0, i32 2>
 // CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 3, i32 1>
 
 res_vuc = vec_xxpermdi(vuc, vuc, 1);
 // CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 0, i32 3>
 // CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 2, i32 1>
+
+res_vd = vec_xxsldwi(vd, vd, 0);
+// CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+// CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+
+res_vf = vec_xxsldwi(vf, vf, 1);
+// CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
+// CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 7, i32 0, i32 1, i32 2>
+
+res_vsll = vec_xxsldwi(vsll, vsll, 2);
+// CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
+// CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
+
+res_vull = vec_xxsldwi(vull, vull, 3);
+// CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
+// CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 5, i32 6, i32 7, i32 0>
+
+res_vsi = vec_xxsldwi(vsi, vsi, 0);
+// CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+// CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+
+res_vui = vec_xxsldwi(vui, vui, 1);
+// CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
+// CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 7, i32 0, i32 1, i32 2>
+
+res_vss = vec_xxsldwi(vss, vss, 2);
+// CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
+// CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
+
+
+res_vus = vec_xxsldwi(vus, vus, 3);
+// CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
+// CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 5, i32 6, i32 7, i32 0>
+
+res_vsc = vec_xxsldwi(vsc, vsc, 0);
+// CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+// CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+
+res_vuc = vec_xxsldwi(vuc, vuc, 1);
+// CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
+// CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 7, i32 0, i32 1, i32 2>
 }