[ARM] Mark LEApcrel instructions as isAsCheapAsAMove

[john.brawn]

Summary

Doing this means that if an LEApcrel is used in two places we will rematerialize instead of generating two MOVs. This is particularly useful for printfs using the same format string, where we want to generate an address into a register that's going to get corrupted by the call.

[john.brawn]

Ping.

[jmolloy]

LGTM

llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
   let Inst{23-22} = label{13-12};
   let Inst{21} = 0;
   let Inst{20} = 0;
   let Inst{19-16} = 0b1111;
   let Inst{15-12} = Rd;
   let Inst{11-0} = label{11-0};
 }
 
-let hasSideEffects = 0, isReMaterializable = 1 in
+let hasSideEffects = 0, isReMaterializable = 1, isAsCheapAsAMove = 1 in
 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
                     4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
 
 let hasSideEffects = 1 in
 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
                       (ins i32imm:$label, pred:$p),
                       4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
 

llvm/trunk/lib/Target/ARM/ARMInstrThumb.td

def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
                T1Encoding<{1,0,1,0,0,?}>, Sched<[WriteALU]> {
   bits<3> Rd;
   bits<8> addr;
   let Inst{10-8} = Rd;
   let Inst{7-0} = addr;
   let DecoderMethod = "DecodeThumbAddSpecialReg";
 }
 
-let hasSideEffects = 0, isReMaterializable = 1 in
+let hasSideEffects = 0, isReMaterializable = 1, isAsCheapAsAMove = 1 in
 def tLEApcrel   : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
                               2, IIC_iALUi, []>, Sched<[WriteALU]>;
 
 let hasSideEffects = 1 in
 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
                               (ins i32imm:$label, pred:$p),
                               2, IIC_iALUi, []>, Sched<[WriteALU]>;
 

llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td

def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
   let Inst{21}    = addr{12};
   let Inst{26}    = addr{11};
   let Inst{14-12} = addr{10-8};
   let Inst{7-0}   = addr{7-0};
 
   let DecoderMethod = "DecodeT2Adr";
 }
 
-let hasSideEffects = 0, isReMaterializable = 1 in
+let hasSideEffects = 0, isReMaterializable = 1, isAsCheapAsAMove = 1 in
 def t2LEApcrel   : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
                                 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
 let hasSideEffects = 1 in
 def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
                                 (ins i32imm:$label, pred:$p),
                                 4, IIC_iALUi,
                                 []>, Sched<[WriteALU, ReadALU]>;
 

llvm/trunk/test/CodeGen/ARM/adr-remat.ll

+; RUN: llc -mtriple=armv7a   %s -o - | FileCheck %s
+; RUN: llc -mtriple=thumbv7m %s -o - | FileCheck %s
+; RUN: llc -mtriple=thumbv6m %s -o - | FileCheck %s
+
+@str.1 = private unnamed_addr constant [58 x i8] c"+-------------------------------------------------------+\00"
+@str.2 = private unnamed_addr constant [58 x i8] c"|                                                       |\00"
+
+declare i32 @puts(i8* nocapture readonly)
+
+; Check that we rematerialize the adr of str.1 instead of doing one adr and two
+; movs.
+
+; CHECK: adr r0, [[STR1:.LCPI[0-9]+_[0-9]+]]
+; CHECK: bl puts
+; CHECK: adr r0, {{.LCPI[0-9]+_[0-9]+}}
+; CHECK: bl puts
+; CHECK: adr r0, [[STR1]]
+; CHECK: b{{l?}} puts
+define void @fn() {
+entry:
+  %puts1 = tail call i32 @puts(i8* getelementptr inbounds ([58 x i8], [58 x i8]* @str.1, i32 0, i32 0))
+  %puts2 = tail call i32 @puts(i8* getelementptr inbounds ([58 x i8], [58 x i8]* @str.2, i32 0, i32 0))
+  %puts3 = tail call i32 @puts(i8* getelementptr inbounds ([58 x i8], [58 x i8]* @str.1, i32 0, i32 0))
+  ret void
+}

llvm/trunk/test/CodeGen/ARM/align-sp-adjustment.ll

 ; RUN: llc -mtriple=thumbv7 -o - %s | FileCheck %s
 
-; CHECK: [sp, #2120]
+; p5 will have been pushed to the stack. Check that it's correctly aligned by
+; looking at the offset of the instruction that loads it. Note that this is
+; very fragile and this test may need to be updated if we happen to spill more
+; or less to the stack.
+; CHECK: ldr{{(.w)?}} r{{[0-9]+}}, [sp, #2104]
 
 %struct.struct_2 = type { [172 x %struct.struct_1] }
 %struct.struct_1 = type { i32, i32, i32 }
 
 @.str = private unnamed_addr constant [2 x i8] c"a\00", align 1
 @.str.1 = private unnamed_addr constant [2 x i8] c"b\00", align 1
 @.str.2 = private unnamed_addr constant [2 x i8] c"c\00", align 1
 @.str.3 = private unnamed_addr constant [2 x i8] c"d\00", align 1