[PowerPC] Implement vec_xxsldwi and vec_xxpermdi builtins - llvm portion.

[jtony]

Summary

The vec_xxsldwi and vec_xxpermdi builtins are missing from altivec.h. This has been requested by developers working on libvpx for VP9 support for Google. Define intrinsics to map to the corresponding PowerPC hard instruction (XXSLDWI, and XXPERMDI) directly.

[nemanjai]

Minor nit, the description doesn't need to have the signatures for the builtins (since this patch does not add any such builtins). Also, ATTRS_o_ai is an implementation detail and not part of the signatures required - on an unrelated note, it will probably not even be used in the final implementation.

lib/Target/PowerPC/PPCInstrVSX.td

2283

These don't need to be here. The instructions are not P9 specific. All targets with VSX have them.

test/CodeGen/PowerPC/p9-xxpermdi.ll

1 ↗

(On Diff #97539)

No need to restrict this to P9.

[jtony]

Address the comments from Nemanja.

[kbarton]

Please add the PR that this problem is addressing to the summary.

Aside from that, LGTM.

[echristo]

A quick question:

I think the clang side of these can lower into generic vector operations rather than intrinsics right? Which would mean that we don't need intrinsics defined for these?

Thoughts?

-eric

[jtony]

These builtins (vec_permdi, vec_xlsdwi) can lower into generic vector operations on the clang side only rather than intrinsics in the llvm part and bulitins in the clang part, abandon this patch and re-implement another one in just clang portion.

include/llvm/IR/IntrinsicsPowerPC.td

def int_ppc_vsx_xvcvhpsp :
                             [llvm_v8i16_ty],[IntrNoMem]>;
 def int_ppc_vsx_xxextractuw :
       PowerPC_VSX_Intrinsic<"xxextractuw",[llvm_v2i64_ty],
                             [llvm_v2i64_ty,llvm_i32_ty], [IntrNoMem]>;
 def int_ppc_vsx_xxinsertw :
       PowerPC_VSX_Intrinsic<"xxinsertw",[llvm_v4i32_ty],
                             [llvm_v4i32_ty,llvm_v2i64_ty,llvm_i32_ty],
                             [IntrNoMem]>;
+
+// Vector Permute Doubleword Immediate
+def int_ppc_vsx_xxpermdi :
+      PowerPC_VSX_Intrinsic<"xxpermdi",[llvm_v2i64_ty],
+                            [llvm_v2i64_ty,llvm_v2i64_ty,llvm_i32_ty],
+                            [IntrNoMem]>;
+
+// Vector Shift Left Double by Word Immediate
+def int_ppc_vsx_xxsldwi:
+      PowerPC_VSX_Intrinsic<"xxsldwi",[llvm_v2i64_ty],
+                            [llvm_v2i64_ty,llvm_v2i64_ty,llvm_i32_ty],
+                            [IntrNoMem]>;
 }
 
 //===----------------------------------------------------------------------===//
 // PowerPC QPX Intrinsics.
 //
 
 let TargetPrefix = "ppc" in {  // All PPC intrinsics start with "llvm.ppc.".
   /// PowerPC_QPX_Intrinsic - Base class for all QPX intrinsics.

lib/Target/PowerPC/PPCInstrVSX.td

def XVXSIGSP : XX2_XT6_XO5_XB6<60,  9, 475, "xvxsigsp", vsrc,
                                   (int_ppc_vsx_xvxsigsp v4f32:$XB))]>;
 
   let AddedComplexity = 400, Predicates = [HasP9Vector] in {
   // Extra patterns expanding to vector Extract Word/Insert Word
   def : Pat<(v4i32 (int_ppc_vsx_xxinsertw v4i32:$A, v2i64:$B, imm:$IMM)),
             (v4i32 (XXINSERTW $A, $B, imm:$IMM))>;
   def : Pat<(v2i64 (int_ppc_vsx_xxextractuw v2i64:$A, imm:$IMM)),
             (v2i64 (COPY_TO_REGCLASS (XXEXTRACTUW $A, imm:$IMM), VSRC))>;
   } // AddedComplexity = 400, HasP9Vector
 
+  let  Predicates = [HasVSX] in {
+  // Extra patterns expanding to vector Permute Doubleword Immediate
+  def : Pat<(v2i64 (int_ppc_vsx_xxpermdi v2i64:$A, v2i64:$B, imm:$IMM)),
+            (v2i64 (XXPERMDI $A, $B, imm:$IMM))>;
+
+  // Extra patterns expanding to vector Shift Left Double by Word Immediate
+  def : Pat<(v2i64 (int_ppc_vsx_xxsldwi v2i64:$A, v2i64:$B, imm:$IMM)),
+            (v2i64 (XXSLDWI $A, $B, imm:$IMM))>;
+  } // HasVSX
+
   //===--------------------------------------------------------------------===//
 
   // Test Data Class SP/DP/QP
   let UseVSXReg = 1 in {
   def XSTSTDCSP : XX2_BF3_DCMX7_RS6<60, 298,
                               (outs crrc:$BF), (ins u7imm:$DCMX, vsfrc:$XB),
                               "xststdcsp $BF, $XB, $DCMX", IIC_VecFP, []>;
   def XSTSTDCDP : XX2_BF3_DCMX7_RS6<60, 362,

test/CodeGen/PowerPC/vsx.ll

entry:
     tail call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %a, i8* %b)
     ret void
       ; CHECK-LABEL: test86
       ; CHECK: stxvd2x 34, 0, 5
       ; CHECK: blr
 }
 ; Function Attrs: nounwind readnone
 declare void @llvm.ppc.vsx.stxvd2x.be(<2 x double>, i8*)
+
+define <2 x i64> @test87(<2 x i64> %a, <2 x i64> %b) {
+entry:
+; CHECK-LABEL: test87
+; CHECK: xxmrghd  34, 34, 35
+; CHECK-NEXT: blr
+  %ans = tail call <2 x i64> @llvm.ppc.vsx.xxpermdi(<2 x i64> %a, <2 x i64> %b, i32 0)
+  ret <2 x i64> %ans
+}
+
+define <2 x i64> @test88(<2 x i64> %a, <2 x i64> %b) {
+entry:
+; CHECK-LABEL: test88
+; CHECK: xxpermdi 34, 34, 35, 1
+; CHECK-NEXT: blr
+  %ans = tail call <2 x i64> @llvm.ppc.vsx.xxpermdi(<2 x i64> %a, <2 x i64> %b, i32 1)
+  ret <2 x i64> %ans
+}
+
+define <2 x i64> @test89(<2 x i64> %a, <2 x i64> %b) {
+entry:
+; CHECK-LABEL: test89
+; CHECK: xxpermdi 34, 34, 35, 2
+; CHECK-NEXT: blr
+  %ans = tail call <2 x i64> @llvm.ppc.vsx.xxpermdi(<2 x i64> %a, <2 x i64> %b, i32 2)
+  ret <2 x i64> %ans
+}
+
+define <2 x i64> @test90(<2 x i64> %a, <2 x i64> %b) {
+entry:
+; CHECK-LABEL: test90
+; CHECK: xxmrgld 34, 34, 35
+; CHECK-NEXT: blr
+  %ans = tail call <2 x i64> @llvm.ppc.vsx.xxpermdi(<2 x i64> %a, <2 x i64> %b, i32 3)
+  ret <2 x i64> %ans
+}
+
+declare <2 x i64>  @llvm.ppc.vsx.xxpermdi(<2 x i64>, <2 x i64>, i32)
+
+define <2 x i64> @test91(<2 x i64> %a, <2 x i64> %b) {
+entry:
+; CHECK-LABEL: test91
+; CHECK: xxsldwi 34, 34, 35, 0
+; CHECK-NEXT: blr
+  %ans = tail call <2 x i64> @llvm.ppc.vsx.xxsldwi(<2 x i64> %a, <2 x i64> %b, i32 0)
+  ret <2 x i64> %ans
+}
+
+define <2 x i64> @test92(<2 x i64> %a, <2 x i64> %b) {
+entry:
+; CHECK-LABEL: test92
+; CHECK: xxsldwi 34, 34, 35, 1
+; CHECK-NEXT: blr
+  %ans = tail call <2 x i64> @llvm.ppc.vsx.xxsldwi(<2 x i64> %a, <2 x i64> %b, i32 1)
+  ret <2 x i64> %ans
+}
+
+define <2 x i64> @test93(<2 x i64> %a, <2 x i64> %b) {
+entry:
+; CHECK-LABEL: test93
+; CHECK: xxsldwi 34, 34, 35, 2
+; CHECK-NEXT: blr
+  %ans = tail call <2 x i64> @llvm.ppc.vsx.xxsldwi(<2 x i64> %a, <2 x i64> %b, i32 2)
+  ret <2 x i64> %ans
+}
+
+define <2 x i64> @test94(<2 x i64> %a, <2 x i64> %b) {
+entry:
+; CHECK-LABEL: test94
+; CHECK: xxsldwi 34, 34, 35, 3
+; CHECK-NEXT: blr
+  %ans = tail call <2 x i64> @llvm.ppc.vsx.xxsldwi(<2 x i64> %a, <2 x i64> %b, i32 3)
+  ret <2 x i64> %ans
+}
+
+declare <2 x i64>  @llvm.ppc.vsx.xxsldwi(<2 x i64>, <2 x i64>, i32)