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Differential D32160

[ARM] Rename HW div feature to HW div Thumb. NFCI.
ClosedPublic

Authored by rovka on Apr 18 2017, 3:30 AM.

Details

Reviewers
kristof.beyls
compnerd
t.p.northover
jmolloy
Commits
rG7c6dee9f1629: [ARM] Rename HW div feature to HW div Thumb. NFCI.
rL300827: [ARM] Rename HW div feature to HW div Thumb. NFCI.
Summary

The hardware div feature refers only to Thumb, but because of its name
it is tempting to use it to check for hardware division in general, which
may cause problems in ARM mode. See https://reviews.llvm.org/D32005.

This patch adds "Thumb" to its name, to make its scope clear. One
notable place where I haven't made the change is in the feature flag
(used with -mattr), which is still hwdiv. Changing it would also require
changes in a lot of tests, including clang tests, and it doesn't seem
like it's worth the effort.

Diff Detail

Event Timeline

rovka created this revision.Apr 18 2017, 3:30 AM
Herald added subscribers: rengolin, aemerson. · View Herald TranscriptApr 18 2017, 3:30 AM
compnerd accepted this revision.Apr 19 2017, 6:18 PM

Thanks for doing this cleanup!

This revision is now accepted and ready to land.Apr 19 2017, 6:18 PM
Closed by commit rL300827: [ARM] Rename HW div feature to HW div Thumb. NFCI. (authored by rovka). · Explain WhyApr 20 2017, 2:51 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
include/
llvm/
Support/
38 lines
2 lines
lib/
Support/
2 lines
Target/
ARM/
43 lines
4 lines
3 lines
6 lines
4 lines
4 lines
6 lines
AsmParser/
4 lines
unittests/
Support/
97 lines

Diff 95547

include/llvm/Support/ARMTargetParser.def

Show First 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
ARM_ARCH("armv6kz", AK_ARMV6KZ, "6KZ", "v6kz", ARMBuildAttrs::CPUArch::v6KZ, ARM_ARCH("armv6kz", AK_ARMV6KZ, "6KZ", "v6kz", ARMBuildAttrs::CPUArch::v6KZ,
FK_VFPV2, (ARM::AEK_SEC | ARM::AEK_DSP)) FK_VFPV2, (ARM::AEK_SEC | ARM::AEK_DSP))
ARM_ARCH("armv6-m", AK_ARMV6M, "6-M", "v6m", ARMBuildAttrs::CPUArch::v6_M, ARM_ARCH("armv6-m", AK_ARMV6M, "6-M", "v6m", ARMBuildAttrs::CPUArch::v6_M,
FK_NONE, ARM::AEK_NONE) FK_NONE, ARM::AEK_NONE)
ARM_ARCH("armv7-a", AK_ARMV7A, "7-A", "v7", ARMBuildAttrs::CPUArch::v7, ARM_ARCH("armv7-a", AK_ARMV7A, "7-A", "v7", ARMBuildAttrs::CPUArch::v7,
FK_NEON, ARM::AEK_DSP) FK_NEON, ARM::AEK_DSP)
ARM_ARCH("armv7ve", AK_ARMV7VE, "7VE", "v7ve", ARMBuildAttrs::CPUArch::v7, ARM_ARCH("armv7ve", AK_ARMV7VE, "7VE", "v7ve", ARMBuildAttrs::CPUArch::v7,
FK_NEON, (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | FK_NEON, (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT |
ARM::AEK_HWDIVARM | ARM::AEK_HWDIV | ARM::AEK_DSP)) ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP))
ARM_ARCH("armv7-r", AK_ARMV7R, "7-R", "v7r", ARMBuildAttrs::CPUArch::v7, ARM_ARCH("armv7-r", AK_ARMV7R, "7-R", "v7r", ARMBuildAttrs::CPUArch::v7,
FK_NONE, (ARM::AEK_HWDIV | ARM::AEK_DSP)) FK_NONE, (ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP))
ARM_ARCH("armv7-m", AK_ARMV7M, "7-M", "v7m", ARMBuildAttrs::CPUArch::v7, ARM_ARCH("armv7-m", AK_ARMV7M, "7-M", "v7m", ARMBuildAttrs::CPUArch::v7,
FK_NONE, ARM::AEK_HWDIV) FK_NONE, ARM::AEK_HWDIVTHUMB)
ARM_ARCH("armv7e-m", AK_ARMV7EM, "7E-M", "v7em", ARMBuildAttrs::CPUArch::v7E_M, ARM_ARCH("armv7e-m", AK_ARMV7EM, "7E-M", "v7em", ARMBuildAttrs::CPUArch::v7E_M,
FK_NONE, (ARM::AEK_HWDIV | ARM::AEK_DSP)) FK_NONE, (ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP))
ARM_ARCH("armv8-a", AK_ARMV8A, "8-A", "v8", ARMBuildAttrs::CPUArch::v8_A, ARM_ARCH("armv8-a", AK_ARMV8A, "8-A", "v8", ARMBuildAttrs::CPUArch::v8_A,
FK_CRYPTO_NEON_FP_ARMV8, FK_CRYPTO_NEON_FP_ARMV8,
(ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
ARM::AEK_HWDIV | ARM::AEK_DSP | ARM::AEK_CRC)) ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC))
ARM_ARCH("armv8.1-a", AK_ARMV8_1A, "8.1-A", "v8.1a", ARM_ARCH("armv8.1-a", AK_ARMV8_1A, "8.1-A", "v8.1a",
ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8, ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
(ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
ARM::AEK_HWDIV | ARM::AEK_DSP | ARM::AEK_CRC)) ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC))
ARM_ARCH("armv8.2-a", AK_ARMV8_2A, "8.2-A", "v8.2a", ARM_ARCH("armv8.2-a", AK_ARMV8_2A, "8.2-A", "v8.2a",
ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8, ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
(ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
ARM::AEK_HWDIV | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS)) ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS))
ARM_ARCH("armv8-r", AK_ARMV8R, "8-R", "v8r", ARMBuildAttrs::CPUArch::v8_R, ARM_ARCH("armv8-r", AK_ARMV8R, "8-R", "v8r", ARMBuildAttrs::CPUArch::v8_R,
FK_NEON_FP_ARMV8, FK_NEON_FP_ARMV8,
(ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_HWDIV | (ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
ARM::AEK_DSP | ARM::AEK_CRC)) ARM::AEK_DSP | ARM::AEK_CRC))
ARM_ARCH("armv8-m.base", AK_ARMV8MBaseline, "8-M.Baseline", "v8m.base", ARM_ARCH("armv8-m.base", AK_ARMV8MBaseline, "8-M.Baseline", "v8m.base",
ARMBuildAttrs::CPUArch::v8_M_Base, FK_NONE, ARM::AEK_HWDIV) ARMBuildAttrs::CPUArch::v8_M_Base, FK_NONE, ARM::AEK_HWDIVTHUMB)
ARM_ARCH("armv8-m.main", AK_ARMV8MMainline, "8-M.Mainline", "v8m.main", ARM_ARCH("armv8-m.main", AK_ARMV8MMainline, "8-M.Mainline", "v8m.main",
ARMBuildAttrs::CPUArch::v8_M_Main, FK_FPV5_D16, ARM::AEK_HWDIV) ARMBuildAttrs::CPUArch::v8_M_Main, FK_FPV5_D16, ARM::AEK_HWDIVTHUMB)
// Non-standard Arch names. // Non-standard Arch names.
ARM_ARCH("iwmmxt", AK_IWMMXT, "iwmmxt", "", ARMBuildAttrs::CPUArch::v5TE, ARM_ARCH("iwmmxt", AK_IWMMXT, "iwmmxt", "", ARMBuildAttrs::CPUArch::v5TE,
FK_NONE, ARM::AEK_NONE) FK_NONE, ARM::AEK_NONE)
ARM_ARCH("iwmmxt2", AK_IWMMXT2, "iwmmxt2", "", ARMBuildAttrs::CPUArch::v5TE, ARM_ARCH("iwmmxt2", AK_IWMMXT2, "iwmmxt2", "", ARMBuildAttrs::CPUArch::v5TE,
FK_NONE, ARM::AEK_NONE) FK_NONE, ARM::AEK_NONE)
ARM_ARCH("xscale", AK_XSCALE, "xscale", "v5e", ARMBuildAttrs::CPUArch::v5TE, ARM_ARCH("xscale", AK_XSCALE, "xscale", "v5e", ARMBuildAttrs::CPUArch::v5TE,
FK_NONE, ARM::AEK_NONE) FK_NONE, ARM::AEK_NONE)
ARM_ARCH("armv7s", AK_ARMV7S, "7-S", "v7s", ARMBuildAttrs::CPUArch::v7, ARM_ARCH("armv7s", AK_ARMV7S, "7-S", "v7s", ARMBuildAttrs::CPUArch::v7,
FK_NEON_VFPV4, ARM::AEK_DSP) FK_NEON_VFPV4, ARM::AEK_DSP)
ARM_ARCH("armv7k", AK_ARMV7K, "7-K", "v7k", ARMBuildAttrs::CPUArch::v7, ARM_ARCH("armv7k", AK_ARMV7K, "7-K", "v7k", ARMBuildAttrs::CPUArch::v7,
FK_NONE, ARM::AEK_DSP) FK_NONE, ARM::AEK_DSP)
#undef ARM_ARCH #undef ARM_ARCH
#ifndef ARM_ARCH_EXT_NAME #ifndef ARM_ARCH_EXT_NAME
#define ARM_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE) #define ARM_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE)
#endif #endif
// FIXME: This would be nicer were it tablegen // FIXME: This would be nicer were it tablegen
ARM_ARCH_EXT_NAME("invalid", ARM::AEK_INVALID, nullptr, nullptr) ARM_ARCH_EXT_NAME("invalid", ARM::AEK_INVALID, nullptr, nullptr)
ARM_ARCH_EXT_NAME("none", ARM::AEK_NONE, nullptr, nullptr) ARM_ARCH_EXT_NAME("none", ARM::AEK_NONE, nullptr, nullptr)
ARM_ARCH_EXT_NAME("crc", ARM::AEK_CRC, "+crc", "-crc") ARM_ARCH_EXT_NAME("crc", ARM::AEK_CRC, "+crc", "-crc")
ARM_ARCH_EXT_NAME("crypto", ARM::AEK_CRYPTO, "+crypto","-crypto") ARM_ARCH_EXT_NAME("crypto", ARM::AEK_CRYPTO, "+crypto","-crypto")
ARM_ARCH_EXT_NAME("dsp", ARM::AEK_DSP, "+dsp", "-dsp") ARM_ARCH_EXT_NAME("dsp", ARM::AEK_DSP, "+dsp", "-dsp")
ARM_ARCH_EXT_NAME("fp", ARM::AEK_FP, nullptr, nullptr) ARM_ARCH_EXT_NAME("fp", ARM::AEK_FP, nullptr, nullptr)
ARM_ARCH_EXT_NAME("idiv", (ARM::AEK_HWDIVARM | ARM::AEK_HWDIV), nullptr, nullptr) ARM_ARCH_EXT_NAME("idiv", (ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB), nullptr, nullptr)
ARM_ARCH_EXT_NAME("mp", ARM::AEK_MP, nullptr, nullptr) ARM_ARCH_EXT_NAME("mp", ARM::AEK_MP, nullptr, nullptr)
ARM_ARCH_EXT_NAME("simd", ARM::AEK_SIMD, nullptr, nullptr) ARM_ARCH_EXT_NAME("simd", ARM::AEK_SIMD, nullptr, nullptr)
ARM_ARCH_EXT_NAME("sec", ARM::AEK_SEC, nullptr, nullptr) ARM_ARCH_EXT_NAME("sec", ARM::AEK_SEC, nullptr, nullptr)
ARM_ARCH_EXT_NAME("virt", ARM::AEK_VIRT, nullptr, nullptr) ARM_ARCH_EXT_NAME("virt", ARM::AEK_VIRT, nullptr, nullptr)
ARM_ARCH_EXT_NAME("fp16", ARM::AEK_FP16, "+fullfp16", "-fullfp16") ARM_ARCH_EXT_NAME("fp16", ARM::AEK_FP16, "+fullfp16", "-fullfp16")
ARM_ARCH_EXT_NAME("ras", ARM::AEK_RAS, "+ras", "-ras") ARM_ARCH_EXT_NAME("ras", ARM::AEK_RAS, "+ras", "-ras")
ARM_ARCH_EXT_NAME("os", ARM::AEK_OS, nullptr, nullptr) ARM_ARCH_EXT_NAME("os", ARM::AEK_OS, nullptr, nullptr)
ARM_ARCH_EXT_NAME("iwmmxt", ARM::AEK_IWMMXT, nullptr, nullptr) ARM_ARCH_EXT_NAME("iwmmxt", ARM::AEK_IWMMXT, nullptr, nullptr)
ARM_ARCH_EXT_NAME("iwmmxt2", ARM::AEK_IWMMXT2, nullptr, nullptr) ARM_ARCH_EXT_NAME("iwmmxt2", ARM::AEK_IWMMXT2, nullptr, nullptr)
ARM_ARCH_EXT_NAME("maverick", ARM::AEK_MAVERICK, nullptr, nullptr) ARM_ARCH_EXT_NAME("maverick", ARM::AEK_MAVERICK, nullptr, nullptr)
ARM_ARCH_EXT_NAME("xscale", ARM::AEK_XSCALE, nullptr, nullptr) ARM_ARCH_EXT_NAME("xscale", ARM::AEK_XSCALE, nullptr, nullptr)
#undef ARM_ARCH_EXT_NAME #undef ARM_ARCH_EXT_NAME
#ifndef ARM_HW_DIV_NAME #ifndef ARM_HW_DIV_NAME
#define ARM_HW_DIV_NAME(NAME, ID) #define ARM_HW_DIV_NAME(NAME, ID)
#endif #endif
ARM_HW_DIV_NAME("invalid", ARM::AEK_INVALID) ARM_HW_DIV_NAME("invalid", ARM::AEK_INVALID)
ARM_HW_DIV_NAME("none", ARM::AEK_NONE) ARM_HW_DIV_NAME("none", ARM::AEK_NONE)
ARM_HW_DIV_NAME("thumb", ARM::AEK_HWDIV) ARM_HW_DIV_NAME("thumb", ARM::AEK_HWDIVTHUMB)
ARM_HW_DIV_NAME("arm", ARM::AEK_HWDIVARM) ARM_HW_DIV_NAME("arm", ARM::AEK_HWDIVARM)
ARM_HW_DIV_NAME("arm,thumb", (ARM::AEK_HWDIVARM | ARM::AEK_HWDIV)) ARM_HW_DIV_NAME("arm,thumb", (ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB))
#undef ARM_HW_DIV_NAME #undef ARM_HW_DIV_NAME
#ifndef ARM_CPU_NAME #ifndef ARM_CPU_NAME
#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) #define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT)
#endif #endif
ARM_CPU_NAME("arm2", AK_ARMV2, FK_NONE, true, ARM::AEK_NONE) ARM_CPU_NAME("arm2", AK_ARMV2, FK_NONE, true, ARM::AEK_NONE)
ARM_CPU_NAME("arm3", AK_ARMV2A, FK_NONE, true, ARM::AEK_NONE) ARM_CPU_NAME("arm3", AK_ARMV2A, FK_NONE, true, ARM::AEK_NONE)
ARM_CPU_NAME("arm6", AK_ARMV3, FK_NONE, true, ARM::AEK_NONE) ARM_CPU_NAME("arm6", AK_ARMV3, FK_NONE, true, ARM::AEK_NONE)
Show All 39 Lines
ARM_CPU_NAME("cortex-m0", AK_ARMV6M, FK_NONE, true, ARM::AEK_NONE) ARM_CPU_NAME("cortex-m0", AK_ARMV6M, FK_NONE, true, ARM::AEK_NONE)
ARM_CPU_NAME("cortex-m0plus", AK_ARMV6M, FK_NONE, false, ARM::AEK_NONE) ARM_CPU_NAME("cortex-m0plus", AK_ARMV6M, FK_NONE, false, ARM::AEK_NONE)
ARM_CPU_NAME("cortex-m1", AK_ARMV6M, FK_NONE, false, ARM::AEK_NONE) ARM_CPU_NAME("cortex-m1", AK_ARMV6M, FK_NONE, false, ARM::AEK_NONE)
ARM_CPU_NAME("sc000", AK_ARMV6M, FK_NONE, false, ARM::AEK_NONE) ARM_CPU_NAME("sc000", AK_ARMV6M, FK_NONE, false, ARM::AEK_NONE)
ARM_CPU_NAME("cortex-a5", AK_ARMV7A, FK_NEON_VFPV4, false, ARM_CPU_NAME("cortex-a5", AK_ARMV7A, FK_NEON_VFPV4, false,
(ARM::AEK_SEC | ARM::AEK_MP)) (ARM::AEK_SEC | ARM::AEK_MP))
ARM_CPU_NAME("cortex-a7", AK_ARMV7A, FK_NEON_VFPV4, false, ARM_CPU_NAME("cortex-a7", AK_ARMV7A, FK_NEON_VFPV4, false,
(ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
ARM::AEK_HWDIV)) ARM::AEK_HWDIVTHUMB))
ARM_CPU_NAME("cortex-a8", AK_ARMV7A, FK_NEON, true, ARM::AEK_SEC) ARM_CPU_NAME("cortex-a8", AK_ARMV7A, FK_NEON, true, ARM::AEK_SEC)
ARM_CPU_NAME("cortex-a9", AK_ARMV7A, FK_NEON_FP16, false, (ARM::AEK_SEC | ARM::AEK_MP)) ARM_CPU_NAME("cortex-a9", AK_ARMV7A, FK_NEON_FP16, false, (ARM::AEK_SEC | ARM::AEK_MP))
ARM_CPU_NAME("cortex-a12", AK_ARMV7A, FK_NEON_VFPV4, false, ARM_CPU_NAME("cortex-a12", AK_ARMV7A, FK_NEON_VFPV4, false,
(ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
ARM::AEK_HWDIV)) ARM::AEK_HWDIVTHUMB))
ARM_CPU_NAME("cortex-a15", AK_ARMV7A, FK_NEON_VFPV4, false, ARM_CPU_NAME("cortex-a15", AK_ARMV7A, FK_NEON_VFPV4, false,
(ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
ARM::AEK_HWDIV)) ARM::AEK_HWDIVTHUMB))
ARM_CPU_NAME("cortex-a17", AK_ARMV7A, FK_NEON_VFPV4, false, ARM_CPU_NAME("cortex-a17", AK_ARMV7A, FK_NEON_VFPV4, false,
(ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
ARM::AEK_HWDIV)) ARM::AEK_HWDIVTHUMB))
ARM_CPU_NAME("krait", AK_ARMV7A, FK_NEON_VFPV4, false, ARM_CPU_NAME("krait", AK_ARMV7A, FK_NEON_VFPV4, false,
(ARM::AEK_HWDIVARM | ARM::AEK_HWDIV)) (ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB))
ARM_CPU_NAME("cortex-r4", AK_ARMV7R, FK_NONE, true, ARM::AEK_NONE) ARM_CPU_NAME("cortex-r4", AK_ARMV7R, FK_NONE, true, ARM::AEK_NONE)
ARM_CPU_NAME("cortex-r4f", AK_ARMV7R, FK_VFPV3_D16, false, ARM::AEK_NONE) ARM_CPU_NAME("cortex-r4f", AK_ARMV7R, FK_VFPV3_D16, false, ARM::AEK_NONE)
ARM_CPU_NAME("cortex-r5", AK_ARMV7R, FK_VFPV3_D16, false, ARM_CPU_NAME("cortex-r5", AK_ARMV7R, FK_VFPV3_D16, false,
(ARM::AEK_MP | ARM::AEK_HWDIVARM)) (ARM::AEK_MP | ARM::AEK_HWDIVARM))
ARM_CPU_NAME("cortex-r7", AK_ARMV7R, FK_VFPV3_D16_FP16, false, ARM_CPU_NAME("cortex-r7", AK_ARMV7R, FK_VFPV3_D16_FP16, false,
(ARM::AEK_MP | ARM::AEK_HWDIVARM)) (ARM::AEK_MP | ARM::AEK_HWDIVARM))
ARM_CPU_NAME("cortex-r8", AK_ARMV7R, FK_VFPV3_D16_FP16, false, ARM_CPU_NAME("cortex-r8", AK_ARMV7R, FK_VFPV3_D16_FP16, false,
(ARM::AEK_MP | ARM::AEK_HWDIVARM)) (ARM::AEK_MP | ARM::AEK_HWDIVARM))
Show All 14 Lines
ARM_CPU_NAME("exynos-m1", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC) ARM_CPU_NAME("exynos-m1", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
ARM_CPU_NAME("exynos-m2", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC) ARM_CPU_NAME("exynos-m2", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
ARM_CPU_NAME("exynos-m3", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC) ARM_CPU_NAME("exynos-m3", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
ARM_CPU_NAME("kryo", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC) ARM_CPU_NAME("kryo", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
// Non-standard Arch names. // Non-standard Arch names.
ARM_CPU_NAME("iwmmxt", AK_IWMMXT, FK_NONE, true, ARM::AEK_NONE) ARM_CPU_NAME("iwmmxt", AK_IWMMXT, FK_NONE, true, ARM::AEK_NONE)
ARM_CPU_NAME("xscale", AK_XSCALE, FK_NONE, true, ARM::AEK_NONE) ARM_CPU_NAME("xscale", AK_XSCALE, FK_NONE, true, ARM::AEK_NONE)
ARM_CPU_NAME("swift", AK_ARMV7S, FK_NEON_VFPV4, true, ARM_CPU_NAME("swift", AK_ARMV7S, FK_NEON_VFPV4, true,
(ARM::AEK_HWDIVARM | ARM::AEK_HWDIV)) (ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB))
// Invalid CPU // Invalid CPU
ARM_CPU_NAME("invalid", AK_INVALID, FK_INVALID, true, ARM::AEK_INVALID) ARM_CPU_NAME("invalid", AK_INVALID, FK_INVALID, true, ARM::AEK_INVALID)
#undef ARM_CPU_NAME #undef ARM_CPU_NAME

include/llvm/Support/TargetParser.h

Show First 20 Lines • Show All 69 Lines • ▼ Show 20 Lines
// Arch extension modifiers for CPUs. // Arch extension modifiers for CPUs.
enum ArchExtKind : unsigned { enum ArchExtKind : unsigned {
AEK_INVALID = 0x0, AEK_INVALID = 0x0,
AEK_NONE = 0x1, AEK_NONE = 0x1,
AEK_CRC = 0x2, AEK_CRC = 0x2,
AEK_CRYPTO = 0x4, AEK_CRYPTO = 0x4,
AEK_FP = 0x8, AEK_FP = 0x8,
AEK_HWDIV = 0x10, AEK_HWDIVTHUMB = 0x10,
AEK_HWDIVARM = 0x20, AEK_HWDIVARM = 0x20,
AEK_MP = 0x40, AEK_MP = 0x40,
AEK_SIMD = 0x80, AEK_SIMD = 0x80,
AEK_SEC = 0x100, AEK_SEC = 0x100,
AEK_VIRT = 0x200, AEK_VIRT = 0x200,
AEK_DSP = 0x400, AEK_DSP = 0x400,
AEK_FP16 = 0x800, AEK_FP16 = 0x800,
AEK_RAS = 0x1000, AEK_RAS = 0x1000,
▲ Show 20 Lines • Show All 123 Lines • Show Last 20 Lines

lib/Support/TargetParser.cpp

Show First 20 Lines • Show All 204 Lines • ▼ Show 20 Linesbool llvm::ARM::getHWDivFeatures(unsigned HWDivKind,
if (HWDivKind == ARM::AEK_INVALID) if (HWDivKind == ARM::AEK_INVALID)
return false; return false;
if (HWDivKind & ARM::AEK_HWDIVARM) if (HWDivKind & ARM::AEK_HWDIVARM)
Features.push_back("+hwdiv-arm"); Features.push_back("+hwdiv-arm");
else else
Features.push_back("-hwdiv-arm"); Features.push_back("-hwdiv-arm");
if (HWDivKind & ARM::AEK_HWDIV) if (HWDivKind & ARM::AEK_HWDIVTHUMB)
Features.push_back("+hwdiv"); Features.push_back("+hwdiv");
else else
Features.push_back("-hwdiv"); Features.push_back("-hwdiv");
return true; return true;
} }
bool llvm::ARM::getExtensionFeatures(unsigned Extensions, bool llvm::ARM::getExtensionFeatures(unsigned Extensions,
▲ Show 20 Lines • Show All 620 Lines • Show Last 20 Lines

lib/Target/ARM/ARM.td

Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8",
"true", "Enable ARMv8 FP", "true", "Enable ARMv8 FP",
[FeatureVFP4]>; [FeatureVFP4]>;
def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true", def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
"Enable full half-precision floating point", "Enable full half-precision floating point",
[FeatureFPARMv8]>; [FeatureFPARMv8]>;
def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true", def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true",
"Restrict FP to 16 double registers">; "Restrict FP to 16 double registers">;
def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true", def FeatureHWDivThumb : SubtargetFeature<"hwdiv", "HasHardwareDivideInThumb",
"Enable divide instructions">; "true",
"Enable divide instructions in Thumb">;
def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm", def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm",
"HasHardwareDivideInARM", "true", "HasHardwareDivideInARM", "true",
"Enable divide instructions in ARM mode">; "Enable divide instructions in ARM mode">;
def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true", def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
"Has data barrier (dmb / dsb) instructions">; "Has data barrier (dmb / dsb) instructions">;
def FeatureV7Clrex : SubtargetFeature<"v7clrex", "HasV7Clrex", "true", def FeatureV7Clrex : SubtargetFeature<"v7clrex", "HasV7Clrex", "true",
"Has v7 clrex instruction">; "Has v7 clrex instruction">;
def FeatureAcquireRelease : SubtargetFeature<"acquire-release", def FeatureAcquireRelease : SubtargetFeature<"acquire-release",
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// Multiprocessing extension. // Multiprocessing extension.
def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true", def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
"Supports Multiprocessing extension">; "Supports Multiprocessing extension">;
// Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8). // Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8).
def FeatureVirtualization : SubtargetFeature<"virtualization", def FeatureVirtualization : SubtargetFeature<"virtualization",
"HasVirtualization", "true", "HasVirtualization", "true",
"Supports Virtualization extension", "Supports Virtualization extension",
[FeatureHWDiv, FeatureHWDivARM]>; [FeatureHWDivThumb, FeatureHWDivARM]>;
// M-series ISA // M-series ISA
def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass", def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
"Is microcontroller profile ('M' series)">; "Is microcontroller profile ('M' series)">;
// R-series ISA // R-series ISA
def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass", def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass",
"Is realtime profile ('R' series)">; "Is realtime profile ('R' series)">;
▲ Show 20 Lines • Show All 191 Lines • ▼ Show 20 Linesdef ARMv7ve : Architecture<"armv7ve", "ARMv7ve", [HasV7Ops,
FeatureTrustZone, FeatureTrustZone,
FeatureMP, FeatureMP,
FeatureVirtualization, FeatureVirtualization,
FeatureAClass]>; FeatureAClass]>;
def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops, def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops,
FeatureDB, FeatureDB,
FeatureDSP, FeatureDSP,
FeatureHWDiv, FeatureHWDivThumb,
FeatureRClass]>; FeatureRClass]>;
def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops, def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops,
FeatureThumb2, FeatureThumb2,
FeatureNoARM, FeatureNoARM,
FeatureDB, FeatureDB,
FeatureHWDiv, FeatureHWDivThumb,
FeatureMClass]>; FeatureMClass]>;
def ARMv7em : Architecture<"armv7e-m", "ARMv7em", [HasV7Ops, def ARMv7em : Architecture<"armv7e-m", "ARMv7em", [HasV7Ops,
FeatureThumb2, FeatureThumb2,
FeatureNoARM, FeatureNoARM,
FeatureDB, FeatureDB,
FeatureHWDiv, FeatureHWDivThumb,
FeatureMClass, FeatureMClass,
FeatureDSP]>; FeatureDSP]>;
def ARMv8a : Architecture<"armv8-a", "ARMv8a", [HasV8Ops, def ARMv8a : Architecture<"armv8-a", "ARMv8a", [HasV8Ops,
FeatureAClass, FeatureAClass,
FeatureDB, FeatureDB,
FeatureFPARMv8, FeatureFPARMv8,
FeatureNEON, FeatureNEON,
Show All 38 Linesdef ARMv8r : Architecture<"armv8-r", "ARMv8r", [HasV8Ops,
FeatureVirtualization, FeatureVirtualization,
FeatureFPARMv8, FeatureFPARMv8,
FeatureNEON]>; FeatureNEON]>;
def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline", def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline",
[HasV8MBaselineOps, [HasV8MBaselineOps,
FeatureNoARM, FeatureNoARM,
FeatureDB, FeatureDB,
FeatureHWDiv, FeatureHWDivThumb,
FeatureV7Clrex, FeatureV7Clrex,
Feature8MSecExt, Feature8MSecExt,
FeatureAcquireRelease, FeatureAcquireRelease,
FeatureMClass]>; FeatureMClass]>;
def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline", def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline",
[HasV8MMainlineOps, [HasV8MMainlineOps,
FeatureNoARM, FeatureNoARM,
FeatureDB, FeatureDB,
FeatureHWDiv, FeatureHWDivThumb,
Feature8MSecExt, Feature8MSecExt,
FeatureAcquireRelease, FeatureAcquireRelease,
FeatureMClass]>; FeatureMClass]>;
// Aliases // Aliases
def IWMMXT : Architecture<"iwmmxt", "ARMv5te", [ARMv5te]>; def IWMMXT : Architecture<"iwmmxt", "ARMv5te", [ARMv5te]>;
def IWMMXT2 : Architecture<"iwmmxt2", "ARMv5te", [ARMv5te]>; def IWMMXT2 : Architecture<"iwmmxt2", "ARMv5te", [ARMv5te]>;
def XScale : Architecture<"xscale", "ARMv5te", [ARMv5te]>; def XScale : Architecture<"xscale", "ARMv5te", [ARMv5te]>;
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def : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait, def : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait,
FeatureHasRetAddrStack, FeatureHasRetAddrStack,
FeatureMuxedUnits, FeatureMuxedUnits,
FeatureCheckVLDnAlign, FeatureCheckVLDnAlign,
FeatureVMLxForwarding, FeatureVMLxForwarding,
FeatureFP16, FeatureFP16,
FeatureAvoidPartialCPSR, FeatureAvoidPartialCPSR,
FeatureVFP4, FeatureVFP4,
FeatureHWDiv, FeatureHWDivThumb,
FeatureHWDivARM]>; FeatureHWDivARM]>;
def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift, def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift,
FeatureHasRetAddrStack, FeatureHasRetAddrStack,
FeatureNEONForFP, FeatureNEONForFP,
FeatureVFP4, FeatureVFP4,
FeatureMP, FeatureMP,
FeatureHWDiv, FeatureHWDivThumb,
FeatureHWDivARM, FeatureHWDivARM,
FeatureAvoidPartialCPSR, FeatureAvoidPartialCPSR,
FeatureAvoidMOVsShOp, FeatureAvoidMOVsShOp,
FeatureHasSlowFPVMLx, FeatureHasSlowFPVMLx,
FeatureHasVMLxHazards, FeatureHasVMLxHazards,
FeatureProfUnpredicate, FeatureProfUnpredicate,
FeaturePrefISHSTBarrier, FeaturePrefISHSTBarrier,
FeatureSlowOddRegister, FeatureSlowOddRegister,
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def : ProcNoItin<"cortex-m33", [ARMv8mMainline, def : ProcNoItin<"cortex-m33", [ARMv8mMainline,
FeatureDSP, FeatureDSP,
FeatureFPARMv8, FeatureFPARMv8,
FeatureD16, FeatureD16,
FeatureVFPOnlySP]>; FeatureVFPOnlySP]>;
def : ProcNoItin<"cortex-a32", [ARMv8a, def : ProcNoItin<"cortex-a32", [ARMv8a,
FeatureHWDiv, FeatureHWDivThumb,
FeatureHWDivARM, FeatureHWDivARM,
FeatureCrypto, FeatureCrypto,
FeatureCRC]>; FeatureCRC]>;
def : ProcNoItin<"cortex-a35", [ARMv8a, ProcA35, def : ProcNoItin<"cortex-a35", [ARMv8a, ProcA35,
FeatureHWDiv, FeatureHWDivThumb,
FeatureHWDivARM, FeatureHWDivARM,
FeatureCrypto, FeatureCrypto,
FeatureCRC]>; FeatureCRC]>;
def : ProcNoItin<"cortex-a53", [ARMv8a, ProcA53, def : ProcNoItin<"cortex-a53", [ARMv8a, ProcA53,
FeatureHWDiv, FeatureHWDivThumb,
FeatureHWDivARM, FeatureHWDivARM,
FeatureCrypto, FeatureCrypto,
FeatureCRC, FeatureCRC,
FeatureFPAO]>; FeatureFPAO]>;
def : ProcNoItin<"cortex-a57", [ARMv8a, ProcA57, def : ProcNoItin<"cortex-a57", [ARMv8a, ProcA57,
FeatureHWDiv, FeatureHWDivThumb,
FeatureHWDivARM, FeatureHWDivARM,
FeatureCrypto, FeatureCrypto,
FeatureCRC, FeatureCRC,
FeatureFPAO]>; FeatureFPAO]>;
def : ProcNoItin<"cortex-a72", [ARMv8a, ProcA72, def : ProcNoItin<"cortex-a72", [ARMv8a, ProcA72,
FeatureHWDiv, FeatureHWDivThumb,
FeatureHWDivARM, FeatureHWDivARM,
FeatureCrypto, FeatureCrypto,
FeatureCRC]>; FeatureCRC]>;
def : ProcNoItin<"cortex-a73", [ARMv8a, ProcA73, def : ProcNoItin<"cortex-a73", [ARMv8a, ProcA73,
FeatureHWDiv, FeatureHWDivThumb,
FeatureHWDivARM, FeatureHWDivARM,
FeatureCrypto, FeatureCrypto,
FeatureCRC]>; FeatureCRC]>;
// Cyclone is very similar to swift // Cyclone is very similar to swift
def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift, def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift,
FeatureHasRetAddrStack, FeatureHasRetAddrStack,
FeatureNEONForFP, FeatureNEONForFP,
FeatureVFP4, FeatureVFP4,
FeatureMP, FeatureMP,
FeatureHWDiv, FeatureHWDivThumb,
FeatureHWDivARM, FeatureHWDivARM,
FeatureAvoidPartialCPSR, FeatureAvoidPartialCPSR,
FeatureAvoidMOVsShOp, FeatureAvoidMOVsShOp,
FeatureHasSlowFPVMLx, FeatureHasSlowFPVMLx,
FeatureCrypto, FeatureCrypto,
FeatureZCZeroing]>; FeatureZCZeroing]>;
def : ProcNoItin<"exynos-m1", [ARMv8a, ProcExynosM1, def : ProcNoItin<"exynos-m1", [ARMv8a, ProcExynosM1,
FeatureHWDiv, FeatureHWDivThumb,
FeatureHWDivARM, FeatureHWDivARM,
FeatureCrypto, FeatureCrypto,
FeatureCRC]>; FeatureCRC]>;
def : ProcNoItin<"exynos-m2", [ARMv8a, ProcExynosM1, def : ProcNoItin<"exynos-m2", [ARMv8a, ProcExynosM1,
FeatureHWDiv, FeatureHWDivThumb,
FeatureHWDivARM, FeatureHWDivARM,
FeatureCrypto, FeatureCrypto,
FeatureCRC]>; FeatureCRC]>;
def : ProcNoItin<"exynos-m3", [ARMv8a, ProcExynosM1, def : ProcNoItin<"exynos-m3", [ARMv8a, ProcExynosM1,
FeatureHWDiv, FeatureHWDivThumb,
FeatureHWDivARM, FeatureHWDivARM,
FeatureCrypto, FeatureCrypto,
FeatureCRC]>; FeatureCRC]>;
def : ProcNoItin<"kryo", [ARMv8a, ProcKryo, def : ProcNoItin<"kryo", [ARMv8a, ProcKryo,
FeatureHWDiv, FeatureHWDivThumb,
FeatureHWDivARM, FeatureHWDivARM,
FeatureCrypto, FeatureCrypto,
FeatureCRC]>; FeatureCRC]>;
def : ProcessorModel<"cortex-r52", CortexR52Model, [ARMv8r, ProcR52, def : ProcessorModel<"cortex-r52", CortexR52Model, [ARMv8r, ProcR52,
FeatureFPAO]>; FeatureFPAO]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
Show All 40 Lines

lib/Target/ARM/ARMAsmPrinter.cpp

Show First 20 Lines • Show All 673 Lines • ▼ Show 20 Linesvoid ARMAsmPrinter::emitAttributes() {
const std::string &CPUString = STI.getCPUString(); const std::string &CPUString = STI.getCPUString();
if (!StringRef(CPUString).startswith("generic")) { if (!StringRef(CPUString).startswith("generic")) {
// FIXME: remove krait check when GNU tools support krait cpu // FIXME: remove krait check when GNU tools support krait cpu
if (STI.isKrait()) { if (STI.isKrait()) {
ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a9"); ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a9");
// We consider krait as a "cortex-a9" + hwdiv CPU // We consider krait as a "cortex-a9" + hwdiv CPU
// Enable hwdiv through ".arch_extension idiv" // Enable hwdiv through ".arch_extension idiv"
if (STI.hasDivide() || STI.hasDivideInARMMode()) if (STI.hasDivideInThumbMode() || STI.hasDivideInARMMode())
ATS.emitArchExtension(ARM::AEK_HWDIV | ARM::AEK_HWDIVARM); ATS.emitArchExtension(ARM::AEK_HWDIVTHUMB | ARM::AEK_HWDIVARM);
} else } else
ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString); ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
} }
ATS.emitAttribute(ARMBuildAttrs::CPU_arch, getArchForCPU(CPUString, &STI)); ATS.emitAttribute(ARMBuildAttrs::CPU_arch, getArchForCPU(CPUString, &STI));
// Tag_CPU_arch_profile must have the default value of 0 when "Architecture // Tag_CPU_arch_profile must have the default value of 0 when "Architecture
// profile is not applicable (e.g. pre v7, or cross-profile code)". // profile is not applicable (e.g. pre v7, or cross-profile code)".
▲ Show 20 Lines • Show All 1,479 Lines • Show Last 20 Lines

lib/Target/ARM/ARMFastISel.cpp

Show First 20 Lines • Show All 1,696 Lines • ▼ Show 20 Linesbool ARMFastISel::SelectDiv(const Instruction *I, bool isSigned) {
MVT VT; MVT VT;
Type *Ty = I->getType(); Type *Ty = I->getType();
if (!isTypeLegal(Ty, VT)) if (!isTypeLegal(Ty, VT))
return false; return false;
// If we have integer div support we should have selected this automagically. // If we have integer div support we should have selected this automagically.
// In case we have a real miss go ahead and return false and we'll pick // In case we have a real miss go ahead and return false and we'll pick
// it up later. // it up later.
if (Subtarget->hasDivide()) return false; if (Subtarget->hasDivideInThumbMode())
return false;
// Otherwise emit a libcall. // Otherwise emit a libcall.
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
if (VT == MVT::i8) if (VT == MVT::i8)
LC = isSigned ? RTLIB::SDIV_I8 : RTLIB::UDIV_I8; LC = isSigned ? RTLIB::SDIV_I8 : RTLIB::UDIV_I8;
else if (VT == MVT::i16) else if (VT == MVT::i16)
LC = isSigned ? RTLIB::SDIV_I16 : RTLIB::UDIV_I16; LC = isSigned ? RTLIB::SDIV_I16 : RTLIB::UDIV_I16;
else if (VT == MVT::i32) else if (VT == MVT::i32)
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lib/Target/ARM/ARMISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 846 Lines • ▼ Show 20 LinesARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
// implementation-specific ways of obtaining this information. // implementation-specific ways of obtaining this information.
if (Subtarget->hasPerfMon()) if (Subtarget->hasPerfMon())
setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom); setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
// Only ARMv6 has BSWAP. // Only ARMv6 has BSWAP.
if (!Subtarget->hasV6Ops()) if (!Subtarget->hasV6Ops())
setOperationAction(ISD::BSWAP, MVT::i32, Expand); setOperationAction(ISD::BSWAP, MVT::i32, Expand);
bool hasDivide = Subtarget->isThumb() ? Subtarget->hasDivide() bool hasDivide = Subtarget->isThumb() ? Subtarget->hasDivideInThumbMode()
: Subtarget->hasDivideInARMMode(); : Subtarget->hasDivideInARMMode();
if (!hasDivide) { if (!hasDivide) {
// These are expanded into libcalls if the cpu doesn't have HW divider. // These are expanded into libcalls if the cpu doesn't have HW divider.
setOperationAction(ISD::SDIV, MVT::i32, LibCall); setOperationAction(ISD::SDIV, MVT::i32, LibCall);
setOperationAction(ISD::UDIV, MVT::i32, LibCall); setOperationAction(ISD::UDIV, MVT::i32, LibCall);
} }
if (Subtarget->isTargetWindows() && !Subtarget->hasDivide()) { if (Subtarget->isTargetWindows() && !Subtarget->hasDivideInThumbMode()) {
setOperationAction(ISD::SDIV, MVT::i32, Custom); setOperationAction(ISD::SDIV, MVT::i32, Custom);
setOperationAction(ISD::UDIV, MVT::i32, Custom); setOperationAction(ISD::UDIV, MVT::i32, Custom);
setOperationAction(ISD::SDIV, MVT::i64, Custom); setOperationAction(ISD::SDIV, MVT::i64, Custom);
setOperationAction(ISD::UDIV, MVT::i64, Custom); setOperationAction(ISD::UDIV, MVT::i64, Custom);
} }
setOperationAction(ISD::SREM, MVT::i32, Expand); setOperationAction(ISD::SREM, MVT::i32, Expand);
▲ Show 20 Lines • Show All 12,175 Lines • ▼ Show 20 LinesSDValue ARMTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
Type *Ty = VT.getTypeForEVT(*DAG.getContext()); Type *Ty = VT.getTypeForEVT(*DAG.getContext());
SDLoc dl(Op); SDLoc dl(Op);
// If the target has hardware divide, use divide + multiply + subtract: // If the target has hardware divide, use divide + multiply + subtract:
// div = a / b // div = a / b
// rem = a - b * div // rem = a - b * div
// return {div, rem} // return {div, rem}
// This should be lowered into UDIV/SDIV + MLS later on. // This should be lowered into UDIV/SDIV + MLS later on.
bool hasDivide = Subtarget->isThumb() ? Subtarget->hasDivide() bool hasDivide = Subtarget->isThumb() ? Subtarget->hasDivideInThumbMode()
: Subtarget->hasDivideInARMMode(); : Subtarget->hasDivideInARMMode();
if (hasDivide && Op->getValueType(0).isSimple() && if (hasDivide && Op->getValueType(0).isSimple() &&
Op->getSimpleValueType(0) == MVT::i32) { Op->getSimpleValueType(0) == MVT::i32) {
unsigned DivOpcode = isSigned ? ISD::SDIV : ISD::UDIV; unsigned DivOpcode = isSigned ? ISD::SDIV : ISD::UDIV;
const SDValue Dividend = Op->getOperand(0); const SDValue Dividend = Op->getOperand(0);
const SDValue Divisor = Op->getOperand(1); const SDValue Divisor = Op->getOperand(1);
SDValue Div = DAG.getNode(DivOpcode, dl, VT, Dividend, Divisor); SDValue Div = DAG.getNode(DivOpcode, dl, VT, Dividend, Divisor);
SDValue Mul = DAG.getNode(ISD::MUL, dl, VT, Div, Divisor); SDValue Mul = DAG.getNode(ISD::MUL, dl, VT, Div, Divisor);
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lib/Target/ARM/ARMInstrInfo.td

Show First 20 Lines • Show All 253 Lines • ▼ Show 20 Lines
def HasCRC : Predicate<"Subtarget->hasCRC()">, def HasCRC : Predicate<"Subtarget->hasCRC()">,
AssemblerPredicate<"FeatureCRC", "crc">; AssemblerPredicate<"FeatureCRC", "crc">;
def HasRAS : Predicate<"Subtarget->hasRAS()">, def HasRAS : Predicate<"Subtarget->hasRAS()">,
AssemblerPredicate<"FeatureRAS", "ras">; AssemblerPredicate<"FeatureRAS", "ras">;
def HasFP16 : Predicate<"Subtarget->hasFP16()">, def HasFP16 : Predicate<"Subtarget->hasFP16()">,
AssemblerPredicate<"FeatureFP16","half-float conversions">; AssemblerPredicate<"FeatureFP16","half-float conversions">;
def HasFullFP16 : Predicate<"Subtarget->hasFullFP16()">, def HasFullFP16 : Predicate<"Subtarget->hasFullFP16()">,
AssemblerPredicate<"FeatureFullFP16","full half-float">; AssemblerPredicate<"FeatureFullFP16","full half-float">;
def HasDivide : Predicate<"Subtarget->hasDivide()">, def HasDivideInThumb : Predicate<"Subtarget->hasDivideInThumbMode()">,
AssemblerPredicate<"FeatureHWDiv", "divide in THUMB">; AssemblerPredicate<"FeatureHWDivThumb", "divide in THUMB">;
def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">, def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">,
AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">; AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">;
def HasDSP : Predicate<"Subtarget->hasDSP()">, def HasDSP : Predicate<"Subtarget->hasDSP()">,
AssemblerPredicate<"FeatureDSP", "dsp">; AssemblerPredicate<"FeatureDSP", "dsp">;
def HasDB : Predicate<"Subtarget->hasDataBarrier()">, def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
AssemblerPredicate<"FeatureDB", AssemblerPredicate<"FeatureDB",
"data-barriers">; "data-barriers">;
def HasV7Clrex : Predicate<"Subtarget->hasV7Clrex()">, def HasV7Clrex : Predicate<"Subtarget->hasV7Clrex()">,
▲ Show 20 Lines • Show All 5,706 Lines • Show Last 20 Lines

lib/Target/ARM/ARMInstrThumb2.td

Show First 20 Lines • Show All 2,791 Lines • ▼ Show 20 Lines
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Division Instructions. // Division Instructions.
// Signed and unsigned division on v7-M // Signed and unsigned division on v7-M
// //
def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV, def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV,
"sdiv", "\t$Rd, $Rn, $Rm", "sdiv", "\t$Rd, $Rn, $Rm",
[(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>, [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
Requires<[HasDivide, IsThumb, HasV8MBaseline]>, Requires<[HasDivideInThumb, IsThumb, HasV8MBaseline]>,
Sched<[WriteDIV]> { Sched<[WriteDIV]> {
let Inst{31-27} = 0b11111; let Inst{31-27} = 0b11111;
let Inst{26-21} = 0b011100; let Inst{26-21} = 0b011100;
let Inst{20} = 0b1; let Inst{20} = 0b1;
let Inst{15-12} = 0b1111; let Inst{15-12} = 0b1111;
let Inst{7-4} = 0b1111; let Inst{7-4} = 0b1111;
} }
def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV, def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV,
"udiv", "\t$Rd, $Rn, $Rm", "udiv", "\t$Rd, $Rn, $Rm",
[(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>, [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
Requires<[HasDivide, IsThumb, HasV8MBaseline]>, Requires<[HasDivideInThumb, IsThumb, HasV8MBaseline]>,
Sched<[WriteDIV]> { Sched<[WriteDIV]> {
let Inst{31-27} = 0b11111; let Inst{31-27} = 0b11111;
let Inst{26-21} = 0b011101; let Inst{26-21} = 0b011101;
let Inst{20} = 0b1; let Inst{20} = 0b1;
let Inst{15-12} = 0b1111; let Inst{15-12} = 0b1111;
let Inst{7-4} = 0b1111; let Inst{7-4} = 0b1111;
} }
▲ Show 20 Lines • Show All 1,903 Lines • Show Last 20 Lines

lib/Target/ARM/ARMSubtarget.h

Show First 20 Lines • Show All 202 Lines • ▼ Show 20 Linesprotected:
/// HasFullFP16 - True if subtarget supports half-precision FP operations /// HasFullFP16 - True if subtarget supports half-precision FP operations
bool HasFullFP16 = false; bool HasFullFP16 = false;
/// HasD16 - True if subtarget is limited to 16 double precision /// HasD16 - True if subtarget is limited to 16 double precision
/// FP registers for VFPv3. /// FP registers for VFPv3.
bool HasD16 = false; bool HasD16 = false;
/// HasHardwareDivide - True if subtarget supports [su]div /// HasHardwareDivide - True if subtarget supports [su]div in Thumb mode
bool HasHardwareDivide = false; bool HasHardwareDivideInThumb = false;
/// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
bool HasHardwareDivideInARM = false; bool HasHardwareDivideInARM = false;
/// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
/// instructions. /// instructions.
bool HasDataBarrier = false; bool HasDataBarrier = false;
▲ Show 20 Lines • Show All 281 Lines • ▼ Show 20 Linespublic:
bool hasCRC() const { return HasCRC; } bool hasCRC() const { return HasCRC; }
bool hasRAS() const { return HasRAS; } bool hasRAS() const { return HasRAS; }
bool hasVirtualization() const { return HasVirtualization; } bool hasVirtualization() const { return HasVirtualization; }
bool useNEONForSinglePrecisionFP() const { bool useNEONForSinglePrecisionFP() const {
return hasNEON() && UseNEONForSinglePrecisionFP; return hasNEON() && UseNEONForSinglePrecisionFP;
} }
bool hasDivide() const { return HasHardwareDivide; } bool hasDivideInThumbMode() const { return HasHardwareDivideInThumb; }
bool hasDivideInARMMode() const { return HasHardwareDivideInARM; } bool hasDivideInARMMode() const { return HasHardwareDivideInARM; }
bool hasDataBarrier() const { return HasDataBarrier; } bool hasDataBarrier() const { return HasDataBarrier; }
bool hasV7Clrex() const { return HasV7Clrex; } bool hasV7Clrex() const { return HasV7Clrex; }
bool hasAcquireRelease() const { return HasAcquireRelease; } bool hasAcquireRelease() const { return HasAcquireRelease; }
bool hasAnyDataBarrier() const { bool hasAnyDataBarrier() const {
return HasDataBarrier || (hasV6Ops() && !isThumb()); return HasDataBarrier || (hasV6Ops() && !isThumb());
} }
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lib/Target/ARM/AsmParser/ARMAsmParser.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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const unsigned Kind; const unsigned Kind;
const uint64_t ArchCheck; const uint64_t ArchCheck;
const FeatureBitset Features; const FeatureBitset Features;
} Extensions[] = { } Extensions[] = {
{ ARM::AEK_CRC, Feature_HasV8, {ARM::FeatureCRC} }, { ARM::AEK_CRC, Feature_HasV8, {ARM::FeatureCRC} },
{ ARM::AEK_CRYPTO, Feature_HasV8, { ARM::AEK_CRYPTO, Feature_HasV8,
{ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8} }, {ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8} },
{ ARM::AEK_FP, Feature_HasV8, {ARM::FeatureFPARMv8} }, { ARM::AEK_FP, Feature_HasV8, {ARM::FeatureFPARMv8} },
{ (ARM::AEK_HWDIV | ARM::AEK_HWDIVARM), Feature_HasV7 | Feature_IsNotMClass, { (ARM::AEK_HWDIVTHUMB | ARM::AEK_HWDIVARM), Feature_HasV7 | Feature_IsNotMClass,
{ARM::FeatureHWDiv, ARM::FeatureHWDivARM} }, {ARM::FeatureHWDivThumb, ARM::FeatureHWDivARM} },
{ ARM::AEK_MP, Feature_HasV7 | Feature_IsNotMClass, {ARM::FeatureMP} }, { ARM::AEK_MP, Feature_HasV7 | Feature_IsNotMClass, {ARM::FeatureMP} },
{ ARM::AEK_SIMD, Feature_HasV8, {ARM::FeatureNEON, ARM::FeatureFPARMv8} }, { ARM::AEK_SIMD, Feature_HasV8, {ARM::FeatureNEON, ARM::FeatureFPARMv8} },
{ ARM::AEK_SEC, Feature_HasV6K, {ARM::FeatureTrustZone} }, { ARM::AEK_SEC, Feature_HasV6K, {ARM::FeatureTrustZone} },
// FIXME: Only available in A-class, isel not predicated // FIXME: Only available in A-class, isel not predicated
{ ARM::AEK_VIRT, Feature_HasV7, {ARM::FeatureVirtualization} }, { ARM::AEK_VIRT, Feature_HasV7, {ARM::FeatureVirtualization} },
{ ARM::AEK_FP16, Feature_HasV8_2a, {ARM::FeatureFPARMv8, ARM::FeatureFullFP16} }, { ARM::AEK_FP16, Feature_HasV8_2a, {ARM::FeatureFPARMv8, ARM::FeatureFullFP16} },
{ ARM::AEK_RAS, Feature_HasV8, {ARM::FeatureRAS} }, { ARM::AEK_RAS, Feature_HasV8, {ARM::FeatureRAS} },
// FIXME: Unsupported extensions. // FIXME: Unsupported extensions.
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unittests/Support/TargetParserTest.cpp

Show First 20 Lines • Show All 143 Lines • ▼ Show 20 Lines EXPECT_TRUE(testARMCPU("cortex-m0plus", "armv6-m", "none",
ARM::AEK_NONE, "6-M")); ARM::AEK_NONE, "6-M"));
EXPECT_TRUE(testARMCPU("cortex-m1", "armv6-m", "none", EXPECT_TRUE(testARMCPU("cortex-m1", "armv6-m", "none",
ARM::AEK_NONE, "6-M")); ARM::AEK_NONE, "6-M"));
EXPECT_TRUE(testARMCPU("sc000", "armv6-m", "none", EXPECT_TRUE(testARMCPU("sc000", "armv6-m", "none",
ARM::AEK_NONE, "6-M")); ARM::AEK_NONE, "6-M"));
EXPECT_TRUE(testARMCPU("cortex-a5", "armv7-a", "neon-vfpv4", EXPECT_TRUE(testARMCPU("cortex-a5", "armv7-a", "neon-vfpv4",
ARM::AEK_MP | ARM::AEK_SEC | ARM::AEK_DSP, "7-A")); ARM::AEK_MP | ARM::AEK_SEC | ARM::AEK_DSP, "7-A"));
EXPECT_TRUE(testARMCPU("cortex-a7", "armv7-a", "neon-vfpv4", EXPECT_TRUE(testARMCPU("cortex-a7", "armv7-a", "neon-vfpv4",
ARM::AEK_HWDIV | ARM::AEK_HWDIVARM | ARM::AEK_MP | ARM::AEK_HWDIVTHUMB | ARM::AEK_HWDIVARM | ARM::AEK_MP |
ARM::AEK_SEC | ARM::AEK_VIRT | ARM::AEK_DSP, ARM::AEK_SEC | ARM::AEK_VIRT | ARM::AEK_DSP,
"7-A")); "7-A"));
EXPECT_TRUE(testARMCPU("cortex-a8", "armv7-a", "neon", EXPECT_TRUE(testARMCPU("cortex-a8", "armv7-a", "neon",
ARM::AEK_SEC | ARM::AEK_DSP, "7-A")); ARM::AEK_SEC | ARM::AEK_DSP, "7-A"));
EXPECT_TRUE(testARMCPU("cortex-a9", "armv7-a", "neon-fp16", EXPECT_TRUE(testARMCPU("cortex-a9", "armv7-a", "neon-fp16",
ARM::AEK_MP | ARM::AEK_SEC | ARM::AEK_DSP, "7-A")); ARM::AEK_MP | ARM::AEK_SEC | ARM::AEK_DSP, "7-A"));
EXPECT_TRUE(testARMCPU("cortex-a12", "armv7-a", "neon-vfpv4", EXPECT_TRUE(testARMCPU("cortex-a12", "armv7-a", "neon-vfpv4",
ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT |
ARM::AEK_HWDIVARM | ARM::AEK_HWDIV | ARM::AEK_DSP, ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
ARM::AEK_DSP,
"7-A")); "7-A"));
EXPECT_TRUE(testARMCPU("cortex-a15", "armv7-a", "neon-vfpv4", EXPECT_TRUE(testARMCPU("cortex-a15", "armv7-a", "neon-vfpv4",
ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT |
ARM::AEK_HWDIVARM | ARM::AEK_HWDIV | ARM::AEK_DSP, ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
ARM::AEK_DSP,
"7-A")); "7-A"));
EXPECT_TRUE(testARMCPU("cortex-a17", "armv7-a", "neon-vfpv4", EXPECT_TRUE(testARMCPU("cortex-a17", "armv7-a", "neon-vfpv4",
ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT |
ARM::AEK_HWDIVARM | ARM::AEK_HWDIV | ARM::AEK_DSP, ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
ARM::AEK_DSP,
"7-A")); "7-A"));
EXPECT_TRUE(testARMCPU("krait", "armv7-a", "neon-vfpv4", EXPECT_TRUE(testARMCPU("krait", "armv7-a", "neon-vfpv4",
ARM::AEK_HWDIVARM | ARM::AEK_HWDIV | ARM::AEK_DSP, ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
"7-A")); "7-A"));
EXPECT_TRUE(testARMCPU("cortex-r4", "armv7-r", "none", EXPECT_TRUE(testARMCPU("cortex-r4", "armv7-r", "none",
ARM::AEK_HWDIV | ARM::AEK_DSP, "7-R")); ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP, "7-R"));
EXPECT_TRUE(testARMCPU("cortex-r4f", "armv7-r", "vfpv3-d16", EXPECT_TRUE(testARMCPU("cortex-r4f", "armv7-r", "vfpv3-d16",
ARM::AEK_HWDIV | ARM::AEK_DSP, "7-R")); ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP, "7-R"));
EXPECT_TRUE(testARMCPU("cortex-r5", "armv7-r", "vfpv3-d16", EXPECT_TRUE(testARMCPU("cortex-r5", "armv7-r", "vfpv3-d16",
ARM::AEK_MP | ARM::AEK_HWDIVARM | ARM::AEK_HWDIV | ARM::AEK_MP | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
ARM::AEK_DSP, "7-R")); ARM::AEK_DSP,
"7-R"));
EXPECT_TRUE(testARMCPU("cortex-r7", "armv7-r", "vfpv3-d16-fp16", EXPECT_TRUE(testARMCPU("cortex-r7", "armv7-r", "vfpv3-d16-fp16",
ARM::AEK_MP | ARM::AEK_HWDIVARM | ARM::AEK_HWDIV | ARM::AEK_MP | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
ARM::AEK_DSP, "7-R")); ARM::AEK_DSP,
"7-R"));
EXPECT_TRUE(testARMCPU("cortex-r8", "armv7-r", "vfpv3-d16-fp16", EXPECT_TRUE(testARMCPU("cortex-r8", "armv7-r", "vfpv3-d16-fp16",
ARM::AEK_MP | ARM::AEK_HWDIVARM | ARM::AEK_HWDIV | ARM::AEK_MP | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
ARM::AEK_DSP, "7-R")); ARM::AEK_DSP,
"7-R"));
EXPECT_TRUE(testARMCPU("cortex-r52", "armv8-r", "neon-fp-armv8", EXPECT_TRUE(testARMCPU("cortex-r52", "armv8-r", "neon-fp-armv8",
ARM::AEK_CRC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_CRC | ARM::AEK_MP | ARM::AEK_VIRT |
ARM::AEK_HWDIVARM | ARM::AEK_HWDIV | ARM::AEK_DSP, ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
ARM::AEK_DSP,
"8-R")); "8-R"));
EXPECT_TRUE(testARMCPU("sc300", "armv7-m", "none", EXPECT_TRUE(
ARM::AEK_HWDIV, "7-M")); testARMCPU("sc300", "armv7-m", "none", ARM::AEK_HWDIVTHUMB, "7-M"));
EXPECT_TRUE(testARMCPU("cortex-m3", "armv7-m", "none", EXPECT_TRUE(
ARM::AEK_HWDIV, "7-M")); testARMCPU("cortex-m3", "armv7-m", "none", ARM::AEK_HWDIVTHUMB, "7-M"));
EXPECT_TRUE(testARMCPU("cortex-m4", "armv7e-m", "fpv4-sp-d16", EXPECT_TRUE(testARMCPU("cortex-m4", "armv7e-m", "fpv4-sp-d16",
ARM::AEK_HWDIV | ARM::AEK_DSP, "7E-M")); ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP, "7E-M"));
EXPECT_TRUE(testARMCPU("cortex-m7", "armv7e-m", "fpv5-d16", EXPECT_TRUE(testARMCPU("cortex-m7", "armv7e-m", "fpv5-d16",
ARM::AEK_HWDIV | ARM::AEK_DSP, "7E-M")); ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP, "7E-M"));
EXPECT_TRUE(testARMCPU("cortex-a32", "armv8-a", "crypto-neon-fp-armv8", EXPECT_TRUE(testARMCPU("cortex-a32", "armv8-a", "crypto-neon-fp-armv8",
ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
ARM::AEK_HWDIV | ARM::AEK_DSP, ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
"8-A")); "8-A"));
EXPECT_TRUE(testARMCPU("cortex-a35", "armv8-a", "crypto-neon-fp-armv8", EXPECT_TRUE(testARMCPU("cortex-a35", "armv8-a", "crypto-neon-fp-armv8",
ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
ARM::AEK_HWDIV | ARM::AEK_DSP, ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
"8-A")); "8-A"));
EXPECT_TRUE(testARMCPU("cortex-a53", "armv8-a", "crypto-neon-fp-armv8", EXPECT_TRUE(testARMCPU("cortex-a53", "armv8-a", "crypto-neon-fp-armv8",
ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
ARM::AEK_HWDIV | ARM::AEK_DSP, ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
"8-A")); "8-A"));
EXPECT_TRUE(testARMCPU("cortex-a57", "armv8-a", "crypto-neon-fp-armv8", EXPECT_TRUE(testARMCPU("cortex-a57", "armv8-a", "crypto-neon-fp-armv8",
ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
ARM::AEK_HWDIV | ARM::AEK_DSP, ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
"8-A")); "8-A"));
EXPECT_TRUE(testARMCPU("cortex-a72", "armv8-a", "crypto-neon-fp-armv8", EXPECT_TRUE(testARMCPU("cortex-a72", "armv8-a", "crypto-neon-fp-armv8",
ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
ARM::AEK_HWDIV | ARM::AEK_DSP, ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
"8-A")); "8-A"));
EXPECT_TRUE(testARMCPU("cortex-a73", "armv8-a", "crypto-neon-fp-armv8", EXPECT_TRUE(testARMCPU("cortex-a73", "armv8-a", "crypto-neon-fp-armv8",
ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
ARM::AEK_HWDIV | ARM::AEK_DSP, ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
"8-A")); "8-A"));
EXPECT_TRUE(testARMCPU("cyclone", "armv8-a", "crypto-neon-fp-armv8", EXPECT_TRUE(testARMCPU("cyclone", "armv8-a", "crypto-neon-fp-armv8",
ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
ARM::AEK_HWDIV | ARM::AEK_DSP, ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
"8-A")); "8-A"));
EXPECT_TRUE(testARMCPU("exynos-m1", "armv8-a", "crypto-neon-fp-armv8", EXPECT_TRUE(testARMCPU("exynos-m1", "armv8-a", "crypto-neon-fp-armv8",
ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
ARM::AEK_HWDIV | ARM::AEK_DSP, ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
"8-A")); "8-A"));
EXPECT_TRUE(testARMCPU("exynos-m2", "armv8-a", "crypto-neon-fp-armv8", EXPECT_TRUE(testARMCPU("exynos-m2", "armv8-a", "crypto-neon-fp-armv8",
ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
ARM::AEK_HWDIV | ARM::AEK_DSP, ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
"8-A")); "8-A"));
EXPECT_TRUE(testARMCPU("exynos-m3", "armv8-a", "crypto-neon-fp-armv8", EXPECT_TRUE(testARMCPU("exynos-m3", "armv8-a", "crypto-neon-fp-armv8",
ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
ARM::AEK_HWDIV | ARM::AEK_DSP, ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
"8-A")); "8-A"));
EXPECT_TRUE(testARMCPU("cortex-m23", "armv8-m.base", "none", EXPECT_TRUE(testARMCPU("cortex-m23", "armv8-m.base", "none",
ARM::AEK_HWDIV, "8-M.Baseline")); ARM::AEK_HWDIVTHUMB, "8-M.Baseline"));
EXPECT_TRUE(testARMCPU("cortex-m33", "armv8-m.main", "fpv5-sp-d16", EXPECT_TRUE(testARMCPU("cortex-m33", "armv8-m.main", "fpv5-sp-d16",
ARM::AEK_HWDIV | ARM::AEK_DSP, "8-M.Mainline")); ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP, "8-M.Mainline"));
EXPECT_TRUE(testARMCPU("iwmmxt", "iwmmxt", "none", EXPECT_TRUE(testARMCPU("iwmmxt", "iwmmxt", "none",
ARM::AEK_NONE, "iwmmxt")); ARM::AEK_NONE, "iwmmxt"));
EXPECT_TRUE(testARMCPU("xscale", "xscale", "none", EXPECT_TRUE(testARMCPU("xscale", "xscale", "none",
ARM::AEK_NONE, "xscale")); ARM::AEK_NONE, "xscale"));
EXPECT_TRUE(testARMCPU("swift", "armv7s", "neon-vfpv4", EXPECT_TRUE(testARMCPU("swift", "armv7s", "neon-vfpv4",
ARM::AEK_HWDIVARM | ARM::AEK_HWDIV | ARM::AEK_DSP, ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
"7-S")); "7-S"));
} }
bool testARMArch(StringRef Arch, StringRef DefaultCPU, StringRef SubArch, bool testARMArch(StringRef Arch, StringRef DefaultCPU, StringRef SubArch,
unsigned ArchAttr) { unsigned ArchAttr) {
unsigned ArchKind = ARM::parseArch(Arch); unsigned ArchKind = ARM::parseArch(Arch);
return (ArchKind != ARM::AK_INVALID) & return (ArchKind != ARM::AK_INVALID) &
ARM::getDefaultCPU(Arch).equals(DefaultCPU) & ARM::getDefaultCPU(Arch).equals(DefaultCPU) &
▲ Show 20 Lines • Show All 182 Lines • ▼ Show 20 Lines if (FK == ARM::FK_LAST)
EXPECT_EQ(0U, ARM::getFPURestriction(FK)); EXPECT_EQ(0U, ARM::getFPURestriction(FK));
else else
EXPECT_LE(0U, ARM::getFPURestriction(FK)); EXPECT_LE(0U, ARM::getFPURestriction(FK));
} }
TEST(TargetParserTest, ARMExtensionFeatures) { TEST(TargetParserTest, ARMExtensionFeatures) {
std::vector<StringRef> Features; std::vector<StringRef> Features;
unsigned Extensions = ARM::AEK_CRC | ARM::AEK_CRYPTO | ARM::AEK_DSP | unsigned Extensions = ARM::AEK_CRC | ARM::AEK_CRYPTO | ARM::AEK_DSP |
ARM::AEK_HWDIVARM | ARM::AEK_HWDIV | ARM::AEK_MP | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_MP |
ARM::AEK_SEC | ARM::AEK_VIRT | ARM::AEK_RAS; ARM::AEK_SEC | ARM::AEK_VIRT | ARM::AEK_RAS;
for (unsigned i = 0; i <= Extensions; i++) for (unsigned i = 0; i <= Extensions; i++)
EXPECT_TRUE(i == 0 ? !ARM::getExtensionFeatures(i, Features) EXPECT_TRUE(i == 0 ? !ARM::getExtensionFeatures(i, Features)
: ARM::getExtensionFeatures(i, Features)); : ARM::getExtensionFeatures(i, Features));
} }
TEST(TargetParserTest, ARMFPUFeatures) { TEST(TargetParserTest, ARMFPUFeatures) {
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