AMDGPU/GFX9: Add AsmPrinter support for aperture registers

[arsenm]

lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

2453

We have a dedicated feature for the aperture registers

lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

bool isSCSrcV2B16() const {
     return isSCSrcB16();
   }
 
   bool isSCSrcB32() const {
     return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::i32);
   }
 
   bool isSCSrcB64() const {
-    return isRegOrInlineNoMods(AMDGPU::SReg_64_WITH_SUBREGSRegClassID,
-                               MVT::i64);
+    return isRegOrInlineNoMods(AMDGPU::SReg_64RegClassID, MVT::i64);
   }
 
   bool isSCSrcF16() const {
     return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::f16);
   }
 
   bool isSCSrcV2F16() const {
     return isSCSrcF16();
   }
 
   bool isSCSrcF32() const {
     return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::f32);
   }
 
   bool isSCSrcF64() const {
-    return isRegOrInlineNoMods(AMDGPU::SReg_64_WITH_SUBREGSRegClassID,
-                               MVT::f64);
+    return isRegOrInlineNoMods(AMDGPU::SReg_64RegClassID, MVT::f64);
   }
 
   bool isSSrcB32() const {
     return isSCSrcB32() || isLiteralImm(MVT::i32) || isExpr();
   }
 
   bool isSSrcB16() const {
     return isSCSrcB16() || isLiteralImm(MVT::i16);
public:
   bool isCI() const {
     return AMDGPU::isCI(getSTI());
   }
 
   bool isVI() const {
     return AMDGPU::isVI(getSTI());
   }
 
+  bool isGFX9() const {
+    return AMDGPU::isGFX9(getSTI());
+  }
+
   bool hasInv2PiInlineImm() const {
     return getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm];
   }
 
   bool hasSGPR102_SGPR103() const {
     return !isVI();
   }
 
return StringSwitch<unsigned>(RegName)
     .Case("vcc_lo", AMDGPU::VCC_LO)
     .Case("vcc_hi", AMDGPU::VCC_HI)
     .Case("exec_lo", AMDGPU::EXEC_LO)
     .Case("exec_hi", AMDGPU::EXEC_HI)
     .Case("tma_lo", AMDGPU::TMA_LO)
     .Case("tma_hi", AMDGPU::TMA_HI)
     .Case("tba_lo", AMDGPU::TBA_LO)
     .Case("tba_hi", AMDGPU::TBA_HI)
+    .Case("src_shared_base", AMDGPU::SRC_SHARED_BASE)
+    .Case("src_shared_limit", AMDGPU::SRC_SHARED_LIMIT)
+    .Case("src_private_base", AMDGPU::SRC_PRIVATE_BASE)
+    .Case("src_private_limit", AMDGPU::SRC_PRIVATE_LIMIT)
     .Default(0);
 }
 
 bool AMDGPUAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
                                     SMLoc &EndLoc) {
   auto R = parseRegister();
   if (!R) return true;
   assert(R->isReg());
bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) {
   if (IDVal == ".hsarodata_readonly_agent")
     return ParseSectionDirectiveHSARodataReadonlyAgent();
 
   return true;
 }
 
 bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI,
                                            unsigned RegNo) const {
+  if (!isGFX9()) {
+    switch (RegNo) {
+    case AMDGPU::SRC_SHARED_BASE:
+    case AMDGPU::SRC_SHARED_LIMIT:
+    case AMDGPU::SRC_PRIVATE_BASE:
+    case AMDGPU::SRC_PRIVATE_LIMIT:
+      return false;
+    }
+  }
+
   if (isCI())
     return true;
 
   if (isSI()) {
     // No flat_scr
     switch (RegNo) {
     case AMDGPU::FLAT_SCR:
     case AMDGPU::FLAT_SCR_LO:

lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

 unsigned getInitialPSInputAddr(const Function &F);
 
 bool isShader(CallingConv::ID cc);
 bool isCompute(CallingConv::ID cc);
 
 bool isSI(const MCSubtargetInfo &STI);
 bool isCI(const MCSubtargetInfo &STI);
 bool isVI(const MCSubtargetInfo &STI);
+bool isGFX9(const MCSubtargetInfo &STI);
 
 /// If \p Reg is a pseudo reg, return the correct hardware register given
 /// \p STI otherwise return \p Reg.
 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
 
 /// \brief Convert hardware register \p Reg to a pseudo register
 LLVM_READNONE
 unsigned mc2PseudoReg(unsigned Reg);

lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

 bool isCI(const MCSubtargetInfo &STI) {
   return STI.getFeatureBits()[AMDGPU::FeatureSeaIslands];
 }
 
 bool isVI(const MCSubtargetInfo &STI) {
   return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
 }
 
+bool isGFX9(const MCSubtargetInfo &STI) {
+  return STI.getFeatureBits()[AMDGPU::FeatureGFX9];
+}
+
 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI) {
 
   switch(Reg) {
   default: break;
   case AMDGPU::FLAT_SCR:
     assert(!isSI(STI));
     return isCI(STI) ? AMDGPU::FLAT_SCR_ci : AMDGPU::FLAT_SCR_vi;
 

test/MC/AMDGPU/aperture-regs.s

+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx800 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX8 %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck --check-prefix=GFX9 %s
+
+// GFX8: error: not a valid operand.
+// GFX9: s_mov_b64 s[0:1], src_shared_base ; encoding: [0xeb,0x01,0x80,0xbe]
+s_mov_b64 s[0:1], src_shared_base
+
+// GFX8: error: not a valid operand.
+// GFX9: s_mov_b64 s[2:3], src_shared_limit ; encoding: [0xec,0x01,0x82,0xbe]
+s_mov_b64 s[2:3], src_shared_limit
+
+// GFX8: error: not a valid operand.
+// GFX9: s_mov_b64 s[4:5], src_private_base ; encoding: [0xed,0x01,0x84,0xbe]
+s_mov_b64 s[4:5], src_private_base
+
+// GFX8: error: not a valid operand.
+// GFX9: s_mov_b64 s[6:7], src_private_limit ; encoding: [0xee,0x01,0x86,0xbe]
+s_mov_b64 s[6:7], src_private_limit