AMDGPU: Minor SReg64 register class refactoring

[kzhuravl]

Summary

• Introduce register class for SReg_64 with subregisters
• Introduce register class for aperture registers
• Make aperture register class a part of SReg_64 register class

[arsenm]

lib/Target/AMDGPU/SIRegisterInfo.td

133

Aren't these 32bit only, so i32?

306

It would be less annoying to keep this with the same name and to rename the other one

313

This is adding 32-bit registers to the 64-bit register class?

315

The set with the aperture regs should be unallocatable

[arsenm]

I think this requires changing the register class for SSrc_32/VSrc_32 to be the one that includes the special 32-bit regs. I think I started doing this to start supporting vccz and the other special 1-bit inputs

[kzhuravl]

In D31872#722575, @arsenm wrote:

I think this requires changing the register class for SSrc_32/VSrc_32 to be the one that includes the special 32-bit regs. I think I started doing this to start supporting vccz and the other special 1-bit inputs

I do not think so. src_*_base and src_*_limit are 64 bit inline constants. Here is an example of src_shared_base:

{SMB.shared_base[15:0], 48’h000000000000}

src_*_base and src_*_limit also do not have subregisters.

lib/Target/AMDGPU/SIRegisterInfo.td

133

Aperture registers are 64 bit inline constants.

306

Which one?

313

Those are 64 bit inline constants, hence in 64 bit register class.

315

APERTURE_REGS is let isAllocatable = 0.

[arsenm]

In D31872#723085, @kzhuravl wrote:

In D31872#722575, @arsenm wrote:

I think this requires changing the register class for SSrc_32/VSrc_32 to be the one that includes the special 32-bit regs. I think I started doing this to start supporting vccz and the other special 1-bit inputs

I do not think so. src_*_base and src_*_limit are 64 bit inline constants. Here is an example of src_shared_base:

{SMB.shared_base[15:0], 48’h000000000000}

src_*_base and src_*_limit also do not have subregisters.

According to the manual it says if used with a 32-bit input, the 32 LSBs are used, so I guess it has sub0 but not sub1

[arsenm]

lib/Target/AMDGPU/SIRegisterInfo.td

306

I mean SReg_64 remains as it is and add SReg_64_WithApertureRegs or something

315

The class containing it also needs to be unallocatable (so having the allocation priority set also doesn't make sense)

[arsenm]

While you're working on this, can you implement TargetRegisterInfo::isConstantPhysReg for these?

[kzhuravl]

In D31872#723109, @arsenm wrote:

While you're working on this, can you implement TargetRegisterInfo::isConstantPhysReg for these?

Sure.

lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

for (const MachineInstr &MI : MBB) {
         if (AMDGPU::SReg_32RegClass.contains(reg)) {
           assert(!AMDGPU::TTMP_32RegClass.contains(reg) &&
                  "trap handler registers should not be used");
           isSGPR = true;
           width = 1;
         } else if (AMDGPU::VGPR_32RegClass.contains(reg)) {
           isSGPR = false;
           width = 1;
-        } else if (AMDGPU::SReg_64RegClass.contains(reg)) {
+        } else if (AMDGPU::SReg_64_WITH_SUBREGSRegClass.contains(reg)) {
           assert(!AMDGPU::TTMP_64RegClass.contains(reg) &&
                  "trap handler registers should not be used");
           isSGPR = true;
           width = 2;
         } else if (AMDGPU::VReg_64RegClass.contains(reg)) {
           isSGPR = false;
           width = 2;
         } else if (AMDGPU::VReg_96RegClass.contains(reg)) {

lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

SDNode *AMDGPUDAGToDAGISel::glueCopyToM0(SDNode *N) const {
   return N;
 }
 
 static unsigned selectSGPRVectorRegClassID(unsigned NumVectorElts) {
   switch (NumVectorElts) {
   case 1:
     return AMDGPU::SReg_32_XM0RegClassID;
   case 2:
-    return AMDGPU::SReg_64RegClassID;
+    return AMDGPU::SReg_64_WITH_SUBREGSRegClassID;
   case 4:
     return AMDGPU::SReg_128RegClassID;
   case 8:
     return AMDGPU::SReg_256RegClassID;
   case 16:
     return AMDGPU::SReg_512RegClassID;
   }
 
if (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
       break;
     }
     SDLoc DL(N);
     if (N->getValueType(0) == MVT::i128) {
       RC = CurDAG->getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32);
       SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, DL, MVT::i32);
       SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, DL, MVT::i32);
     } else if (N->getValueType(0) == MVT::i64) {
-      RC = CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32);
+      RC = CurDAG->getTargetConstant(AMDGPU::SReg_64_WITH_SUBREGSRegClassID,
+                                     DL, MVT::i32);
       SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32);
       SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32);
     } else {
       llvm_unreachable("Unhandled value type for BUILD_PAIR");
     }
     const SDValue Ops[] = { RC, N->getOperand(0), SubReg0,
                             N->getOperand(1), SubReg1 };
     ReplaceNode(N, CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL,
case ISD::ConstantFP: {
 
     SDLoc DL(N);
     SDNode *Lo = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
                                 CurDAG->getConstant(Imm & 0xFFFFFFFF, DL,
                                                     MVT::i32));
     SDNode *Hi = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
                                 CurDAG->getConstant(Imm >> 32, DL, MVT::i32));
     const SDValue Ops[] = {
-      CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32),
+      CurDAG->getTargetConstant(AMDGPU::SReg_64_WITH_SUBREGSRegClassID,
+                                DL, MVT::i32),
       SDValue(Lo, 0), CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
       SDValue(Hi, 0), CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32)
     };
 
     ReplaceNode(N, CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL,
                                           N->getValueType(0), Ops));
     return;
   }
void AMDGPUDAGToDAGISel::SelectADD_SUB_I64(SDNode *N) {
   SDValue AddHiArgs[] = {
     SDValue(Hi0, 0),
     SDValue(Hi1, 0),
     SDValue(AddLo, 1)
   };
   SDNode *AddHi = CurDAG->getMachineNode(CarryOpc, DL, VTList, AddHiArgs);
 
   SDValue RegSequenceArgs[] = {
-    CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32),
+    CurDAG->getTargetConstant(AMDGPU::SReg_64_WITH_SUBREGSRegClassID,
+                              DL, MVT::i32),
     SDValue(AddLo,0),
     Sub0,
     SDValue(AddHi,0),
     Sub1,
   };
   SDNode *RegSequence = CurDAG->getMachineNode(AMDGPU::REG_SEQUENCE, DL,
                                                MVT::i64, RegSequenceArgs);
 

lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), I.getOperand(0).getReg())
           .addReg(DstLo)
           .addImm(AMDGPU::sub0)
           .addReg(DstHi)
           .addImm(AMDGPU::sub1);
 
   for (MachineOperand &MO : I.explicit_operands()) {
     if (!MO.isReg() || TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
       continue;
-    RBI.constrainGenericRegister(MO.getReg(), AMDGPU::SReg_64RegClass, MRI);
+    RBI.constrainGenericRegister(MO.getReg(),
+                                 AMDGPU::SReg_64_WITH_SUBREGSRegClass,
+                                 MRI);
   }
 
   I.eraseFromParent();
   return true;
 }
 
 bool AMDGPUInstructionSelector::selectG_GEP(MachineInstr &I) const {
   return selectG_ADD(I);
bool AMDGPUInstructionSelector::selectG_CONSTANT(MachineInstr &I) const {
   BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), DstReg)
           .addReg(LoReg)
           .addImm(AMDGPU::sub0)
           .addReg(HiReg)
           .addImm(AMDGPU::sub1);
   // We can't call constrainSelectedInstRegOperands here, because it doesn't
   // work for target independent opcodes
   I.eraseFromParent();
-  return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_64RegClass, MRI);
+  return RBI.constrainGenericRegister(DstReg,
+                                      AMDGPU::SReg_64_WITH_SUBREGSRegClass,
+                                      MRI);
 }
 
 static bool isConstant(const MachineInstr &MI) {
   return MI.getOpcode() == TargetOpcode::G_CONSTANT;
 }
 
 void AMDGPUInstructionSelector::getAddrModeInfo(const MachineInstr &Load,
     const MachineRegisterInfo &MRI, SmallVectorImpl<GEPInfo> &AddrInfo) const {

lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

bool isSCSrcV2B16() const {
     return isSCSrcB16();
   }
 
   bool isSCSrcB32() const {
     return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::i32);
   }
 
   bool isSCSrcB64() const {
-    return isRegOrInlineNoMods(AMDGPU::SReg_64RegClassID, MVT::i64);
+    return isRegOrInlineNoMods(AMDGPU::SReg_64_WITH_SUBREGSRegClassID,
+                               MVT::i64);
   }
 
   bool isSCSrcF16() const {
     return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::f16);
   }
 
   bool isSCSrcV2F16() const {
     return isSCSrcF16();
   }
 
   bool isSCSrcF32() const {
     return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::f32);
   }
 
   bool isSCSrcF64() const {
-    return isRegOrInlineNoMods(AMDGPU::SReg_64RegClassID, MVT::f64);
+    return isRegOrInlineNoMods(AMDGPU::SReg_64_WITH_SUBREGSRegClassID,
+                               MVT::f64);
   }
 
   bool isSSrcB32() const {
     return isSCSrcB32() || isLiteralImm(MVT::i32) || isExpr();
   }
 
   bool isSSrcB16() const {
     return isSCSrcB16() || isLiteralImm(MVT::i16);

lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const {
   case 107: return createRegOperand(VCC_HI);
   case 108: return createRegOperand(TBA_LO);
   case 109: return createRegOperand(TBA_HI);
   case 110: return createRegOperand(TMA_LO);
   case 111: return createRegOperand(TMA_HI);
   case 124: return createRegOperand(M0);
   case 126: return createRegOperand(EXEC_LO);
   case 127: return createRegOperand(EXEC_HI);
-  case 235: return createRegOperand(SRC_SHARED_BASE);
-  case 236: return createRegOperand(SRC_SHARED_LIMIT);
-  case 237: return createRegOperand(SRC_PRIVATE_BASE);
-  case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
     // TODO: SRC_POPS_EXITING_WAVE_ID
     // ToDo: no support for vccz register
   case 251: break;
     // ToDo: no support for execz register
   case 252: break;
   case 253: return createRegOperand(SCC);
   default: break;
   }
   return errOperand(Val, "unknown operand encoding " + Twine(Val));
 }
 
 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const {
   using namespace AMDGPU;
   switch (Val) {
   case 102: return createRegOperand(getMCReg(FLAT_SCR, STI));
   case 106: return createRegOperand(VCC);
   case 108: return createRegOperand(TBA);
   case 110: return createRegOperand(TMA);
   case 126: return createRegOperand(EXEC);
+  case 235: return createRegOperand(SRC_SHARED_BASE);
+  case 236: return createRegOperand(SRC_SHARED_LIMIT);
+  case 237: return createRegOperand(SRC_PRIVATE_BASE);
+  case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
   default: break;
   }
   return errOperand(Val, "unknown operand encoding " + Twine(Val));
 }
 
 //===----------------------------------------------------------------------===//
 // AMDGPUSymbolizer
 //===----------------------------------------------------------------------===//

lib/Target/AMDGPU/SIISelLowering.cpp

static unsigned findFirstFreeSGPR(CCState &CCInfo) {
   }
   llvm_unreachable("Cannot allocate sgpr");
 }
 
 SITargetLowering::SITargetLowering(const TargetMachine &TM,
                                    const SISubtarget &STI)
     : AMDGPUTargetLowering(TM, STI) {
   addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
-  addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
+  addRegisterClass(MVT::i64, &AMDGPU::SReg_64_WITH_SUBREGSRegClass);
 
   addRegisterClass(MVT::i32, &AMDGPU::SReg_32_XM0RegClass);
   addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass);
 
   addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass);
-  addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);
+  addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64_WITH_SUBREGSRegClass);
   addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);
 
   addRegisterClass(MVT::v2i64, &AMDGPU::SReg_128RegClass);
   addRegisterClass(MVT::v2f64, &AMDGPU::SReg_128RegClass);
 
   addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass);
   addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
 
assert(!Info->hasDispatchPtr() &&
            !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() &&
            !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() &&
            !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() &&
            !Info->hasWorkItemIDZ());
   }
 
   if (Info->hasPrivateMemoryInputPtr()) {
     unsigned PrivateMemoryPtrReg = Info->addPrivateMemoryPtr(*TRI);
-    MF.addLiveIn(PrivateMemoryPtrReg, &AMDGPU::SReg_64RegClass);
+    MF.addLiveIn(PrivateMemoryPtrReg, &AMDGPU::SReg_64_WITH_SUBREGSRegClass);
     CCInfo.AllocateReg(PrivateMemoryPtrReg);
   }
 
   // FIXME: How should these inputs interact with inreg / custom SGPR inputs?
   if (Info->hasPrivateSegmentBuffer()) {
     unsigned PrivateSegmentBufferReg = Info->addPrivateSegmentBuffer(*TRI);
     MF.addLiveIn(PrivateSegmentBufferReg, &AMDGPU::SReg_128RegClass);
     CCInfo.AllocateReg(PrivateSegmentBufferReg);
static MachineBasicBlock::iterator emitLoadM0FromVGPRLoop(
   unsigned InitReg,
   unsigned ResultReg,
   unsigned PhiReg,
   unsigned InitSaveExecReg,
   int Offset,
   bool UseGPRIdxMode) {
   MachineBasicBlock::iterator I = LoopBB.begin();
 
-  unsigned PhiExec = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
-  unsigned NewExec = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
-  unsigned CurrentIdxReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
-  unsigned CondReg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
+  unsigned PhiExec =
+      MRI.createVirtualRegister(&AMDGPU::SReg_64_WITH_SUBREGSRegClass);
+  unsigned NewExec =
+      MRI.createVirtualRegister(&AMDGPU::SReg_64_WITH_SUBREGSRegClass);
+  unsigned CurrentIdxReg =
+      MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
+  unsigned CondReg =
+      MRI.createVirtualRegister(&AMDGPU::SReg_64_WITH_SUBREGSRegClass);
 
   BuildMI(LoopBB, I, DL, TII->get(TargetOpcode::PHI), PhiReg)
     .addReg(InitReg)
     .addMBB(&OrigBB)
     .addReg(ResultReg)
     .addMBB(&LoopBB);
 
   BuildMI(LoopBB, I, DL, TII->get(TargetOpcode::PHI), PhiExec)
static MachineBasicBlock::iterator loadM0FromVGPR(const SIInstrInfo *TII,
                                                   int Offset,
                                                   bool UseGPRIdxMode) {
   MachineFunction *MF = MBB.getParent();
   MachineRegisterInfo &MRI = MF->getRegInfo();
   const DebugLoc &DL = MI.getDebugLoc();
   MachineBasicBlock::iterator I(&MI);
 
   unsigned DstReg = MI.getOperand(0).getReg();
-  unsigned SaveExec = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
-  unsigned TmpExec = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
+  unsigned SaveExec =
+      MRI.createVirtualRegister(&AMDGPU::SReg_64_WITH_SUBREGSRegClass);
+  unsigned TmpExec =
+      MRI.createVirtualRegister(&AMDGPU::SReg_64_WITH_SUBREGSRegClass);
 
   BuildMI(MBB, I, DL, TII->get(TargetOpcode::IMPLICIT_DEF), TmpExec);
 
   // Save the EXEC mask
   BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B64), SaveExec)
     .addReg(AMDGPU::EXEC);
 
   // To insert the loop we need to split the block. Move everything after this
SDValue SITargetLowering::getSegmentAperture(unsigned AS, const SDLoc &DL,
   }
 
   MachineFunction &MF = DAG.getMachineFunction();
   SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
   unsigned UserSGPR = Info->getQueuePtrUserSGPR();
   assert(UserSGPR != AMDGPU::NoRegister);
 
   SDValue QueuePtr = CreateLiveInRegister(
-    DAG, &AMDGPU::SReg_64RegClass, UserSGPR, MVT::i64);
+    DAG, &AMDGPU::SReg_64_WITH_SUBREGSRegClass, UserSGPR, MVT::i64);
 
   // Offset into amd_queue_t for group_segment_aperture_base_hi /
   // private_segment_aperture_base_hi.
   uint32_t StructOffset = (AS == AMDGPUASI.LOCAL_ADDRESS) ? 0x40 : 0x44;
 
   SDValue Ptr = DAG.getNode(ISD::ADD, DL, MVT::i64, QueuePtr,
                             DAG.getConstant(StructOffset, DL, MVT::i64));
 
SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
   EVT VT = Op.getValueType();
   SDLoc DL(Op);
   unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
 
   // TODO: Should this propagate fast-math-flags?
 
   switch (IntrinsicID) {
   case Intrinsic::amdgcn_implicit_buffer_ptr: {
-    unsigned Reg = TRI->getPreloadedValue(MF, SIRegisterInfo::PRIVATE_SEGMENT_BUFFER);
-    return CreateLiveInRegister(DAG, &AMDGPU::SReg_64RegClass, Reg, VT);
+    unsigned Reg =
+        TRI->getPreloadedValue(MF, SIRegisterInfo::PRIVATE_SEGMENT_BUFFER);
+    return CreateLiveInRegister(DAG, &AMDGPU::SReg_64_WITH_SUBREGSRegClass,
+                                Reg, VT);
   }
   case Intrinsic::amdgcn_dispatch_ptr:
   case Intrinsic::amdgcn_queue_ptr: {
     if (!Subtarget->isAmdCodeObjectV2(MF)) {
       DiagnosticInfoUnsupported BadIntrin(
           *MF.getFunction(), "unsupported hsa intrinsic without hsa target",
           DL.getDebugLoc());
       DAG.getContext()->diagnose(BadIntrin);
       return DAG.getUNDEF(VT);
     }
 
     auto Reg = IntrinsicID == Intrinsic::amdgcn_dispatch_ptr ?
       SIRegisterInfo::DISPATCH_PTR : SIRegisterInfo::QUEUE_PTR;
-    return CreateLiveInRegister(DAG, &AMDGPU::SReg_64RegClass,
+    return CreateLiveInRegister(DAG, &AMDGPU::SReg_64_WITH_SUBREGSRegClass,
                                 TRI->getPreloadedValue(MF, Reg), VT);
   }
   case Intrinsic::amdgcn_implicitarg_ptr: {
     unsigned offset = getImplicitParameterOffset(MFI, FIRST_IMPLICIT);
     return LowerParameterPtr(DAG, DL, DAG.getEntryNode(), offset);
   }
   case Intrinsic::amdgcn_kernarg_segment_ptr: {
     unsigned Reg
         = TRI->getPreloadedValue(MF, SIRegisterInfo::KERNARG_SEGMENT_PTR);
-    return CreateLiveInRegister(DAG, &AMDGPU::SReg_64RegClass, Reg, VT);
+    return CreateLiveInRegister(DAG, &AMDGPU::SReg_64_WITH_SUBREGSRegClass,
+                                Reg, VT);
   }
   case Intrinsic::amdgcn_dispatch_id: {
     unsigned Reg = TRI->getPreloadedValue(MF, SIRegisterInfo::DISPATCH_ID);
-    return CreateLiveInRegister(DAG, &AMDGPU::SReg_64RegClass, Reg, VT);
+    return CreateLiveInRegister(DAG, &AMDGPU::SReg_64_WITH_SUBREGSRegClass,
+                                Reg, VT);
   }
   case Intrinsic::amdgcn_rcp:
     return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1));
   case Intrinsic::amdgcn_rsq:
     return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
   case Intrinsic::amdgcn_rsq_legacy:
     if (Subtarget->getGeneration() >= SISubtarget::VOLCANIC_ISLANDS)
       return emitRemovedIntrinsicError(DAG, DL, VT);

lib/Target/AMDGPU/SIInstrInfo.cpp

if (!AMDGPU::SReg_32RegClass.contains(SrcReg)) {
       return;
     }
 
     BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
             .addReg(SrcReg, getKillRegState(KillSrc));
     return;
   }
 
-  if (RC == &AMDGPU::SReg_64RegClass) {
+  if (RC == &AMDGPU::SReg_64_WITH_SUBREGSRegClass) {
     if (DestReg == AMDGPU::VCC) {
-      if (AMDGPU::SReg_64RegClass.contains(SrcReg)) {
+      if (AMDGPU::SReg_64_WITH_SUBREGSRegClass.contains(SrcReg)) {
         BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC)
           .addReg(SrcReg, getKillRegState(KillSrc));
       } else {
         // FIXME: Hack until VReg_1 removed.
         assert(AMDGPU::VGPR_32RegClass.contains(SrcReg));
         BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_U32_e32))
           .addImm(0)
           .addReg(SrcReg, getKillRegState(KillSrc));
       }
 
       return;
     }
 
-    if (!AMDGPU::SReg_64RegClass.contains(SrcReg)) {
+    if (!AMDGPU::SReg_64_WITH_SUBREGSRegClass.contains(SrcReg)) {
       reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc);
       return;
     }
 
     BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
             .addReg(SrcReg, getKillRegState(KillSrc));
     return;
   }
if (!AMDGPU::isShader(MF->getFunction()->getCallingConv()) &&
       unsigned InputPtrReg =
           TRI->getPreloadedValue(*MF, SIRegisterInfo::KERNARG_SEGMENT_PTR);
       for (unsigned Reg : {TIDIGXReg, TIDIGYReg, TIDIGZReg}) {
         if (!Entry.isLiveIn(Reg))
           Entry.addLiveIn(Reg);
       }
 
       RS->enterBasicBlock(Entry);
-      // FIXME: Can we scavenge an SReg_64 and access the subregs?
+      // FIXME: Can we scavenge an SReg_64_WITH_SUBREGS and access the subregs?
       unsigned STmp0 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
       unsigned STmp1 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
       BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp0)
               .addReg(InputPtrReg)
               .addImm(SI::KernelInputOffsets::NGROUPS_Z);
       BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp1)
               .addReg(InputPtrReg)
               .addImm(SI::KernelInputOffsets::NGROUPS_Y);
assert(MBB.empty() &&
          "new block should be inserted for expanding unconditional branch");
   assert(MBB.pred_size() == 1);
 
   MachineFunction *MF = MBB.getParent();
   MachineRegisterInfo &MRI = MF->getRegInfo();
 
   // FIXME: Virtual register workaround for RegScavenger not working with empty
   // blocks.
-  unsigned PCReg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
+  unsigned PCReg =
+      MRI.createVirtualRegister(&AMDGPU::SReg_64_WITH_SUBREGSRegClass);
 
   auto I = MBB.end();
 
   // We need to compute the offset relative to the instruction immediately after
   // s_getpc_b64. Insert pc arithmetic code before last terminator.
   MachineInstr *GetPC = BuildMI(MBB, I, DL, get(AMDGPU::S_GETPC_B64), PCReg);
 
   // TODO: Handle > 32-bit block address.
unsigned SIInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
   // restore_bb:
   //  restore s[8:9]
   //  fallthrough dest_bb
   ///
   // dest_bb:
   //   buzz;
 
   RS->enterBasicBlockEnd(MBB);
-  unsigned Scav = RS->scavengeRegister(&AMDGPU::SReg_64RegClass,
+  unsigned Scav = RS->scavengeRegister(&AMDGPU::SReg_64_WITH_SUBREGSRegClass,
                                        MachineBasicBlock::iterator(GetPC), 0);
   MRI.replaceRegWith(PCReg, Scav);
   MRI.clearVirtRegs();
   RS->setRegUsed(Scav);
 
   return 4 + 8 + 4 + 4;
 }
 
if (SRsrcIdx != -1) {
 
     MachineBasicBlock &MBB = *MI.getParent();
 
     // Extract the ptr from the resource descriptor.
     unsigned SRsrcPtr = buildExtractSubReg(MI, MRI, *SRsrc,
       &AMDGPU::VReg_128RegClass, AMDGPU::sub0_sub1, &AMDGPU::VReg_64RegClass);
 
     // Create an empty resource descriptor
-    unsigned Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
+    unsigned Zero64 =
+        MRI.createVirtualRegister(&AMDGPU::SReg_64_WITH_SUBREGSRegClass);
     unsigned SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
     unsigned SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
     unsigned NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
     uint64_t RsrcDataFormat = getDefaultRsrcDataFormat();
 
     // Zero64 = 0
     BuildMI(MBB, MI, MI.getDebugLoc(), get(AMDGPU::S_MOV_B64), Zero64)
         .addImm(0);

lib/Target/AMDGPU/SILowerControlFlow.cpp

void SILowerControlFlow::emitIf(MachineInstr &MI) {
 
   unsigned SaveExecReg = SaveExec.getReg();
 
   MachineOperand &ImpDefSCC = MI.getOperand(4);
   assert(ImpDefSCC.getReg() == AMDGPU::SCC && ImpDefSCC.isDef());
 
   // Add an implicit def of exec to discourage scheduling VALU after this which
   // will interfere with trying to form s_and_saveexec_b64 later.
-  unsigned CopyReg = MRI->createVirtualRegister(&AMDGPU::SReg_64RegClass);
+  unsigned CopyReg =
+      MRI->createVirtualRegister(&AMDGPU::SReg_64_WITH_SUBREGSRegClass);
   MachineInstr *CopyExec =
     BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), CopyReg)
     .addReg(AMDGPU::EXEC)
     .addReg(AMDGPU::EXEC, RegState::ImplicitDefine);
 
-  unsigned Tmp = MRI->createVirtualRegister(&AMDGPU::SReg_64RegClass);
+  unsigned Tmp =
+      MRI->createVirtualRegister(&AMDGPU::SReg_64_WITH_SUBREGSRegClass);
 
   MachineInstr *And =
     BuildMI(MBB, I, DL, TII->get(AMDGPU::S_AND_B64), Tmp)
     .addReg(CopyReg)
     //.addReg(AMDGPU::EXEC)
     .addReg(Cond.getReg());
   setImpSCCDefDead(*And, true);
 
void SILowerControlFlow::emitElse(MachineInstr &MI) {
   assert(MI.getOperand(0).getSubReg() == AMDGPU::NoSubRegister);
 
   bool ExecModified = MI.getOperand(3).getImm() != 0;
   MachineBasicBlock::iterator Start = MBB.begin();
 
   // We are running before TwoAddressInstructions, and si_else's operands are
   // tied. In order to correctly tie the registers, split this into a copy of
   // the src like it does.
-  unsigned CopyReg = MRI->createVirtualRegister(&AMDGPU::SReg_64RegClass);
+  unsigned CopyReg =
+      MRI->createVirtualRegister(&AMDGPU::SReg_64_WITH_SUBREGSRegClass);
   MachineInstr *CopyExec =
     BuildMI(MBB, Start, DL, TII->get(AMDGPU::COPY), CopyReg)
       .add(MI.getOperand(1)); // Saved EXEC
 
   // This must be inserted before phis and any spill code inserted before the
   // else.
   unsigned SaveReg = ExecModified ?
-    MRI->createVirtualRegister(&AMDGPU::SReg_64RegClass) : DstReg;
+    MRI->createVirtualRegister(&AMDGPU::SReg_64_WITH_SUBREGSRegClass) : DstReg;
   MachineInstr *OrSaveExec =
     BuildMI(MBB, Start, DL, TII->get(AMDGPU::S_OR_SAVEEXEC_B64), SaveReg)
     .addReg(CopyReg);
 
   MachineBasicBlock *DestBB = MI.getOperand(2).getMBB();
 
   MachineBasicBlock::iterator ElsePt(MI);
 

lib/Target/AMDGPU/SILowerI1Copies.cpp

for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
     for (I = MBB.begin(); I != MBB.end(); I = Next) {
       Next = std::next(I);
       MachineInstr &MI = *I;
 
       if (MI.getOpcode() == AMDGPU::IMPLICIT_DEF) {
         unsigned Reg = MI.getOperand(0).getReg();
         const TargetRegisterClass *RC = MRI.getRegClass(Reg);
         if (RC == &AMDGPU::VReg_1RegClass)
-          MRI.setRegClass(Reg, &AMDGPU::SReg_64RegClass);
+          MRI.setRegClass(Reg, &AMDGPU::SReg_64_WITH_SUBREGSRegClass);
         continue;
       }
 
       if (MI.getOpcode() != AMDGPU::COPY)
         continue;
 
       const MachineOperand &Dst = MI.getOperand(0);
       const MachineOperand &Src = MI.getOperand(1);

lib/Target/AMDGPU/SIMachineFunctionInfo.cpp

unsigned SIMachineFunctionInfo::addPrivateSegmentBuffer(
   PrivateSegmentBufferUserSGPR = TRI.getMatchingSuperReg(
     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_128RegClass);
   NumUserSGPRs += 4;
   return PrivateSegmentBufferUserSGPR;
 }
 
 unsigned SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) {
   DispatchPtrUserSGPR = TRI.getMatchingSuperReg(
-    getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass);
+    getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64_WITH_SUBREGSRegClass);
   NumUserSGPRs += 2;
   return DispatchPtrUserSGPR;
 }
 
 unsigned SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) {
   QueuePtrUserSGPR = TRI.getMatchingSuperReg(
-    getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass);
+    getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64_WITH_SUBREGSRegClass);
   NumUserSGPRs += 2;
   return QueuePtrUserSGPR;
 }
 
 unsigned SIMachineFunctionInfo::addKernargSegmentPtr(const SIRegisterInfo &TRI) {
   KernargSegmentPtrUserSGPR = TRI.getMatchingSuperReg(
-    getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass);
+    getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64_WITH_SUBREGSRegClass);
   NumUserSGPRs += 2;
   return KernargSegmentPtrUserSGPR;
 }
 
 unsigned SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) {
   DispatchIDUserSGPR = TRI.getMatchingSuperReg(
-    getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass);
+    getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64_WITH_SUBREGSRegClass);
   NumUserSGPRs += 2;
   return DispatchIDUserSGPR;
 }
 
 unsigned SIMachineFunctionInfo::addFlatScratchInit(const SIRegisterInfo &TRI) {
   FlatScratchInitUserSGPR = TRI.getMatchingSuperReg(
-    getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass);
+    getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64_WITH_SUBREGSRegClass);
   NumUserSGPRs += 2;
   return FlatScratchInitUserSGPR;
 }
 
 unsigned SIMachineFunctionInfo::addPrivateMemoryPtr(const SIRegisterInfo &TRI) {
   PrivateMemoryPtrUserSGPR = TRI.getMatchingSuperReg(
-    getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass);
+    getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64_WITH_SUBREGSRegClass);
   NumUserSGPRs += 2;
   return PrivateMemoryPtrUserSGPR;
 }
 
 /// Reserve a slice of a VGPR to support spilling for FrameIndex \p FI.
 bool SIMachineFunctionInfo::allocateSGPRSpillToVGPR(MachineFunction &MF,
                                                     int FI) {
   std::vector<SpilledReg> &SpillLanes = SGPRToVGPRSpills[FI];

lib/Target/AMDGPU/SIRegisterInfo.cpp

BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   BitVector Reserved(getNumRegs());
   Reserved.set(AMDGPU::INDIRECT_BASE_ADDR);
 
   // EXEC_LO and EXEC_HI could be allocated and used as regular register, but
   // this seems likely to result in bugs, so I'm marking them as reserved.
   reserveRegisterTuples(Reserved, AMDGPU::EXEC);
   reserveRegisterTuples(Reserved, AMDGPU::FLAT_SCR);
 
-  // Reserve the memory aperture registers.
-  reserveRegisterTuples(Reserved, AMDGPU::SRC_SHARED_BASE);
-  reserveRegisterTuples(Reserved, AMDGPU::SRC_SHARED_LIMIT);
-  reserveRegisterTuples(Reserved, AMDGPU::SRC_PRIVATE_BASE);
-  reserveRegisterTuples(Reserved, AMDGPU::SRC_PRIVATE_LIMIT);
-
   // Reserve Trap Handler registers - support is not implemented in Codegen.
   reserveRegisterTuples(Reserved, AMDGPU::TBA);
   reserveRegisterTuples(Reserved, AMDGPU::TMA);
   reserveRegisterTuples(Reserved, AMDGPU::TTMP0_TTMP1);
   reserveRegisterTuples(Reserved, AMDGPU::TTMP2_TTMP3);
   reserveRegisterTuples(Reserved, AMDGPU::TTMP4_TTMP5);
   reserveRegisterTuples(Reserved, AMDGPU::TTMP6_TTMP7);
   reserveRegisterTuples(Reserved, AMDGPU::TTMP8_TTMP9);
void SIRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,
 
   if (Offset == 0) {
     BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::V_MOV_B32_e32), BaseReg)
       .addFrameIndex(FrameIdx);
     return;
   }
 
   MachineRegisterInfo &MRI = MF->getRegInfo();
-  unsigned UnusedCarry = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
-  unsigned OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
+  unsigned UnusedCarry =
+      MRI.createVirtualRegister(&AMDGPU::SReg_64_WITH_SUBREGSRegClass);
+  unsigned OffsetReg =
+      MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
 
   unsigned FIReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
 
   BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg)
     .addImm(Offset);
   BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::V_MOV_B32_e32), FIReg)
     .addFrameIndex(FrameIdx);
 

 // register class.
 const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const {
   assert(!TargetRegisterInfo::isVirtualRegister(Reg));
 
   static const TargetRegisterClass *const BaseClasses[] = {
     &AMDGPU::VGPR_32RegClass,
     &AMDGPU::SReg_32RegClass,
     &AMDGPU::VReg_64RegClass,
-    &AMDGPU::SReg_64RegClass,
+    &AMDGPU::SReg_64_WITH_SUBREGSRegClass,
     &AMDGPU::VReg_96RegClass,
     &AMDGPU::VReg_128RegClass,
     &AMDGPU::SReg_128RegClass,
     &AMDGPU::VReg_256RegClass,
     &AMDGPU::SReg_256RegClass,
     &AMDGPU::VReg_512RegClass,
     &AMDGPU::SReg_512RegClass,
     &AMDGPU::SCC_CLASSRegClass,

 }
 
 const TargetRegisterClass *SIRegisterInfo::getEquivalentSGPRClass(
                                          const TargetRegisterClass *VRC) const {
   switch (VRC->getSize()) {
   case 4:
     return &AMDGPU::SGPR_32RegClass;
   case 8:
-    return &AMDGPU::SReg_64RegClass;
+    return &AMDGPU::SReg_64_WITH_SUBREGSRegClass;
   case 16:
     return &AMDGPU::SReg_128RegClass;
   case 32:
     return &AMDGPU::SReg_256RegClass;
   case 64:
     return &AMDGPU::SReg_512RegClass;
   default:
     llvm_unreachable("Invalid register class size");
   }
 }
 
 const TargetRegisterClass *SIRegisterInfo::getSubRegClass(
                          const TargetRegisterClass *RC, unsigned SubIdx) const {
   if (SubIdx == AMDGPU::NoSubRegister)
     return RC;
 
   // We can assume that each lane corresponds to one 32-bit register.
   LaneBitmask::Type Mask = getSubRegIndexLaneMask(SubIdx).getAsInteger();
   unsigned Count = countPopulation(Mask);
   if (isSGPRClass(RC)) {
     switch (Count) {
     case 1:
       return &AMDGPU::SGPR_32RegClass;
     case 2:
-      return &AMDGPU::SReg_64RegClass;
+      return &AMDGPU::SReg_64_WITH_SUBREGSRegClass;
     case 4:
       return &AMDGPU::SReg_128RegClass;
     case 8:
       return &AMDGPU::SReg_256RegClass;
     case 16: /* fall-through */
     default:
       llvm_unreachable("Invalid sub-register class size");
     }

lib/Target/AMDGPU/SIRegisterInfo.td

def SCC_CLASS : RegisterClass<"AMDGPU", [i1], 1, (add SCC)> {
   let isAllocatable = 0;
 }
 
 def M0_CLASS : RegisterClass<"AMDGPU", [i32], 32, (add M0)> {
   let CopyCost = 1;
   let isAllocatable = 0;
 }
 
+def APERTURE_CLASS : RegisterClass<"AMDGPU", [i64], 32,
+  (add SRC_SHARED_BASE, SRC_SHARED_LIMIT, SRC_PRIVATE_BASE,
+   SRC_PRIVATE_LIMIT)> {
+  let CopyCost = 1;
+  let isAllocatable = 0;
+}
+
 // TODO: Do we need to set DwarfRegAlias on register tuples?
 
 // SGPR 32-bit registers
 def SGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
                             (add (sequence "SGPR%u", 0, 103))> {
   // Give all SGPR classes higher priority than VGPR classes, because
   // we want to spill SGPRs to VGPRs.
   let AllocationPriority = 7;

 //===----------------------------------------------------------------------===//
 //  Register classes used as source and destination
 //===----------------------------------------------------------------------===//
 
 // Subset of SReg_32 without M0 for SMRD instructions and alike.
 // See comments in SIInstructions.td for more info.
 def SReg_32_XM0_XEXEC : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
   (add SGPR_32, VCC_LO, VCC_HI, FLAT_SCR_LO, FLAT_SCR_HI,
-   TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI, SRC_SHARED_BASE, SRC_SHARED_LIMIT,
-   SRC_PRIVATE_BASE, SRC_PRIVATE_LIMIT)> {
+   TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI)> {
   let AllocationPriority = 7;
 }
 
 def SReg_32_XM0 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
   (add SReg_32_XM0_XEXEC, EXEC_LO, EXEC_HI)> {
   let AllocationPriority = 7;
 }
 

 }
 
 def SReg_64_XEXEC : RegisterClass<"AMDGPU", [v2i32, i64, f64, i1], 32,
   (add SGPR_64, VCC, FLAT_SCR, TTMP_64, TBA, TMA)> {
   let CopyCost = 1;
   let AllocationPriority = 8;
 }
 
-def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64, i1], 32,
+def SReg_64_WITH_SUBREGS : RegisterClass<"AMDGPU", [v2i32, i64, f64, i1], 32,
   (add SReg_64_XEXEC, EXEC)> {
   let CopyCost = 1;
   let AllocationPriority = 8;
 }
 
+def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64, i1], 32,
+  (add SReg_64_WITH_SUBREGS, APERTURE_CLASS)> {
+  let CopyCost = 1;
+  let AllocationPriority = 8;
+}
+
 // Requires 2 s_mov_b64 to copy
 let CopyCost = 2 in {
 
 def SGPR_128 : RegisterClass<"AMDGPU", [v4i32, v16i8, v2i64], 32, (add SGPR_128Regs)> {
   let AllocationPriority = 10;
 }
 
 def TTMP_128 : RegisterClass<"AMDGPU", [v4i32, v16i8, v2i64], 32, (add TTMP_128Regs)> {

lib/Target/AMDGPU/SIWholeQuadMode.cpp

for (;;) {
 
     if (Needs) {
       if (Needs != State) {
         MachineBasicBlock::iterator Before =
             prepareInsertion(MBB, First, II, Needs == StateWQM,
                              Needs == StateExact || WQMFromExec);
 
         if (Needs == StateExact) {
-          if (!WQMFromExec && (OutNeeds & StateWQM))
-            SavedWQMReg = MRI->createVirtualRegister(&AMDGPU::SReg_64RegClass);
+          if (!WQMFromExec && (OutNeeds & StateWQM)) {
+            SavedWQMReg =
+              MRI->createVirtualRegister(&AMDGPU::SReg_64_WITH_SUBREGSRegClass);
+          }
 
           toExact(MBB, Before, SavedWQMReg, LiveMaskReg);
         } else {
           assert(WQMFromExec == (SavedWQMReg == 0));
 
           toWQM(MBB, Before, SavedWQMReg);
 
           if (SavedWQMReg) {
bool SIWholeQuadMode::runOnMachineFunction(MachineFunction &MF) {
 
   // Store a copy of the original live mask when required
   unsigned LiveMaskReg = 0;
   {
     MachineBasicBlock &Entry = MF.front();
     MachineBasicBlock::iterator EntryMI = Entry.getFirstNonPHI();
 
     if (GlobalFlags & StateExact || !LiveMaskQueries.empty()) {
-      LiveMaskReg = MRI->createVirtualRegister(&AMDGPU::SReg_64RegClass);
+      LiveMaskReg =
+          MRI->createVirtualRegister(&AMDGPU::SReg_64_WITH_SUBREGSRegClass);
       MachineInstr *MI = BuildMI(Entry, EntryMI, DebugLoc(),
                                  TII->get(AMDGPU::COPY), LiveMaskReg)
                              .addReg(AMDGPU::EXEC);
       LIS->InsertMachineInstrInMaps(*MI);
     }
 
     if (GlobalFlags == StateWQM) {
       // For a shader that needs only WQM, we can just set it once.

lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

unsigned getRegBitWidth(unsigned RCID) {
   case AMDGPU::VGPR_32RegClassID:
   case AMDGPU::VS_32RegClassID:
   case AMDGPU::SReg_32RegClassID:
   case AMDGPU::SReg_32_XM0RegClassID:
     return 32;
   case AMDGPU::SGPR_64RegClassID:
   case AMDGPU::VS_64RegClassID:
   case AMDGPU::SReg_64RegClassID:
+  case AMDGPU::SReg_64_WITH_SUBREGSRegClassID:
   case AMDGPU::VReg_64RegClassID:
     return 64;
   case AMDGPU::VReg_96RegClassID:
     return 96;
   case AMDGPU::SGPR_128RegClassID:
   case AMDGPU::SReg_128RegClassID:
   case AMDGPU::VReg_128RegClassID:
     return 128;

test/CodeGen/AMDGPU/branch-relax-spill.ll

 ; RUN: not llc -march=amdgcn -verify-machineinstrs  -amdgpu-s-branch-bits=4 < %s 2>&1 | FileCheck -check-prefix=FAIL %s
 
 ; FIXME: This should be able to compile, but requires inserting an
 ; extra block to restore the scavenged register.
 
-; FAIL: LLVM ERROR: Error while trying to spill VCC from class SReg_64: Cannot scavenge register without an emergency spill slot!
+; FAIL: LLVM ERROR: Error while trying to spill VCC from class SReg_64_WITH_SUBREGS: Cannot scavenge register without an emergency spill slot!
 
 define amdgpu_kernel void @spill(i32 addrspace(1)* %arg, i32 %cnd) #0 {
 entry:
   %sgpr0 = tail call i32 asm sideeffect "s_mov_b32 s0, 0", "={SGPR0}"() #0
   %sgpr1 = tail call i32 asm sideeffect "s_mov_b32 s1, 0", "={SGPR1}"() #0
   %sgpr2 = tail call i32 asm sideeffect "s_mov_b32 s2, 0", "={SGPR2}"() #0
   %sgpr3 = tail call i32 asm sideeffect "s_mov_b32 s3, 0", "={SGPR3}"() #0
   %sgpr4 = tail call i32 asm sideeffect "s_mov_b32 s4, 0", "={SGPR4}"() #0

test/CodeGen/MIR/AMDGPU/fold-imm-f16-f32.mir

 name:            add_f32_1.0_one_f16_use
 alignment:       0
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: sreg_64 }
+  - { id: 0, class: sreg_64_with_subregs }
   - { id: 1, class: sreg_32 }
   - { id: 2, class: sgpr_32 }
   - { id: 3, class: vgpr_32 }
-  - { id: 4, class: sreg_64 }
+  - { id: 4, class: sreg_64_with_subregs }
   - { id: 5, class: sreg_32 }
-  - { id: 6, class: sreg_64 }
+  - { id: 6, class: sreg_64_with_subregs }
   - { id: 7, class: sreg_32 }
   - { id: 8, class: sreg_32 }
   - { id: 9, class: sreg_32 }
   - { id: 10, class: sreg_128 }
   - { id: 11, class: vgpr_32 }
   - { id: 12, class: vgpr_32 }
   - { id: 13, class: vgpr_32 }
 frameInfo:

 name:            add_f32_1.0_multi_f16_use
 alignment:       0
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: sreg_64 }
+  - { id: 0, class: sreg_64_with_subregs }
   - { id: 1, class: sreg_32 }
   - { id: 2, class: sgpr_32 }
   - { id: 3, class: vgpr_32 }
-  - { id: 4, class: sreg_64 }
+  - { id: 4, class: sreg_64_with_subregs }
   - { id: 5, class: sreg_32 }
-  - { id: 6, class: sreg_64 }
+  - { id: 6, class: sreg_64_with_subregs }
   - { id: 7, class: sreg_32 }
   - { id: 8, class: sreg_32 }
   - { id: 9, class: sreg_32 }
   - { id: 10, class: sreg_128 }
   - { id: 11, class: vgpr_32 }
   - { id: 12, class: vgpr_32 }
   - { id: 13, class: vgpr_32 }
   - { id: 14, class: vgpr_32 }

 name:            add_f32_1.0_one_f32_use_one_f16_use
 alignment:       0
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: sreg_64 }
+  - { id: 0, class: sreg_64_with_subregs }
   - { id: 1, class: sreg_32 }
   - { id: 2, class: sgpr_32 }
   - { id: 3, class: vgpr_32 }
-  - { id: 4, class: sreg_64 }
+  - { id: 4, class: sreg_64_with_subregs }
   - { id: 5, class: sreg_32 }
-  - { id: 6, class: sreg_64 }
+  - { id: 6, class: sreg_64_with_subregs }
   - { id: 7, class: sreg_32 }
   - { id: 8, class: sreg_32 }
   - { id: 9, class: sreg_32 }
   - { id: 10, class: sreg_128 }
   - { id: 11, class: vgpr_32 }
   - { id: 12, class: vgpr_32 }
   - { id: 13, class: vgpr_32 }
   - { id: 14, class: vgpr_32 }

 name:            add_f32_1.0_one_f32_use_multi_f16_use
 alignment:       0
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: sreg_64 }
+  - { id: 0, class: sreg_64_with_subregs }
   - { id: 1, class: sreg_32 }
   - { id: 2, class: sgpr_32 }
   - { id: 3, class: vgpr_32 }
-  - { id: 4, class: sreg_64 }
+  - { id: 4, class: sreg_64_with_subregs }
   - { id: 5, class: sreg_32 }
-  - { id: 6, class: sreg_64 }
+  - { id: 6, class: sreg_64_with_subregs }
   - { id: 7, class: sreg_32 }
   - { id: 8, class: sreg_32 }
   - { id: 9, class: sreg_32 }
   - { id: 10, class: sreg_128 }
   - { id: 11, class: vgpr_32 }
   - { id: 12, class: vgpr_32 }
   - { id: 13, class: vgpr_32 }
   - { id: 14, class: vgpr_32 }

 name:            add_i32_1_multi_f16_use
 alignment:       0
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: sreg_64 }
+  - { id: 0, class: sreg_64_with_subregs }
   - { id: 1, class: sreg_32 }
   - { id: 2, class: sgpr_32 }
   - { id: 3, class: vgpr_32 }
-  - { id: 4, class: sreg_64 }
+  - { id: 4, class: sreg_64_with_subregs }
   - { id: 5, class: sreg_32 }
-  - { id: 6, class: sreg_64 }
+  - { id: 6, class: sreg_64_with_subregs }
   - { id: 7, class: sreg_32 }
   - { id: 8, class: sreg_32 }
   - { id: 9, class: sreg_32 }
   - { id: 10, class: sreg_128 }
   - { id: 11, class: vgpr_32 }
   - { id: 12, class: vgpr_32 }
   - { id: 13, class: vgpr_32 }
   - { id: 14, class: vgpr_32 }

 name:            add_i32_m2_one_f32_use_multi_f16_use
 alignment:       0
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: sreg_64 }
+  - { id: 0, class: sreg_64_with_subregs }
   - { id: 1, class: sreg_32 }
   - { id: 2, class: sgpr_32 }
   - { id: 3, class: vgpr_32 }
-  - { id: 4, class: sreg_64 }
+  - { id: 4, class: sreg_64_with_subregs }
   - { id: 5, class: sreg_32 }
-  - { id: 6, class: sreg_64 }
+  - { id: 6, class: sreg_64_with_subregs }
   - { id: 7, class: sreg_32 }
   - { id: 8, class: sreg_32 }
   - { id: 9, class: sreg_32 }
   - { id: 10, class: sreg_128 }
   - { id: 11, class: vgpr_32 }
   - { id: 12, class: vgpr_32 }
   - { id: 13, class: vgpr_32 }
   - { id: 14, class: vgpr_32 }

 name:            add_f16_1.0_multi_f32_use
 alignment:       0
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: sreg_64 }
+  - { id: 0, class: sreg_64_with_subregs }
   - { id: 1, class: sreg_32 }
   - { id: 2, class: sgpr_32 }
   - { id: 3, class: vgpr_32 }
-  - { id: 4, class: sreg_64 }
+  - { id: 4, class: sreg_64_with_subregs }
   - { id: 5, class: sreg_32 }
-  - { id: 6, class: sreg_64 }
+  - { id: 6, class: sreg_64_with_subregs }
   - { id: 7, class: sreg_32 }
   - { id: 8, class: sreg_32 }
   - { id: 9, class: sreg_32 }
   - { id: 10, class: sreg_128 }
   - { id: 11, class: vgpr_32 }
   - { id: 12, class: vgpr_32 }
   - { id: 13, class: vgpr_32 }
   - { id: 14, class: vgpr_32 }

 name:            add_f16_1.0_other_high_bits_multi_f16_use
 alignment:       0
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: sreg_64 }
+  - { id: 0, class: sreg_64_with_subregs }
   - { id: 1, class: sreg_32 }
   - { id: 2, class: sgpr_32 }
   - { id: 3, class: vgpr_32 }
-  - { id: 4, class: sreg_64 }
+  - { id: 4, class: sreg_64_with_subregs }
   - { id: 5, class: sreg_32 }
-  - { id: 6, class: sreg_64 }
+  - { id: 6, class: sreg_64_with_subregs }
   - { id: 7, class: sreg_32 }
   - { id: 8, class: sreg_32 }
   - { id: 9, class: sreg_32 }
   - { id: 10, class: sreg_128 }
   - { id: 11, class: vgpr_32 }
   - { id: 12, class: vgpr_32 }
   - { id: 13, class: vgpr_32 }
   - { id: 14, class: vgpr_32 }

 name:            add_f16_1.0_other_high_bits_use_f16_f32
 alignment:       0
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: sreg_64 }
+  - { id: 0, class: sreg_64_with_subregs }
   - { id: 1, class: sreg_32 }
   - { id: 2, class: sgpr_32 }
   - { id: 3, class: vgpr_32 }
-  - { id: 4, class: sreg_64 }
+  - { id: 4, class: sreg_64_with_subregs }
   - { id: 5, class: sreg_32 }
-  - { id: 6, class: sreg_64 }
+  - { id: 6, class: sreg_64_with_subregs }
   - { id: 7, class: sreg_32 }
   - { id: 8, class: sreg_32 }
   - { id: 9, class: sreg_32 }
   - { id: 10, class: sreg_128 }
   - { id: 11, class: vgpr_32 }
   - { id: 12, class: vgpr_32 }
   - { id: 13, class: vgpr_32 }
   - { id: 14, class: vgpr_32 }

test/MC/Disassembler/AMDGPU/aperture-regs.ll

 # RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX9 %s
 
-# GFX9: v_mov_b32_e32 v1, src_shared_base ; encoding: [0xeb,0x02,0x02,0x7e]
-0xeb 0x02 0x02 0x7e
+# GFX9: s_mov_b64 s[0:1], src_shared_base ; encoding: [0xeb,0x01,0x80,0xbe]
+0xeb 0x01 0x80 0xbe
 
-# GFX9: v_mov_b32_e32 v1, src_shared_limit ; encoding: [0xec,0x02,0x02,0x7e]
-0xec 0x02 0x02 0x7e
+# GFX9: s_mov_b64 s[0:1], src_shared_limit ; encoding: [0xec,0x01,0x80,0xbe]
+0xec 0x01 0x80 0xbe
 
-# GFX9: v_mov_b32_e32 v1, src_private_base ; encoding: [0xed,0x02,0x02,0x7e]
-0xed 0x02 0x02 0x7e
+# GFX9: s_mov_b64 s[0:1], src_private_base ; encoding: [0xed,0x01,0x80,0xbe]
+0xed 0x01 0x80 0xbe
 
-# GFX9: v_mov_b32_e32 v1, src_private_limit ; encoding: [0xee,0x02,0x02,0x7e]
-0xee 0x02 0x02 0x7e
+# GFX9: s_mov_b64 s[0:1], src_private_limit ; encoding: [0xee,0x01,0x80,0xbe]
+0xee 0x01 0x80 0xbe

unittests/MI/LiveIntervalTest.cpp

static void liveIntervalTest(StringRef MIRFunc, LiveIntervalTest T) {
   legacy::PassManager PM;
 
   SmallString<160> S;
   StringRef MIRString = (Twine(R"MIR(
 ---
 ...
 name: func
 registers:
-  - { id: 0, class: sreg_64 }
+  - { id: 0, class: sreg_64_with_subregs }
 body: |
   bb.0:
 )MIR") + Twine(MIRFunc) + Twine("...\n")).toNullTerminatedStringRef(S);
   std::unique_ptr<MIRParser> MIR;
   std::unique_ptr<Module> M = parseMIR(Context, PM, MIR, *TM, MIRString,
                                        "func");
 
   PM.add(new TestPass(T));