- Introduce register class for SReg_64 with subregisters
- Introduce register class for aperture registers
- Make aperture register class a part of SReg_64 register class
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arsenm
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I think this requires changing the register class for SSrc_32/VSrc_32 to be the one that includes the special 32-bit regs. I think I started doing this to start supporting vccz and the other special 1-bit inputs
I do not think so. src_*_base and src_*_limit are 64 bit inline constants. Here is an example of src_shared_base:
{SMB.shared_base[15:0], 48’h000000000000}
src_*_base and src_*_limit also do not have subregisters.
lib/Target/AMDGPU/SIRegisterInfo.td | ||
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133 | Aperture registers are 64 bit inline constants. | |
306 | Which one? | |
313 | Those are 64 bit inline constants, hence in 64 bit register class. | |
315 | APERTURE_REGS is let isAllocatable = 0. |
According to the manual it says if used with a 32-bit input, the 32 LSBs are used, so I guess it has sub0 but not sub1
While you're working on this, can you implement TargetRegisterInfo::isConstantPhysReg for these?
Aren't these 32bit only, so i32?