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Differential D31854

AMDGPU: Fix crash when disassembling VOP3 mac
ClosedPublic

Authored by arsenm on Apr 8 2017, 1:38 PM.

Details

Reviewers
kzhuravl
vpykhtin
dp
Summary

The unused dummy src2_modifiers is missing, so it crashes
when trying to print it.




I tried to fully remove src2_modifiers, but there are some

irritations in the places where it is converted to mad since

it starts to require modifying use lists while iterating over

them.
Diff Detail
Event Timeline
arsenm created this revision.Apr 8 2017, 1:38 PM
Herald added subscribers: t-tye, tpr, dstuttard and 4 others.  ·  View Herald TranscriptApr 8 2017, 1:38 PM
arsenm added reviewers: vpykhtin, kzhuravl.Apr 10 2017, 8:03 AM
vpykhtin accepted this revision.Apr 10 2017, 11:06 AM
vpykhtin added a reviewer: dp.
LGTM.
This revision is now accepted and ready to land.Apr 10 2017, 11:07 AM
arsenm closed this revision.Apr 10 2017, 11:10 AM
r299861
Revision Contents
PathSize
lib/
Target/
AMDGPU/
1 line
1 line
1 line
1 line
Disassembler/
16 lines
MCTargetDesc/
6 lines
1 line
Utils/
4 lines
9 lines
2 lines
test/
MC/
Disassembler/
AMDGPU/
19 lines
Diff 94604
lib/Target/AMDGPU/AMDGPU.h
//===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
//===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//

//
//

//                     The LLVM Compiler Infrastructure
//                     The LLVM Compiler Infrastructure

//
//

// This file is distributed under the University of Illinois Open Source
// This file is distributed under the University of Illinois Open Source

// License. See LICENSE.TXT for details.
// License. See LICENSE.TXT for details.

//
//

/// \file
/// \file

//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//




#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H

#define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
#define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H




#include "MCTargetDesc/AMDGPUMCTargetDesc.h"

#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetMachine.h"




namespace llvm {
namespace llvm {




class AMDGPUTargetMachine;
class AMDGPUTargetMachine;

class FunctionPass;
class FunctionPass;

class GCNTargetMachine;
class GCNTargetMachine;

class ModulePass;
class ModulePass;

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lib/Target/AMDGPU/AMDGPUInstrInfo.h
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H

#define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
#define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H




#include "AMDGPU.h"
#include "AMDGPU.h"

#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetInstrInfo.h"

#include "Utils/AMDGPUBaseInfo.h"
#include "Utils/AMDGPUBaseInfo.h"




#define GET_INSTRINFO_HEADER
#define GET_INSTRINFO_HEADER

#define GET_INSTRINFO_ENUM

#include "AMDGPUGenInstrInfo.inc"
#include "AMDGPUGenInstrInfo.inc"




namespace llvm {
namespace llvm {




class AMDGPUSubtarget;
class AMDGPUSubtarget;

class MachineFunction;
class MachineFunction;

class MachineInstr;
class MachineInstr;

class MachineInstrBuilder;
class MachineInstrBuilder;

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lib/Target/AMDGPU/AMDGPURegisterInfo.h
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//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//




#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERINFO_H
#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERINFO_H

#define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERINFO_H
#define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERINFO_H




#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"




#define GET_REGINFO_HEADER
#define GET_REGINFO_HEADER

#define GET_REGINFO_ENUM

#include "AMDGPUGenRegisterInfo.inc"
#include "AMDGPUGenRegisterInfo.inc"




namespace llvm {
namespace llvm {




class AMDGPUSubtarget;
class AMDGPUSubtarget;

class TargetInstrInfo;
class TargetInstrInfo;




struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo {
struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo {

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lib/Target/AMDGPU/AMDGPUSubtarget.cpp
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#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/CodeGen/MachineScheduler.h"

#include "llvm/Target/TargetFrameLowering.h"
#include "llvm/Target/TargetFrameLowering.h"

#include <algorithm>
#include <algorithm>




using namespace llvm;
using namespace llvm;




#define DEBUG_TYPE "amdgpu-subtarget"
#define DEBUG_TYPE "amdgpu-subtarget"




#define GET_SUBTARGETINFO_ENUM

#define GET_SUBTARGETINFO_TARGET_DESC
#define GET_SUBTARGETINFO_TARGET_DESC

#define GET_SUBTARGETINFO_CTOR
#define GET_SUBTARGETINFO_CTOR

#include "AMDGPUGenSubtargetInfo.inc"
#include "AMDGPUGenSubtargetInfo.inc"




AMDGPUSubtarget::~AMDGPUSubtarget() = default;
AMDGPUSubtarget::~AMDGPUSubtarget() = default;




AMDGPUSubtarget &
AMDGPUSubtarget &

AMDGPUSubtarget::initializeSubtargetDependencies(const Triple &TT,
AMDGPUSubtarget::initializeSubtargetDependencies(const Triple &TT,

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lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
Show All 16 Lines



// ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)?
// ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)?




#include "AMDGPUDisassembler.h"
#include "AMDGPUDisassembler.h"

#include "AMDGPU.h"
#include "AMDGPU.h"

#include "AMDGPURegisterInfo.h"
#include "AMDGPURegisterInfo.h"

#include "SIDefines.h"
#include "SIDefines.h"

#include "Utils/AMDGPUBaseInfo.h"
#include "Utils/AMDGPUBaseInfo.h"

#include "MCTargetDesc/AMDGPUMCTargetDesc.h"




#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCContext.h"

#include "llvm/MC/MCFixedLenDisassembler.h"
#include "llvm/MC/MCFixedLenDisassembler.h"

#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInst.h"

#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrDesc.h"

#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"

#include "llvm/Support/ELF.h"
#include "llvm/Support/ELF.h"

#include "llvm/Support/Endian.h"
#include "llvm/Support/Endian.h"

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static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst,
static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst,

                                         unsigned Imm,
                                         unsigned Imm,

                                         uint64_t Addr,
                                         uint64_t Addr,

                                         const void *Decoder) {
                                         const void *Decoder) {

  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);

  return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm));
  return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm));

}
}




#define GET_SUBTARGETINFO_ENUM

#include "AMDGPUGenSubtargetInfo.inc"

#undef GET_SUBTARGETINFO_ENUM



#include "AMDGPUGenDisassemblerTables.inc"
#include "AMDGPUGenDisassemblerTables.inc"




//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//

//
//

//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//




template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) {
template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) {

  assert(Bytes.size() >= sizeof(T));
  assert(Bytes.size() >= sizeof(T));

▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines  do {

    if (Bytes.size() < 4) break;
    if (Bytes.size() < 4) break;

    const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW;
    const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW;

    Res = tryDecodeInst(DecoderTableVI64, MI, QW, Address);
    Res = tryDecodeInst(DecoderTableVI64, MI, QW, Address);

    if (Res) break;
    if (Res) break;




    Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address);
    Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address);

  } while (false);
  } while (false);




  if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi ||

              MI.getOpcode() == AMDGPU::V_MAC_F32_e64_si ||

              MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi)) {

    // Insert dummy unused src2_modifiers.

    int Src2ModIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),

                                                AMDGPU::OpName::src2_modifiers);

    auto I = MI.begin();

    std::advance(I, Src2ModIdx);

    MI.insert(I, MCOperand::createImm(0));

  }



  Size = Res ? (MaxInstBytesNum - Bytes.size()) : 0;
  Size = Res ? (MaxInstBytesNum - Bytes.size()) : 0;

  return Res;
  return Res;

}
}




const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const {
const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const {

  return getContext().getRegisterInfo()->
  return getContext().getRegisterInfo()->

    getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]);
    getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]);

}
}

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lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h
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MCObjectWriter *createAMDGPUELFObjectWriter(bool Is64Bit,
MCObjectWriter *createAMDGPUELFObjectWriter(bool Is64Bit,

                                            bool HasRelocationAddend,
                                            bool HasRelocationAddend,

                                            raw_pwrite_stream &OS);
                                            raw_pwrite_stream &OS);

} // End llvm namespace
} // End llvm namespace




#define GET_REGINFO_ENUM
#define GET_REGINFO_ENUM

#include "AMDGPUGenRegisterInfo.inc"
#include "AMDGPUGenRegisterInfo.inc"

#undef GET_REGINFO_ENUM




#define GET_INSTRINFO_ENUM
#define GET_INSTRINFO_ENUM

#define GET_INSTRINFO_OPERAND_ENUM

#include "AMDGPUGenInstrInfo.inc"
#include "AMDGPUGenInstrInfo.inc"

#undef GET_INSTRINFO_OPERAND_ENUM

#undef GET_INSTRINFO_ENUM






#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_ENUM

#include "AMDGPUGenSubtargetInfo.inc"
#include "AMDGPUGenSubtargetInfo.inc"

#undef GET_SUBTARGETINFO_ENUM




#endif
#endif

lib/Target/AMDGPU/SIMachineFunctionInfo.h
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//
//

//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//




#ifndef LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
#ifndef LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H

#define LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
#define LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H




#include "AMDGPUMachineFunction.h"
#include "AMDGPUMachineFunction.h"

#include "SIRegisterInfo.h"
#include "SIRegisterInfo.h"

#include "MCTargetDesc/AMDGPUMCTargetDesc.h"

#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/CodeGen/PseudoSourceValue.h"

#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCRegisterInfo.h"

#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/ErrorHandling.h"

#include <array>
#include <array>

#include <cassert>
#include <cassert>

#include <map>
#include <map>

#include <utility>
#include <utility>




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lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
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#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/StringRef.h"

#include "llvm/IR/CallingConv.h"
#include "llvm/IR/CallingConv.h"

#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrDesc.h"

#include "llvm/Support/Compiler.h"
#include "llvm/Support/Compiler.h"

#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/ErrorHandling.h"

#include <cstdint>
#include <cstdint>

#include <utility>
#include <utility>




#define GET_INSTRINFO_OPERAND_ENUM

#include "AMDGPUGenInstrInfo.inc"

#undef GET_INSTRINFO_OPERAND_ENUM



namespace llvm {
namespace llvm {




class FeatureBitset;
class FeatureBitset;

class Function;
class Function;

class GlobalValue;
class GlobalValue;

class MachineMemOperand;
class MachineMemOperand;

class MCContext;
class MCContext;

class MCRegisterClass;
class MCRegisterClass;

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lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
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#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/ErrorHandling.h"

#include "llvm/Support/MathExtras.h"
#include "llvm/Support/MathExtras.h"

#include <algorithm>
#include <algorithm>

#include <cassert>
#include <cassert>

#include <cstdint>
#include <cstdint>

#include <cstring>
#include <cstring>

#include <utility>
#include <utility>




#define GET_SUBTARGETINFO_ENUM
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"

#include "AMDGPUGenSubtargetInfo.inc"


#undef GET_SUBTARGETINFO_ENUM



#define GET_REGINFO_ENUM

#include "AMDGPUGenRegisterInfo.inc"

#undef GET_REGINFO_ENUM




#define GET_INSTRINFO_NAMED_OPS
#define GET_INSTRINFO_NAMED_OPS

#define GET_INSTRINFO_ENUM

#include "AMDGPUGenInstrInfo.inc"
#include "AMDGPUGenInstrInfo.inc"

#undef GET_INSTRINFO_NAMED_OPS
#undef GET_INSTRINFO_NAMED_OPS

#undef GET_INSTRINFO_ENUM




namespace {
namespace {




/// \returns Bit mask for given bit \p Shift and bit \p Width.
/// \returns Bit mask for given bit \p Shift and bit \p Width.

unsigned getBitMask(unsigned Shift, unsigned Width) {
unsigned getBitMask(unsigned Shift, unsigned Width) {

  return ((1 << Width) - 1) << Shift;
  return ((1 << Width) - 1) << Shift;

}
}




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lib/Target/AMDGPU/VOP2Instructions.td
Show First 20 Lines • Show All 175 Lines • ▼ Show 20 Linesclass VOP_MADMK <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> {

  field dag Ins32 = (ins VCSrc_f32:$src0, ImmOpType:$imm, VGPR_32:$src1);
  field dag Ins32 = (ins VCSrc_f32:$src0, ImmOpType:$imm, VGPR_32:$src1);

  field string Asm32 = "$vdst, $src0, $imm, $src1";
  field string Asm32 = "$vdst, $src0, $imm, $src1";

  field bit HasExt = 0;
  field bit HasExt = 0;

}
}




def VOP_MADMK_F16 : VOP_MADMK <f16>;
def VOP_MADMK_F16 : VOP_MADMK <f16>;

def VOP_MADMK_F32 : VOP_MADMK <f32>;
def VOP_MADMK_F32 : VOP_MADMK <f32>;




// FIXME: Remove src2_modifiers. It isn't used, so is wasting memory

// and processing time but it makes it easier to convert to mad.

class VOP_MAC <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> {
class VOP_MAC <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> {

  let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VGPR_32:$src2);
  let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VGPR_32:$src2);

  let Ins64 = getIns64<Src0RC64, Src1RC64, RegisterOperand<VGPR_32>, 3,
  let Ins64 = getIns64<Src0RC64, Src1RC64, RegisterOperand<VGPR_32>, 3,

                       HasModifiers, HasOMod, Src0Mod, Src1Mod, Src2Mod>.ret;
                       HasModifiers, HasOMod, Src0Mod, Src1Mod, Src2Mod>.ret;

  let InsDPP = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
  let InsDPP = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0,

                    Src1ModDPP:$src1_modifiers, Src1DPP:$src1,
                    Src1ModDPP:$src1_modifiers, Src1DPP:$src1,

                    VGPR_32:$src2, // stub argument
                    VGPR_32:$src2, // stub argument

                    dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
                    dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,

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test/MC/Disassembler/AMDGPU/mac.txt
  • This file was added.
# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI



# VI: v_mac_f32_e64 v0, v1, v2 mul:2  ; encoding: [0x00,0x00,0x16,0xd1,0x01,0x05,0x02,0x08]

0x00 0x00 0x16 0xd1 0x01 0x05 0x02 0x08



# VI: v_mac_f32_e64 v0, v1, v2 clamp  ; encoding: [0x00,0x80,0x16,0xd1,0x01,0x05,0x02,0x00]

0x00 0x80 0x16 0xd1 0x01 0x05 0x02 0x00



# VI: v_mac_f32_e64 v0, v1, v2 clamp mul:2 ; encoding: [0x00,0x80,0x16,0xd1,0x01,0x05,0x02,0x08]

0x00 0x80 0x16 0xd1 0x01 0x05 0x02 0x08



# VI: v_mac_f16_e64 v0, v1, v2 mul:2  ; encoding: [0x00,0x00,0x23,0xd1,0x01,0x05,0x02,0x08]

0x00 0x00 0x23 0xd1 0x01 0x05 0x02 0x08



# VI: v_mac_f16_e64 v0, v1, v2 clamp  ; encoding: [0x00,0x80,0x23,0xd1,0x01,0x05,0x02,0x00]

0x00 0x80 0x23 0xd1 0x01 0x05 0x02 0x00



# VI: v_mac_f16_e64 v0, v1, v2 clamp mul:2 ; encoding: [0x00,0x80,0x23,0xd1,0x01,0x05,0x02,0x08]

0x00 0x80 0x23 0xd1 0x01 0x05 0x02 0x08