[AntiDepBreaker] Use liveins as well in StartBlock

[timshen]

Summary

Only calling getPristineRegs() is not sufficient, considering shrink wrapping puts
registers not saved in certain blocks. Use explicit isLiveIn instead.

This fixes pr32292.

[timshen]

About the test:

I tried to reduce the test, but as soon as the complexity gets smaller (not by much), the symptom disappears. I deliberately didn't shrink the test, and posted here to see if you think it's Ok to keep.

[hfinkel]

I see only 5 uses of getPristineRegs, two you're removing here from the anti-dep breakers, one in MachineVerifier, and two in asserts in ARM frame lowering. Should we remove it completely? Update it with the logic you're adding here?

llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp

166

Should this return an Optional (or similar)? It seems unfortunate to check MF.getFrameInfo().isCalleeSavedInfoValid() here and also check MFI.isCalleeSavedInfoValid() in the if below.

[timshen]

Don't do redundant check.

[timshen]

llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp

166

Good catch! I turned the first isCalleeSavedInfoValid into an assert, since it's guarded by the second call.

[MatzeB]

llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp

165

Please do not use auto in context where the type is not immediately obvious. (A reader has to lookup that getFrameInfo() does return a MachineFrameInfo here, it is not immediately obvious). A few more of these below.

175

I don't think this pass will (or should) be used before the prolog epilog inserter so isCalleeSavedInfoValid() should always be true and you could simply assert on it.

176

Adding isLiveIn() here looks wrong given that the code is already adding the live ins of the successors above (which is the way to compute the live-outs of this block). This should already be fine if the code is walking the block backwards afterwards.

Seeing this I would assume we walk the blocks backwards and starting with the live-outs so adding the live-ins would not make sense.

llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp

83–84

see above.

[MatzeB]

llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp

167–172

This looks like you are replacing the check for pristine regs with manually written code that does the same. Am I missing something?

[timshen]

llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp

175

I didn't assert on this, only because of https://github.com/llvm-mirror/llvm/blob/6095a7948d32d712811e8c2ab2190acf8e66a8bc/lib/CodeGen/PrologEpilogInserter.cpp#L66

It appears that CSInfo is valid only if doSpillCalleeSavedRegs is executed.

Is it always the case where usesPhysRegsForPEI is necessary for post-RA scheduling?

176

Looking at https://github.com/llvm-project/llvm-project/blob/master/llvm/lib/CodeGen/PostRASchedulerList.cpp#L331

The blocks are just traversed without an explicit order.

I'll take a closer look at StartBlock. I was more or less confused by its intention.

[timshen]

llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp

167–172

This is because of Quentin's comment in the bug:

I would just resort on live ins information, if at all possible.
If not possible I would work toward making that possible :).

I did it without fully understanding the big picture. :P

It'd be good to have you or someone explain the big picture. :)

[MatzeB]

llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp

175

Ah, that is special behavior for webassembly which keeps using vregs long after register allocation is done. I don't think we should concern ourself with that here as this pass doesn't seem to be compatible with that anyway (a bunch of passes are not and webassembly just isn't using them).

[timshen]

Preserve the use of getPristineRegs() for now.

[timshen]

As discussed in the bug, I'll preserve the use of getPristineRegs() in this patch. And many of your comments don't apply anymore. :)

[qcolombet]

llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp

167–172

Yeah what I was saying is that is we can use isLiveIn alone we should do that.
If we cannot, the long run should be to get rid of the pristine stuff (i.e., just resort on isLiveIn to convey the right information).
I don't expect this patch to fix that :).

llvm/test/CodeGen/PowerPC/pr32292.ll

1 ↗

(On Diff #92510)

Using a .mir test case you should be able to reduce the test even more.

1 ↗

(On Diff #92510)

Please use a more descriptive name for the filename. List the PR in the file if you want.

[timshen]

llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp

167–172

I see.

I was clear whether I need to do anything (e.g. remove this use site) or not. :)

[timshen]

Reduce to a smaller test case.

[timshen]

Rename the test.

[timshen]

llvm/test/CodeGen/PowerPC/pr32292.ll

1 ↗

(On Diff #92510)

I didn't use .mir, but got a much smaller test case.

1 ↗

(On Diff #92510)

Renamed.

[timshen]

Ping? :)

[qcolombet]

Hi Tim,

LGTM.
Out-of-curiosity, what is missing to use a .mir test instead of the .ll test?

I expect a .mir to be more robust against changes.

Cheers,
-Quentin

[timshen]

Hi Quentin,

Oh you mean turn this IR test into a mir test? I don't know how to use mir to reduce the test for even more (I used bugpoint on IR test).

I can turn the test to a mir test.

[qcolombet]

Oh you mean turn this IR test into a mir test?

Yes.

Use -stop-before <ExeDepPassDEBUG_TYPE> to produce the .mir input.
Then, you should be able to reproduce the problem with that input and -run-pass <ExeDepPassDEBUG_TYPE>

[timshen]

Update the test to .mir.

Also fix a mir parser bug, parsing nulls as constants.

[echristo]

Committed thusly:

echristo@athyra ~/s/llvm> git svn dcommit
Committing to https://llvm.org/svn/llvm-project/llvm/trunk ...
M lib/AsmParser/LLParser.cpp
M lib/CodeGen/AggressiveAntiDepBreaker.cpp
M lib/CodeGen/CriticalAntiDepBreaker.cpp
Committed r299124

and... here:

echristo@athyra ~/s/llvm> git svn dcommit
Committing to https://llvm.org/svn/llvm-project/llvm/trunk ...
A test/CodeGen/PowerPC/pristine-and-livein.mir
Committed r299125

*sigh*

[MatzeB]

In D31188#714712, @echristo wrote:

Committed thusly:

echristo@athyra ~/s/llvm> git svn dcommit
Committing to https://llvm.org/svn/llvm-project/llvm/trunk ...
M lib/AsmParser/LLParser.cpp
M lib/CodeGen/AggressiveAntiDepBreaker.cpp
M lib/CodeGen/CriticalAntiDepBreaker.cpp
Committed r299124

and... here:

echristo@athyra ~/s/llvm> git svn dcommit
Committing to https://llvm.org/svn/llvm-project/llvm/trunk ...
A test/CodeGen/PowerPC/pristine-and-livein.mir
Committed r299125

*sigh*

FWIW: I am pretty sure "getPristineRegs is not accurately considering shrink wrapping puts registers not saved in certain blocks." as mentioned in the commit message is not true! getPristineRegs() doesn't have to do that!

I also don't understand the fix here: Adding live-in registers when the code here appears to be searching for live-out registers seem like an odd fix to me (I can see how it helps though as it will just mark more registers as occupied).

[echristo]

Totally happy to pull it back if you'd like, was just going on what Quentin said to do.

-eric

[timshen]

In D31188#718346, @MatzeB wrote:

In D31188#714712, @echristo wrote:

Committed thusly:

echristo@athyra ~/s/llvm> git svn dcommit
Committing to https://llvm.org/svn/llvm-project/llvm/trunk ...
M lib/AsmParser/LLParser.cpp
M lib/CodeGen/AggressiveAntiDepBreaker.cpp
M lib/CodeGen/CriticalAntiDepBreaker.cpp
Committed r299124

and... here:

echristo@athyra ~/s/llvm> git svn dcommit
Committing to https://llvm.org/svn/llvm-project/llvm/trunk ...
A test/CodeGen/PowerPC/pristine-and-livein.mir
Committed r299125

*sigh*

FWIW: I am pretty sure "getPristineRegs is not accurately considering shrink wrapping puts registers not saved in certain blocks." as mentioned in the commit message is not true! getPristineRegs() doesn't have to do that!

Sounds fair, I fixed the description.

I also don't understand the fix here: Adding live-in registers when the code here appears to be searching for live-out registers seem like an odd fix to me (I can see how it helps though as it will just mark more registers as occupied).

This is based on my inderstanding on "ideal liveins()" I mentioned in the bug:

/* Returns all live-ins, including the unspilled callee-saved registers. */
iterator_range<concat_iterator<...>> liveins();

The fix turns "Pristine.test(Reg)" into "Pristine.test(Reg) || BB.IsLiveIn(Reg)" as a refinement (to match the ideal definition of liveins()).

It means that not only those callee-saved registers (we are iterating over only them) who don't have spill slots are considered, but also those who “have spill slots but not spilled”.

[timshen]

In D31188#718346, @MatzeB wrote:

In D31188#714712, @echristo wrote:

Committed thusly:

echristo@athyra ~/s/llvm> git svn dcommit
Committing to https://llvm.org/svn/llvm-project/llvm/trunk ...
M lib/AsmParser/LLParser.cpp
M lib/CodeGen/AggressiveAntiDepBreaker.cpp
M lib/CodeGen/CriticalAntiDepBreaker.cpp
Committed r299124

and... here:

echristo@athyra ~/s/llvm> git svn dcommit
Committing to https://llvm.org/svn/llvm-project/llvm/trunk ...
A test/CodeGen/PowerPC/pristine-and-livein.mir
Committed r299125

*sigh*

FWIW: I am pretty sure "getPristineRegs is not accurately considering shrink wrapping puts registers not saved in certain blocks." as mentioned in the commit message is not true! getPristineRegs() doesn't have to do that!

I also don't understand the fix here: Adding live-in registers when the code here appears to be searching for live-out registers seem like an odd fix to me (I can see how it helps though as it will just mark more registers as occupied).

Also, the new behavior matches the intention in the comment:

In non-return this is any callee-saved register that is not saved in the prolog.

To be fair I don't yet understand why it thinks this is the right thing to do, but I trust that the intention is accurrate, only the code was not.

[MatzeB]

I also don't understand the fix here: Adding live-in registers when the code here appears to be searching for live-out registers seem like an odd fix to me (I can see how it helps though as it will just mark more registers as occupied).

This is based on my inderstanding on "ideal liveins()" I mentioned in the bug:

/* Returns all live-ins, including the unspilled callee-saved registers. */
iterator_range<concat_iterator<...>> liveins();

The fix turns "Pristine.test(Reg)" into "Pristine.test(Reg) || BB.IsLiveIn(Reg)" as a refinement (to match the ideal definition of liveins()).

It means that not only those callee-saved registers (we are iterating over only them) who don't have spill slots are considered, but also those who “have spill slots but not spilled”.

Pristine.test(Reg) || BB.IsLiveIn(Reg) would make a lot of sense when searching for live-ins. But the comments around it indicate it is actually searching for live-outs?

For live-outs you need to:

• Take the union of the successor live-ins + pristines
• In case of the return block without successors take all callee saved register instead

(you may referer to LivePhysRegs::addLiveOuts() / LivePHysRegs::addLiveIns() to see an alternative implementation of this).

From reading the code here the AntiDepBreaker is already doing the right thing. I only read the code though, and did not actually run/play with it so I may have missed something.

[timshen]

In D31188#718616, @MatzeB wrote:

I also don't understand the fix here: Adding live-in registers when the code here appears to be searching for live-out registers seem like an odd fix to me (I can see how it helps though as it will just mark more registers as occupied).

This is based on my inderstanding on "ideal liveins()" I mentioned in the bug:

/* Returns all live-ins, including the unspilled callee-saved registers. */
iterator_range<concat_iterator<...>> liveins();

The fix turns "Pristine.test(Reg)" into "Pristine.test(Reg) || BB.IsLiveIn(Reg)" as a refinement (to match the ideal definition of liveins()).

It means that not only those callee-saved registers (we are iterating over only them) who don't have spill slots are considered, but also those who “have spill slots but not spilled”.

Pristine.test(Reg) || BB.IsLiveIn(Reg) would make a lot of sense when searching for live-ins. But the comments around it indicate it is actually searching for live-outs?

Not for all live-outs, but only for "live-out callee-saved registers".

The code wants to do something on all non-spilled callee-saved registers that are live-outs of the current block. Without considering shrink wrapping, I picture that the correct behavior should be:

1. Epilogue blocks and returning blocks have all callee-saved registers live-out. Handle all of them.
2. Prologue blocks have all callee-saved registers that are spilled. Handle callee-saved registers that are pristine.
3. For the rest of the blocks, a callee-saved register is either not live, or live-through. Handle live-in callee-saved registers.

The behavior was matching my picture, only if all epilogue blocks are returning blocks.

After considering shrink wrapping, things change. Ideally:

1. All blocks before prologue, excluding prologue, have all callee-saved registers live-out.
2. All blocks after epilogue, including epilogue, have all callee-saved registers live-out.
3. For the rest of the blocks, a callee-saved register is either not live, or live-through; pristine registers are precisely live-out callee-saved registers.

Let's see what information we have (I haven't verified yet):

1. For all blocks before prologue, including prologue, shrink wrapping marks all callee-saved registers live-in.
2. For all blocks after epilogue, excluding epilogue, shrink wrapping marks all-callee-saved registers live-in.

I think my fix is wrong about prologues and epilogues, but correct for other blocks. I think that your suggestion is the correct fix, that is looking at the live-ins of the successors. I'll do that.

Do you think that we should keep this patch in the mean time? This patch makes some of the correct cases overly-conservative (but not wrong), and fixes some of the wrong cases. It doesn't make any correct cases wrong. Feel free to revert it if you don't think so.

I'm on vacation until April 15th, so I'll work on it after that. :)

[MatzeB]

Just found the time to look at this a bit:

The thing that is wrong here is the live-in list of bb.2. bb.2 is a return block without any restore instructions in it so it must have the %x29 as a live-in. So it seems the actual problem lies before the DepBreakers here.

I tried reproducing the earlier passes by copying the IR out of the mir test and re-running it on that, but I only always seem to get a version with a single return block without shrink wrapping...

[timshen]

In D31188#725545, @MatzeB wrote:

Just found the time to look at this a bit:

The thing that is wrong here is the live-in list of bb.2. bb.2 is a return block without any restore instructions in it so it must have the %x29 as a live-in. So it seems the actual problem lies before the DepBreakers here.

Good catch!

After some investigation, I found that line:

https://github.com/llvm-mirror/llvm/blob/8c6e6605aa4b10ac5c3e3afc4e87361c2ac1ff9d/lib/CodeGen/BranchFolding.cpp#L391

computeLiveIns() doesn't add r29 and r30 into NewMBB's liveins. I believe that computeLiveIns is doing what it's intended to do (add liveins based on instructions), so we should change the caller side to propagate CSR live-ins.

I tried reproducing the earlier passes by copying the IR out of the mir test and re-running it on that, but I only always seem to get a version with a single return block without shrink wrapping...

[timshen]

In D31188#728097, @timshen wrote:

so we should change the caller side to propagate CSR live-ins.

I'm not sure how to do this -

when splitting a block B to C and D, where C unconditionally jumps (or falls through) to D, how to compute D's liveins, including CSRs?

B could be any block -

1. before save point, CSRs live-through.
2. save point, CSRs live-in, dead-out.
3. between save point and restore point, CSRs are considered normal registers.
4. restore point, CSRs dead-in, live-out.
5. after restore point, CSRs live-through.

If the only information are the liveins(), it seems not easy to tell liveness at the split position. Do we want to use LiveIntervals in BranchFolding.cpp?

[MatzeB]

Ok, now that r303938 / https://reviews.llvm.org/D32464 has landed could you please double check and then revert this?

[MatzeB]

In D31188#765178, @MatzeB wrote:

Ok, now that r303938 / https://reviews.llvm.org/D32464 has landed could you please double check and then revert this?

You can hold off with this for now, somehow I broke some clang stage2 bots with that commit and I first have to investigate why.

[MatzeB]

In D31188#765330, @MatzeB wrote:

In D31188#765178, @MatzeB wrote:

Ok, now that r303938 / https://reviews.llvm.org/D32464 has landed could you please double check and then revert this?

You can hold off with this for now, somehow I broke some clang stage2 bots with that commit and I first have to investigate why.

I re-landed the patch with a fix and it seems to be fine now. I also filed http://llvm.org/PR33182 to document a MachineVerifier shortcoming of catching a case like this.

[timshen]

In D31188#765178, @MatzeB wrote:

Ok, now that r303938 / https://reviews.llvm.org/D32464 has landed could you please double check and then revert this?

D32464 doesn't seem to fix this test case - I ran pass post-RA-sched on this test case, and got bb.2.if.then not having X29 as live-in. Can you take a look?

[MatzeB]

In D31188#766326, @timshen wrote:

In D31188#765178, @MatzeB wrote:

Ok, now that r303938 / https://reviews.llvm.org/D32464 has landed could you please double check and then revert this?

D32464 doesn't seem to fix this test case - I ran pass post-RA-sched on this test case, and got bb.2.if.then not having X29 as live-in. Can you take a look?

The original testcase? The mir test in the repository already has the invalid livein lists from the earlier branch folding.

[timshen]

In D31188#766336, @MatzeB wrote:

In D31188#766326, @timshen wrote:

In D31188#765178, @MatzeB wrote:

Ok, now that r303938 / https://reviews.llvm.org/D32464 has landed could you please double check and then revert this?

D32464 doesn't seem to fix this test case - I ran pass post-RA-sched on this test case, and got bb.2.if.then not having X29 as live-in. Can you take a look?

The original testcase? The mir test in the repository already has the invalid livein lists from the earlier branch folding.

Yes you are right. Posted D33697 to revert.

llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp

for (const auto &LI : (*SI)->liveins()) {
         DefIndices[Reg] = ~0u;
       }
     }
 
   // Mark live-out callee-saved registers. In a return block this is
   // all callee-saved registers. In non-return this is any
   // callee-saved register that is not saved in the prolog.
   const MachineFrameInfo &MFI = MF.getFrameInfo();
   BitVector Pristine = MFI.getPristineRegs(MF);
   for (const MCPhysReg *I = MF.getRegInfo().getCalleeSavedRegs(); *I;
        ++I) {
     unsigned Reg = *I;
-    if (!IsReturnBlock && !Pristine.test(Reg)) continue;
+    if (!IsReturnBlock && !(Pristine.test(Reg) || BB->isLiveIn(Reg)))
+      continue;
     for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
       unsigned AliasReg = *AI;
       State->UnionGroups(AliasReg, 0);
       KillIndices[AliasReg] = BB->size();
       DefIndices[AliasReg] = ~0u;
     }
   }
 }
 
 void AggressiveAntiDepBreaker::FinishBlock() {
   delete State;
   State = nullptr;
 }
 

llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp

void CriticalAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
 
   // Mark live-out callee-saved registers. In a return block this is
   // all callee-saved registers. In non-return this is any
   // callee-saved register that is not saved in the prolog.
   const MachineFrameInfo &MFI = MF.getFrameInfo();
   BitVector Pristine = MFI.getPristineRegs(MF);
   for (const MCPhysReg *I = MF.getRegInfo().getCalleeSavedRegs(); *I;
        ++I) {
-    if (!IsReturnBlock && !Pristine.test(*I)) continue;
+    unsigned Reg = *I;
+    if (!IsReturnBlock && !(Pristine.test(Reg) || BB->isLiveIn(Reg)))
+      continue;
     for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) {
       unsigned Reg = *AI;
       Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
       KillIndices[Reg] = BBSize;
       DefIndices[Reg] = ~0u;
     }
   }
 }
 
 void CriticalAntiDepBreaker::FinishBlock() {
   RegRefs.clear();
   KeepRegs.reset();
 }
 

llvm/test/CodeGen/PowerPC/pristine-and-livein.ll

+; RUN: llc < %s | FileCheck %s
+target datalayout = "e-m:e-i64:64-n32:64"
+target triple = "powerpc64le--linux-gnu"
+
+; See pr32292 for details.
+
+; REG, which is clobbered by an li instruction, shouldn't be a callee-saved
+; register.
+; CHECK-LABEL: test
+; CHECK: li [[REG:[0-9]+]], 0
+; CHECK-NOT: std [[REG]],
+define i64 @test(i64 %adler, i8* readonly %buf, i64 %len) {
+entry:
+  %shr = lshr i64 %adler, 16
+  %and = and i64 %shr, 65535
+  %and1 = and i64 %adler, 65535
+  br i1 undef, label %if.then, label %if.end11
+
+if.then:                                          ; preds = %entry
+  %add = add nuw nsw i64 %and1, 0
+  %sub = add nsw i64 %add, -65521
+  %sub.add = select i1 undef, i64 %sub, i64 %add
+  %add5 = add nsw i64 %sub.add, %and
+  %sum2.0 = select i1 false, i64 undef, i64 %add5
+  %shl = shl i64 %sum2.0, 16
+  %or = or i64 %shl, %sub.add
+  br label %cleanup
+
+if.end11:                                         ; preds = %entry
+  br label %if.end15
+
+if.end15:                                         ; preds = %if.end11
+  br i1 undef, label %while.cond.preheader, label %while.cond30.preheader
+
+while.cond30.preheader:                           ; preds = %if.end15
+  br label %while.body33
+
+while.cond.preheader:                             ; preds = %if.end15
+  %sub25.adler.addr.1 = select i1 false, i64 undef, i64 %and1
+  %rem = urem i64 %and, 65521
+  %shl27 = shl nuw nsw i64 %rem, 16
+  %or28 = or i64 %shl27, %sub25.adler.addr.1
+  br label %cleanup
+
+while.body33:                                     ; preds = %do.end, %while.cond30.preheader
+  %len.addr.1384 = phi i64 [ %sub34, %do.end ], [ %len, %while.cond30.preheader ]
+  %adler.addr.3382 = phi i64 [ %rem101, %do.end ], [ %and1, %while.cond30.preheader ]
+  %sub34 = add i64 %len.addr.1384, -5552
+  %tmp12 = load i8, i8* null
+  %conv36 = zext i8 %tmp12 to i64
+  %add37 = add i64 %adler.addr.3382, %conv36
+  %add41 = add i64 %add37, 0
+  %tmp14 = load i8, i8* undef
+  %conv44 = zext i8 %tmp14 to i64
+  %add45 = add i64 %add41, %conv44
+  %arrayidx47 = getelementptr inbounds i8, i8* null, i64 3
+  %tmp15 = load i8, i8* %arrayidx47
+  %conv48 = zext i8 %tmp15 to i64
+  %add49 = add i64 %add45, %conv48
+  %add53 = add i64 %add49, 0
+  %add57 = add i64 %add53, 0
+  %add61 = add i64 %add57, 0
+  %add65 = add i64 %add61, 0
+  %add69 = add i64 %add65, 0
+  %arrayidx71 = getelementptr inbounds i8, i8* null, i64 9
+  %tmp21 = load i8, i8* %arrayidx71
+  %conv72 = zext i8 %tmp21 to i64
+  %add73 = add i64 %add69, %conv72
+  %arrayidx75 = getelementptr inbounds i8, i8* null, i64 10
+  %tmp22 = load i8, i8* %arrayidx75
+  %conv76 = zext i8 %tmp22 to i64
+  %add77 = add i64 %add73, %conv76
+  %add81 = add i64 %add77, 0
+  %arrayidx83 = getelementptr inbounds i8, i8* null, i64 12
+  %tmp24 = load i8, i8* %arrayidx83
+  %conv84 = zext i8 %tmp24 to i64
+  %add85 = add i64 %add81, %conv84
+  %add89 = add i64 %add85, 0
+  %add93 = add i64 %add89, 0
+  %add97 = add i64 %add93, 0
+  br label %do.end
+
+do.end:                                           ; preds = %while.body33
+  %rem101 = urem i64 %add97, 65521
+  %cmp31 = icmp ugt i64 %sub34, 5551
+  br i1 %cmp31, label %while.body33, label %while.end103
+
+while.end103:                                     ; preds = %do.end
+  br label %while.cond106.preheader
+
+while.cond106.preheader:                          ; preds = %while.end103
+  br i1 undef, label %while.body109.preheader, label %while.body180.preheader
+
+while.body180.preheader:                          ; preds = %while.cond106.preheader
+  %tmp28 = add i64 %sub34, -1
+  br label %while.body180.prol
+
+while.body180.prol:                               ; preds = %while.body180.prol, %while.body180.preheader
+  %adler.addr.6366.prol = phi i64 [ %add183.prol, %while.body180.prol ], [ %rem101, %while.body180.preheader ]
+  %add183.prol = add i64 %adler.addr.6366.prol, 0
+  %add184.prol = add i64 %add183.prol, 0
+  br i1 undef, label %while.body180.prol.loopexit.unr-lcssa, label %while.body180.prol
+
+while.body180.prol.loopexit.unr-lcssa:            ; preds = %while.body180.prol
+  %tmp30 = icmp ult i64 %tmp28, 7
+  %rem186 = urem i64 %add183.prol, 65521
+  %rem187 = urem i64 %add184.prol, 65521
+  %shl189 = shl nuw nsw i64 %rem187, 16
+  %or190 = or i64 %shl189, %rem186
+  br label %cleanup
+
+while.body109.preheader:                          ; preds = %while.cond106.preheader
+  unreachable
+
+cleanup:                                          ; preds = %while.body180.prol.loopexit.unr-lcssa, %while.cond.preheader, %if.then
+  %retval.0 = phi i64 [ %or, %if.then ], [ %or28, %while.cond.preheader ], [ %or190, %while.body180.prol.loopexit.unr-lcssa ]
+  ret i64 %retval.0
+}