[DAGCombiner] allow transforming (select Cond, C +/- 1, C) to (add(ext Cond), C)

[spatel]

Summary

select Cond, C +/- 1, C --> add(ext Cond), C -- with a target hook.

This is part of the ongoing process to obsolete D24480.

PowerPC is an obvious winner for this kind of transform because it has fast and complete bit-twiddling abilities but generally lousy conditional execution perf (although this might have changed in recent implementations).

x86 also sees some wins, but the effect is limited because these transforms already mostly exist in its target-specific combineSelectOfTwoConstants(). The fact that we see any x86 changes just shows that that code is a mess of special-case holes. We may be able to remove some of that logic if this goes in.

My guess is that other targets will want to enable this hook for most cases. The likely follow-ups would be to add value type and/or the constants themselves as parameters for the hook. As the tests in select_const.ll show, we can transform any select-of-constants to math/logic, but the general transform for any 2 constants needs one more instruction (multiply or 'and').

ARM is one target that I think may not want this for most cases. I see infinite loops there because it wants to use selects to enable conditionally executed instructions.

[efriedma]

All of the testcase changes you're showing here involve a select where the condition is a TRUNCATE (so the extension is free, so it's profitable to transform on all platforms). Does this have any impact on the more common patterns, like SELECT(SETCC)?

[spatel]

In D30537#690878, @efriedma wrote:

All of the testcase changes you're showing here involve a select where the condition is a TRUNCATE (so the extension is free, so it's profitable to transform on all platforms). Does this have any impact on the more common patterns, like SELECT(SETCC)?

Excellent question...

For x86, if we have a setcc node, then everything I've tried so far that would be affected by this patch would also be caught in the target-specific combineSelectOfTwoConstants(), so there's no output difference.

For PPC, the code in this patch will fire too, but there is code that reverses the transform:

PPC DAG preprocessing replacing:
Old:    t20: i64 = add t19, Constant:i64<41>
New: t28: i64 = select t8, Constant:i64<42>, Constant:i64<41>

...so <tears forming>, we end up with isel -- or worse cmp/br. And so again, there is no output difference.

So the answer to your question for x86 and PPC (for different reasons) is: no, there is no impact on the common cases AFAICT.

[efriedma]

Okay. Given that, why do we want to do this? Does it allow some useful refactoring of other code?

[spatel]

In D30537#691206, @efriedma wrote:

Okay. Given that, why do we want to do this? Does it allow some useful refactoring of other code?

I haven't looked much at anything besides x86, but yes, at least for that target, we can eliminate custom code and plug the holes that are visible in this patch and probably others. My main motivation is that by putting this fold into the common DAGCombiner code any target will be able to pick it up easily. And that will help ease the restoration for the InstCombine that we currently only have half of:
https://reviews.llvm.org/rL75531
https://reviews.llvm.org/rL159230
...so the ultimate goal is to standardize the patterns in IR (we'll always canonicalize to select when possible) and then have a standard way to transform selects to math/logic here in codegen.

[efriedma]

Okay, then it looks fine.

include/llvm/Target/TargetLowering.h

if (hasMultipleConditionRegisters())
       return false;
     // Only do the transform if the value won't be split into multiple
     // registers.
     LegalizeTypeAction Action = getTypeAction(Context, VT);
     return Action != TypeExpandInteger && Action != TypeExpandFloat &&
       Action != TypeSplitVector;
   }
 
+  /// Return true if a select of constants (select Cond, C1, C2) should be
+  /// transformed into simple math ops with the condition value. For example:
+  /// select Cond, C1, C1-1 --> add (zext Cond), C1-1
+  virtual bool convertSelectOfConstantsToMath() const {
+    return false;
+  }
+
   //===--------------------------------------------------------------------===//
   // TargetLowering Configuration Methods - These methods should be invoked by
   // the derived class constructor to configure this object for the target.
   //
 protected:
   /// Specify how the target extends the result of integer and floating point
   /// boolean values from i1 to a wider type.  See getBooleanContents.
   void setBooleanContents(BooleanContent Ty) {

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

SDValue DAGCombiner::foldSelectOfConstants(SDNode *N) {
   auto *C2 = dyn_cast<ConstantSDNode>(N2);
   if (!C1 || !C2)
     return SDValue();
 
   // Only do this before legalization to avoid conflicting with target-specific
   // transforms in the other direction (create a select from a zext/sext). There
   // is also a target-independent combine here in DAGCombiner in the other
   // direction for (select Cond, -1, 0) when the condition is not i1.
-  // TODO: This could be generalized for any 2 constants that differ by 1:
-  // add ({s/z}ext Cond), C
   if (CondVT == MVT::i1 && !LegalOperations) {
     if (C1->isNullValue() && C2->isOne()) {
       // select Cond, 0, 1 --> zext (!Cond)
       SDValue NotCond = DAG.getNOT(DL, Cond, MVT::i1);
       if (VT != MVT::i1)
         NotCond = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, NotCond);
       return NotCond;
     }
if (C1->isOne() && C2->isNullValue()) {
       return Cond;
     }
     if (C1->isAllOnesValue() && C2->isNullValue()) {
       // select Cond, -1, 0 --> sext (Cond)
       if (VT != MVT::i1)
         Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, Cond);
       return Cond;
     }
+
+    // For any constants that differ by 1, we can transform the select into an
+    // extend and add. Use a target hook because some targets may prefer to
+    // transform in the other direction.
+    if (TLI.convertSelectOfConstantsToMath()) {
+      if (C1->getAPIntValue() - 1 == C2->getAPIntValue()) {
+        // select Cond, C1, C1-1 --> add (zext Cond), C1-1
+        if (VT != MVT::i1)
+          Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Cond);
+        return DAG.getNode(ISD::ADD, DL, VT, Cond, N2);
+      }
+      if (C1->getAPIntValue() + 1 == C2->getAPIntValue()) {
+        // select Cond, C1, C1+1 --> add (sext Cond), C1+1
+        if (VT != MVT::i1)
+          Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, Cond);
+        return DAG.getNode(ISD::ADD, DL, VT, Cond, N2);
+      }
+    }
+
     return SDValue();
   }
 
   // fold (select Cond, 0, 1) -> (xor Cond, 1)
   // We can't do this reliably if integer based booleans have different contents
   // to floating point based booleans. This is because we can't tell whether we
   // have an integer-based boolean or a floating-point-based boolean unless we
   // can find the SETCC that produced it and inspect its operands. This is

lib/Target/PowerPC/PPCISelLowering.h

public:
 
     bool isFPExtFree(EVT VT) const override;
 
     /// \brief Returns true if it is beneficial to convert a load of a constant
     /// to just the constant itself.
     bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
                                            Type *Ty) const override;
 
+    bool convertSelectOfConstantsToMath() const override {
+      return true;
+    }
+
     bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
 
     bool getTgtMemIntrinsic(IntrinsicInfo &Info,
                             const CallInst &I,
                             unsigned Intrinsic) const override;
 
     /// getOptimalMemOpType - Returns the target specific optimal type for load
     /// and store operations as a result of memset, memcpy, and memmove

lib/Target/X86/X86ISelLowering.h

bool isScalarFPTypeInSSEReg(EVT VT) const {
              (VT == MVT::f32 && X86ScalarSSEf32);   // f32 is when SSE1
     }
 
     /// \brief Returns true if it is beneficial to convert a load of a constant
     /// to just the constant itself.
     bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
                                            Type *Ty) const override;
 
+    bool convertSelectOfConstantsToMath() const override {
+      return true;
+    }
+
     /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
     /// with this index.
     bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const override;
 
     /// Intel processors have a unified instruction and data cache
     const char * getClearCacheBuiltinName() const override {
       return nullptr; // nothing to do, move along.
     }

test/CodeGen/PowerPC/crbits.ll

 
 define signext i32 @exttest7(i32 signext %a) #0 {
 entry:
   %cmp = icmp eq i32 %a, 5
   %cond = select i1 %cmp, i32 7, i32 8
   ret i32 %cond
 
 ; CHECK-LABEL: @exttest7
-; CHECK-DAG: cmplwi {{[0-9]+}}, 3, 5
+; CHECK-DAG: cmpwi {{[0-9]+}}, 3, 5
 ; CHECK-DAG: li [[REG1:[0-9]+]], 8
 ; CHECK-DAG: li [[REG2:[0-9]+]], 7
 ; CHECK: isel 3, [[REG2]], [[REG1]],
 ; CHECK-NOT: rldicl
 ; CHECK: blr
 }
 
 define zeroext i32 @exttest8() #0 {

test/CodeGen/PowerPC/select_const.ll

 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i32 -1, i32 0
   ret i32 %sel
 }
 
 ; select Cond, C+1, C --> add (zext Cond), C
 
 define i32 @select_Cplus1_C(i1 %cond) {
-; ISEL-LABEL: select_Cplus1_C:
-; ISEL:       # BB#0:
-; ISEL-NEXT:    andi. 3, 3, 1
-; ISEL-NEXT:    li 4, 42
-; ISEL-NEXT:    li 3, 41
-; ISEL-NEXT:    isel 3, 4, 3, 1
-; ISEL-NEXT:    blr
-;
-; NO_ISEL-LABEL: select_Cplus1_C:
-; NO_ISEL:       # BB#0:
-; NO_ISEL-NEXT:    andi. 3, 3, 1
-; NO_ISEL-NEXT:    li 4, 42
-; NO_ISEL-NEXT:    li 3, 41
-; NO_ISEL-NEXT:    bc 12, 1, .LBB12_1
-; NO_ISEL-NEXT:    blr
-; NO_ISEL-NEXT:  .LBB12_1:
-; NO_ISEL-NEXT:    addi 3, 4, 0
-; NO_ISEL-NEXT:    blr
+; ALL-LABEL: select_Cplus1_C:
+; ALL:       # BB#0:
+; ALL-NEXT:    clrldi 3, 3, 63
+; ALL-NEXT:    addi 3, 3, 41
+; ALL-NEXT:    blr
   %sel = select i1 %cond, i32 42, i32 41
   ret i32 %sel
 }
 
 define i32 @select_Cplus1_C_zeroext(i1 zeroext %cond) {
-; ISEL-LABEL: select_Cplus1_C_zeroext:
-; ISEL:       # BB#0:
-; ISEL-NEXT:    andi. 3, 3, 1
-; ISEL-NEXT:    li 4, 42
-; ISEL-NEXT:    li 3, 41
-; ISEL-NEXT:    isel 3, 4, 3, 1
-; ISEL-NEXT:    blr
-;
-; NO_ISEL-LABEL: select_Cplus1_C_zeroext:
-; NO_ISEL:       # BB#0:
-; NO_ISEL-NEXT:    andi. 3, 3, 1
-; NO_ISEL-NEXT:    li 4, 42
-; NO_ISEL-NEXT:    li 3, 41
-; NO_ISEL-NEXT:    bc 12, 1, .LBB13_1
-; NO_ISEL-NEXT:    blr
-; NO_ISEL-NEXT:  .LBB13_1:
-; NO_ISEL-NEXT:    addi 3, 4, 0
-; NO_ISEL-NEXT:    blr
+; ALL-LABEL: select_Cplus1_C_zeroext:
+; ALL:       # BB#0:
+; ALL-NEXT:    addi 3, 3, 41
+; ALL-NEXT:    blr
   %sel = select i1 %cond, i32 42, i32 41
   ret i32 %sel
 }
 
 define i32 @select_Cplus1_C_signext(i1 signext %cond) {
-; ISEL-LABEL: select_Cplus1_C_signext:
-; ISEL:       # BB#0:
-; ISEL-NEXT:    andi. 3, 3, 1
-; ISEL-NEXT:    li 4, 42
-; ISEL-NEXT:    li 3, 41
-; ISEL-NEXT:    isel 3, 4, 3, 1
-; ISEL-NEXT:    blr
-;
-; NO_ISEL-LABEL: select_Cplus1_C_signext:
-; NO_ISEL:       # BB#0:
-; NO_ISEL-NEXT:    andi. 3, 3, 1
-; NO_ISEL-NEXT:    li 4, 42
-; NO_ISEL-NEXT:    li 3, 41
-; NO_ISEL-NEXT:    bc 12, 1, .LBB14_1
-; NO_ISEL-NEXT:    blr
-; NO_ISEL-NEXT:  .LBB14_1:
-; NO_ISEL-NEXT:    addi 3, 4, 0
-; NO_ISEL-NEXT:    blr
+; ALL-LABEL: select_Cplus1_C_signext:
+; ALL:       # BB#0:
+; ALL-NEXT:    subfic 3, 3, 41
+; ALL-NEXT:    blr
   %sel = select i1 %cond, i32 42, i32 41
   ret i32 %sel
 }
 
 ; select Cond, C, C+1 --> add (sext Cond), C
 
 define i32 @select_C_Cplus1(i1 %cond) {
-; ISEL-LABEL: select_C_Cplus1:
-; ISEL:       # BB#0:
-; ISEL-NEXT:    andi. 3, 3, 1
-; ISEL-NEXT:    li 4, 41
-; ISEL-NEXT:    li 3, 42
-; ISEL-NEXT:    isel 3, 4, 3, 1
-; ISEL-NEXT:    blr
-;
-; NO_ISEL-LABEL: select_C_Cplus1:
-; NO_ISEL:       # BB#0:
-; NO_ISEL-NEXT:    andi. 3, 3, 1
-; NO_ISEL-NEXT:    li 4, 41
-; NO_ISEL-NEXT:    li 3, 42
-; NO_ISEL-NEXT:    bc 12, 1, .LBB15_1
-; NO_ISEL-NEXT:    blr
-; NO_ISEL-NEXT:  .LBB15_1:
-; NO_ISEL-NEXT:    addi 3, 4, 0
-; NO_ISEL-NEXT:    blr
+; ALL-LABEL: select_C_Cplus1:
+; ALL:       # BB#0:
+; ALL-NEXT:    clrldi 3, 3, 63
+; ALL-NEXT:    subfic 3, 3, 42
+; ALL-NEXT:    blr
   %sel = select i1 %cond, i32 41, i32 42
   ret i32 %sel
 }
 
 define i32 @select_C_Cplus1_zeroext(i1 zeroext %cond) {
-; ISEL-LABEL: select_C_Cplus1_zeroext:
-; ISEL:       # BB#0:
-; ISEL-NEXT:    andi. 3, 3, 1
-; ISEL-NEXT:    li 4, 41
-; ISEL-NEXT:    li 3, 42
-; ISEL-NEXT:    isel 3, 4, 3, 1
-; ISEL-NEXT:    blr
-;
-; NO_ISEL-LABEL: select_C_Cplus1_zeroext:
-; NO_ISEL:       # BB#0:
-; NO_ISEL-NEXT:    andi. 3, 3, 1
-; NO_ISEL-NEXT:    li 4, 41
-; NO_ISEL-NEXT:    li 3, 42
-; NO_ISEL-NEXT:    bc 12, 1, .LBB16_1
-; NO_ISEL-NEXT:    blr
-; NO_ISEL-NEXT:  .LBB16_1:
-; NO_ISEL-NEXT:    addi 3, 4, 0
-; NO_ISEL-NEXT:    blr
+; ALL-LABEL: select_C_Cplus1_zeroext:
+; ALL:       # BB#0:
+; ALL-NEXT:    subfic 3, 3, 42
+; ALL-NEXT:    blr
   %sel = select i1 %cond, i32 41, i32 42
   ret i32 %sel
 }
 
 define i32 @select_C_Cplus1_signext(i1 signext %cond) {
-; ISEL-LABEL: select_C_Cplus1_signext:
-; ISEL:       # BB#0:
-; ISEL-NEXT:    andi. 3, 3, 1
-; ISEL-NEXT:    li 4, 41
-; ISEL-NEXT:    li 3, 42
-; ISEL-NEXT:    isel 3, 4, 3, 1
-; ISEL-NEXT:    blr
-;
-; NO_ISEL-LABEL: select_C_Cplus1_signext:
-; NO_ISEL:       # BB#0:
-; NO_ISEL-NEXT:    andi. 3, 3, 1
-; NO_ISEL-NEXT:    li 4, 41
-; NO_ISEL-NEXT:    li 3, 42
-; NO_ISEL-NEXT:    bc 12, 1, .LBB17_1
-; NO_ISEL-NEXT:    blr
-; NO_ISEL-NEXT:  .LBB17_1:
-; NO_ISEL-NEXT:    addi 3, 4, 0
-; NO_ISEL-NEXT:    blr
+; ALL-LABEL: select_C_Cplus1_signext:
+; ALL:       # BB#0:
+; ALL-NEXT:    addi 3, 3, 42
+; ALL-NEXT:    blr
   %sel = select i1 %cond, i32 41, i32 42
   ret i32 %sel
 }
 
 ; In general, select of 2 constants could be:
 ; select Cond, C1, C2 --> add (mul (zext Cond), C1-C2), C2 --> add (and (sext Cond), C1-C2), C2
 
 define i32 @select_C1_C2(i1 %cond) {

 ; NO_ISEL-NEXT:    ori 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = srem i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sel_constants_urem_constant(i1 %cond) {
-; ISEL-LABEL: sel_constants_urem_constant:
-; ISEL:       # BB#0:
-; ISEL-NEXT:    andi. 3, 3, 1
-; ISEL-NEXT:    li 4, 2
-; ISEL-NEXT:    li 3, 3
-; ISEL-NEXT:    isel 3, 4, 3, 1
-; ISEL-NEXT:    blr
-;
-; NO_ISEL-LABEL: sel_constants_urem_constant:
-; NO_ISEL:       # BB#0:
-; NO_ISEL-NEXT:    andi. 3, 3, 1
-; NO_ISEL-NEXT:    li 4, 2
-; NO_ISEL-NEXT:    li 3, 3
-; NO_ISEL-NEXT:    bc 12, 1, .LBB27_1
-; NO_ISEL-NEXT:    blr
-; NO_ISEL-NEXT:  .LBB27_1:
-; NO_ISEL-NEXT:    addi 3, 4, 0
-; NO_ISEL-NEXT:    blr
+; ALL-LABEL: sel_constants_urem_constant:
+; ALL:       # BB#0:
+; ALL-NEXT:    rlwinm 3, 3, 0, 31, 31
+; ALL-NEXT:    subfic 3, 3, 3
+; ALL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = urem i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sel_constants_and_constant(i1 %cond) {
-; ISEL-LABEL: sel_constants_and_constant:
-; ISEL:       # BB#0:
-; ISEL-NEXT:    andi. 3, 3, 1
-; ISEL-NEXT:    li 4, 4
-; ISEL-NEXT:    li 3, 5
-; ISEL-NEXT:    isel 3, 4, 3, 1
-; ISEL-NEXT:    blr
-;
-; NO_ISEL-LABEL: sel_constants_and_constant:
-; NO_ISEL:       # BB#0:
-; NO_ISEL-NEXT:    andi. 3, 3, 1
-; NO_ISEL-NEXT:    li 4, 4
-; NO_ISEL-NEXT:    li 3, 5
-; NO_ISEL-NEXT:    bc 12, 1, .LBB28_1
-; NO_ISEL-NEXT:    blr
-; NO_ISEL-NEXT:  .LBB28_1:
-; NO_ISEL-NEXT:    addi 3, 4, 0
-; NO_ISEL-NEXT:    blr
+; ALL-LABEL: sel_constants_and_constant:
+; ALL:       # BB#0:
+; ALL-NEXT:    rlwinm 3, 3, 0, 31, 31
+; ALL-NEXT:    subfic 3, 3, 5
+; ALL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = and i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sel_constants_or_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_or_constant:
 ; ISEL:       # BB#0:

test/CodeGen/X86/avx512-insert-extract.ll

 
 define zeroext i8 @test_extractelement_v2i1(<2 x i64> %a, <2 x i64> %b) {
 ; KNL-LABEL: test_extractelement_v2i1:
 ; KNL:       ## BB#0:
 ; KNL-NEXT:    vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
 ; KNL-NEXT:    vpxor %xmm2, %xmm1, %xmm1
 ; KNL-NEXT:    vpxor %xmm2, %xmm0, %xmm0
 ; KNL-NEXT:    vpcmpgtq %xmm1, %xmm0, %xmm0
-; KNL-NEXT:    vmovq %xmm0, %rax
-; KNL-NEXT:    testb $1, %al
-; KNL-NEXT:    sete %al
-; KNL-NEXT:    addb $3, %al
+; KNL-NEXT:    vpextrb $0, %xmm0, %eax
+; KNL-NEXT:    addb $4, %al
 ; KNL-NEXT:    movzbl %al, %eax
 ; KNL-NEXT:    retq
 ;
 ; SKX-LABEL: test_extractelement_v2i1:
 ; SKX:       ## BB#0:
 ; SKX-NEXT:    vpcmpnleuq %xmm1, %xmm0, %k0
 ; SKX-NEXT:    kshiftlw $15, %k0, %k0
 ; SKX-NEXT:    kshiftrw $15, %k0, %k0

 ; KNL-LABEL: test_extractelement_v64i1:
 ; KNL:       ## BB#0:
 ; KNL-NEXT:    vmovdqa {{.*#+}} ymm0 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128]
 ; KNL-NEXT:    vpxor %ymm0, %ymm3, %ymm2
 ; KNL-NEXT:    vpxor %ymm0, %ymm1, %ymm0
 ; KNL-NEXT:    vpcmpgtb %ymm2, %ymm0, %ymm0
 ; KNL-NEXT:    vextracti128 $1, %ymm0, %xmm0
 ; KNL-NEXT:    vpextrb $15, %xmm0, %eax
-; KNL-NEXT:    testb $1, %al
-; KNL-NEXT:    sete %al
-; KNL-NEXT:    addb $3, %al
+; KNL-NEXT:    addb $4, %al
 ; KNL-NEXT:    movzbl %al, %eax
 ; KNL-NEXT:    retq
 ;
 ; SKX-LABEL: test_extractelement_v64i1:
 ; SKX:       ## BB#0:
 ; SKX-NEXT:    vpcmpnleub %zmm1, %zmm0, %k0
 ; SKX-NEXT:    kshiftrq $63, %k0, %k0
 ; SKX-NEXT:    kmovw %k0, %eax

test/CodeGen/X86/avx512-select.ll

; CHECK-NEXT:    retq
   %r = select <8 x i1> %mask, <8 x i1> %a, <8 x i1> %b
   %res = bitcast <8 x i1> %r to i8
   ret i8 %res;
 }
 
 define i64 @pr30249() {
 ; CHECK-LABEL: pr30249:
 ; CHECK:       ## BB#0:
-; CHECK-NEXT:    xorl %ecx, %ecx
-; CHECK-NEXT:    cmpb $1, %cl
-; CHECK-NEXT:    movl $1, %eax
-; CHECK-NEXT:    adcxq %rcx, %rax
+; CHECK-NEXT:    movl $2, %eax
 ; CHECK-NEXT:    retq
   %v = select i1 undef , i64 1, i64 2
   ret i64 %v
 }
 
 define double @pr30561_f64(double %b, double %a, i1 %c) {
 ; CHECK-LABEL: pr30561_f64:
 ; CHECK:       ## BB#0:

test/CodeGen/X86/select_const.ll

; CHECK-NEXT:    retq
   ret i32 %sel
 }
 
 ; select Cond, C, C+1 --> add (sext Cond), C
 
 define i32 @select_C_Cplus1(i1 %cond) {
 ; CHECK-LABEL: select_C_Cplus1:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    andb $1, %dil
-; CHECK-NEXT:    cmpb $1, %dil
-; CHECK-NEXT:    movl $41, %eax
-; CHECK-NEXT:    adcl $0, %eax
+; CHECK-NEXT:    andl $1, %edi
+; CHECK-NEXT:    movl $42, %eax
+; CHECK-NEXT:    subl %edi, %eax
 ; CHECK-NEXT:    retq
   %sel = select i1 %cond, i32 41, i32 42
   ret i32 %sel
 }
 
 define i32 @select_C_Cplus1_zeroext(i1 zeroext %cond) {
 ; CHECK-LABEL: select_C_Cplus1_zeroext:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    cmpb $1, %dil
-; CHECK-NEXT:    movl $41, %eax
-; CHECK-NEXT:    adcl $0, %eax
+; CHECK-NEXT:    movzbl %dil, %ecx
+; CHECK-NEXT:    movl $42, %eax
+; CHECK-NEXT:    subl %ecx, %eax
 ; CHECK-NEXT:    retq
   %sel = select i1 %cond, i32 41, i32 42
   ret i32 %sel
 }
 
 define i32 @select_C_Cplus1_signext(i1 signext %cond) {
 ; CHECK-LABEL: select_C_Cplus1_signext:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    andb $1, %dil
-; CHECK-NEXT:    cmpb $1, %dil
-; CHECK-NEXT:    movl $41, %eax
-; CHECK-NEXT:    adcl $0, %eax
+; CHECK-NEXT:    movzbl %dil, %ecx
+; CHECK-NEXT:    movl $42, %eax
+; CHECK-NEXT:    subl %ecx, %eax
 ; CHECK-NEXT:    retq
   %sel = select i1 %cond, i32 41, i32 42
   ret i32 %sel
 }
 
 ; In general, select of 2 constants could be:
 ; select Cond, C1, C2 --> add (mul (zext Cond), C1-C2), C2 --> add (and (sext Cond), C1-C2), C2