[DAGCombiner] fold binops with constant into select-of-constants

[spatel]

Summary

This is part of the ongoing attempt to improve select codegen for all targets and select canonicalization in IR (see D24480 for more background).
The transform is a subset of what is done in InstCombine's FoldOpIntoSelect().

I first noticed a regression in the x86 avx512-insert-extract.ll tests with a patch that hopes to convert more selects to basic math ops. This appears to be a general missing DAG transform though, so I added tests for all standard binops in rL296621 (PowerPC was chosen semi-randomly; it has scripted FileCheck support, but so do ARM and x86).

The debug output for "sel_constants_shl_constant" makes me think that this patch is not at fault for that mess. The shl fold happens as expected. PPC then changes the i8 select to an i32 select, but the return value is i64, so the extend gets folded in creating an i64 select. I noticed this problem in a lesser form in D30180; it's why there weren't more improvements for PPC with that patch.

[efriedma]

The debug output for "sel_constants_shl_constant" makes me think that this patch is not at fault for that mess.

I would agree with that assessment; you get the same terrible lowering for "select i1 %cond, i8 -20, i8 115".

---

Some targets intentionally fold the other way in certain cases: pulling a math operation out of a select can make the immediates cheaper. For example, consider "int y; int *a(int x) { return x ? &y : &y+1; }" on ARM. That isn't directly impacted by this, though, because ARM uses target-specific nodes.

Does it make sense to handle SELECT_CC in addition to SELECT?

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

1788

Could you assert here that NewCT and NewCF are actually constants?

test/CodeGen/X86/setcc.ll

54

Hmm... we really want movl+adcl rather than movw+adcw. Maybe orthogonal to this patch.

[spatel]

In D30502#689854, @efriedma wrote:

The debug output for "sel_constants_shl_constant" makes me think that this patch is not at fault for that mess.

I would agree with that assessment; you get the same terrible lowering for "select i1 %cond, i8 -20, i8 115".

Right - I filed a similar example as:
https://bugs.llvm.org/show_bug.cgi?id=32105

Some targets intentionally fold the other way in certain cases: pulling a math operation out of a select can make the immediates cheaper. For example, consider "int y; int *a(int x) { return x ? &y : &y+1; }" on ARM. That isn't directly impacted by this, though, because ARM uses target-specific nodes.

Should I add a target hook or some other means to protect against that case? Or is it ok to assume this is universally good for the currently handled binop types?

Does it make sense to handle SELECT_CC in addition to SELECT?

I'm only seeing SELECT in the limited scope that I'm looking at so far. I'll add a TODO comment for now if that's ok.

[spatel]

Patch updated:

1. Add asserts for constant folds of the new select operands.
2. Add vector tests (x86 for ease of testing) because there was no coverage for those.
3. Add TODO comment about handling SELECT_CC.

[efriedma]

LGTM.

Or is it ok to assume this is universally good for the currently handled binop types?

Okay for now; if someone eventually trips over it, we can deal with it then.

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

private:
 
     SDValue XformToShuffleWithZero(SDNode *N);
     SDValue ReassociateOps(unsigned Opc, const SDLoc &DL, SDValue LHS,
                            SDValue RHS);
 
     SDValue visitShiftByConstant(SDNode *N, ConstantSDNode *Amt);
 
     SDValue foldSelectOfConstants(SDNode *N);
+    SDValue foldBinOpIntoSelect(SDNode *BO);
     bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
     SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
     SDValue SimplifySelect(const SDLoc &DL, SDValue N0, SDValue N1, SDValue N2);
     SDValue SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1,
                              SDValue N2, SDValue N3, ISD::CondCode CC,
                              bool NotExtCompare = false);
     SDValue foldSelectCCToShiftAnd(const SDLoc &DL, SDValue N0, SDValue N1,
                                    SDValue N2, SDValue N3, ISD::CondCode CC);

 
 /// If \p N is a ConstantSDNode with isOpaque() == false return it casted to a
 /// ConstantSDNode pointer else nullptr.
 static ConstantSDNode *getAsNonOpaqueConstant(SDValue N) {
   ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N);
   return Const != nullptr && !Const->isOpaque() ? Const : nullptr;
 }
 
+SDValue DAGCombiner::foldBinOpIntoSelect(SDNode *BO) {
+  auto BinOpcode = BO->getOpcode();
+  assert((BinOpcode == ISD::ADD || BinOpcode == ISD::SUB ||
+          BinOpcode == ISD::MUL || BinOpcode == ISD::SDIV ||
+          BinOpcode == ISD::UDIV || BinOpcode == ISD::SREM ||
+          BinOpcode == ISD::UREM || BinOpcode == ISD::AND ||
+          BinOpcode == ISD::OR || BinOpcode == ISD::XOR ||
+          BinOpcode == ISD::SHL || BinOpcode == ISD::SRL ||
+          BinOpcode == ISD::SRA || BinOpcode == ISD::FADD ||
+          BinOpcode == ISD::FSUB || BinOpcode == ISD::FMUL ||
+          BinOpcode == ISD::FDIV || BinOpcode == ISD::FREM) &&
+         "Unexpected binary operator");
+
+  SDValue C1 = BO->getOperand(1);
+  if (!isConstantOrConstantVector(C1) &&
+      !isConstantFPBuildVectorOrConstantFP(C1))
+    return SDValue();
+
+  // Don't do this unless the old select is going away. We want to eliminate the
+  // binary operator, not replace a binop with a select.
+  SDValue Sel = BO->getOperand(0);
+  if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse())
+    return SDValue();
+
+  SDValue CT = Sel.getOperand(1);
+  if (!isConstantOrConstantVector(CT) &&
+      !isConstantFPBuildVectorOrConstantFP(CT))
+    return SDValue();
+
+  SDValue CF = Sel.getOperand(2);
+  if (!isConstantOrConstantVector(CF) &&
+      !isConstantFPBuildVectorOrConstantFP(CF))
+    return SDValue();
+
+  // We have a select-of-constants followed by a binary operator with a
+  // constant. Eliminate the binop by pulling the constant math into the select.
+  // Example: add (select Cond, CT, CF), C1 --> select Cond, CT + C1, CF + C1
+  EVT VT = Sel.getValueType();
+  SDLoc DL(Sel);
+  SDValue NewCT = DAG.getNode(BinOpcode, DL, VT, CT, C1);
+  SDValue NewCF = DAG.getNode(BinOpcode, DL, VT, CF, C1);
+  return DAG.getSelect(DL, VT, Sel.getOperand(0), NewCT, NewCF);
+}
+
 SDValue DAGCombiner::visitADD(SDNode *N) {
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
   EVT VT = N0.getValueType();
   SDLoc DL(N);
 
   // fold vector ops
   if (VT.isVector()) {
if (isConstantOrConstantVector(N1, /* NoOpaque */ true)) {
     if (N0.getOpcode() == ISD::SUB)
       if (isConstantOrConstantVector(N0.getOperand(0), /* NoOpaque */ true)) {
         return DAG.getNode(ISD::SUB, DL, VT,
                            DAG.getNode(ISD::ADD, DL, VT, N1, N0.getOperand(0)),
                            N0.getOperand(1));
       }
   }
 
+  if (SDValue NewSel = foldBinOpIntoSelect(N))
+    return NewSel;
+
   // reassociate add
   if (SDValue RADD = ReassociateOps(ISD::ADD, DL, N0, N1))
     return RADD;
 
   // fold ((0-A) + B) -> B-A
   if (N0.getOpcode() == ISD::SUB &&
       isNullConstantOrNullSplatConstant(N0.getOperand(0)))
     return DAG.getNode(ISD::SUB, DL, VT, N1, N0.getOperand(1));
if (N0 == N1)
     return tryFoldToZero(DL, TLI, VT, DAG, LegalOperations, LegalTypes);
   if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
       DAG.isConstantIntBuildVectorOrConstantInt(N1)) {
     // fold (sub c1, c2) -> c1-c2
     return DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, N0.getNode(),
                                       N1.getNode());
   }
 
+  if (SDValue NewSel = foldBinOpIntoSelect(N))
+    return NewSel;
+
   ConstantSDNode *N1C = getAsNonOpaqueConstant(N1);
 
   // fold (sub x, c) -> (add x, -c)
   if (N1C) {
     return DAG.getNode(ISD::ADD, DL, VT, N0,
                        DAG.getConstant(-N1C->getAPIntValue(), DL, VT));
   }
 
if (N1IsConst && ConstValue1 == 0)
     return N1;
   // We require a splat of the entire scalar bit width for non-contiguous
   // bit patterns.
   bool IsFullSplat =
     ConstValue1.getBitWidth() == VT.getScalarSizeInBits();
   // fold (mul x, 1) -> x
   if (N1IsConst && ConstValue1 == 1 && IsFullSplat)
     return N0;
+
+  if (SDValue NewSel = foldBinOpIntoSelect(N))
+    return NewSel;
+
   // fold (mul x, -1) -> 0-x
   if (N1IsConst && ConstValue1.isAllOnesValue()) {
     SDLoc DL(N);
     return DAG.getNode(ISD::SUB, DL, VT,
                        DAG.getConstant(0, DL, VT), N0);
   }
   // fold (mul x, (1 << c)) -> x << c
   if (N1IsConst && !N1IsOpaqueConst && ConstValue1.isPowerOf2() &&
SDValue DAGCombiner::visitSDIV(SDNode *N) {
   // fold (sdiv X, 1) -> X
   if (N1C && N1C->isOne())
     return N0;
   // fold (sdiv X, -1) -> 0-X
   if (N1C && N1C->isAllOnesValue())
     return DAG.getNode(ISD::SUB, DL, VT,
                        DAG.getConstant(0, DL, VT), N0);
 
+  if (SDValue NewSel = foldBinOpIntoSelect(N))
+    return NewSel;
+
   // If we know the sign bits of both operands are zero, strength reduce to a
   // udiv instead.  Handles (X&15) /s 4 -> X&15 >> 2
   if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
     return DAG.getNode(ISD::UDIV, DL, N1.getValueType(), N0, N1);
 
   // fold (sdiv X, pow2) -> simple ops after legalize
   // FIXME: We check for the exact bit here because the generic lowering gives
   // better results in that case. The target-specific lowering should learn how
SDValue DAGCombiner::visitUDIV(SDNode *N) {
   // fold (udiv c1, c2) -> c1/c2
   ConstantSDNode *N0C = isConstOrConstSplat(N0);
   ConstantSDNode *N1C = isConstOrConstSplat(N1);
   if (N0C && N1C)
     if (SDValue Folded = DAG.FoldConstantArithmetic(ISD::UDIV, DL, VT,
                                                     N0C, N1C))
       return Folded;
 
+  if (SDValue NewSel = foldBinOpIntoSelect(N))
+    return NewSel;
+
   // fold (udiv x, (1 << c)) -> x >>u c
   if (isConstantOrConstantVector(N1, /*NoOpaques*/ true) &&
       DAG.isKnownToBeAPowerOfTwo(N1)) {
     SDValue LogBase2 = BuildLogBase2(N1, DL);
     AddToWorklist(LogBase2.getNode());
 
     EVT ShiftVT = getShiftAmountTy(N0.getValueType());
     SDValue Trunc = DAG.getZExtOrTrunc(LogBase2, DL, ShiftVT);
SDValue DAGCombiner::visitREM(SDNode *N) {
 
   // fold (rem c1, c2) -> c1%c2
   ConstantSDNode *N0C = isConstOrConstSplat(N0);
   ConstantSDNode *N1C = isConstOrConstSplat(N1);
   if (N0C && N1C)
     if (SDValue Folded = DAG.FoldConstantArithmetic(Opcode, DL, VT, N0C, N1C))
       return Folded;
 
+  if (SDValue NewSel = foldBinOpIntoSelect(N))
+    return NewSel;
+
   if (isSigned) {
     // If we know the sign bits of both operands are zero, strength reduce to a
     // urem instead.  Handles (X & 0x0FFFFFFF) %s 16 -> X&15
     if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
       return DAG.getNode(ISD::UREM, DL, VT, N0, N1);
   } else {
     SDValue NegOne = DAG.getAllOnesConstant(DL, VT);
     if (DAG.isKnownToBeAPowerOfTwo(N1)) {
SDValue DAGCombiner::visitAND(SDNode *N) {
   // fold (and x, -1) -> x
   if (isAllOnesConstant(N1))
     return N0;
   // if (and x, c) is known to be zero, return 0
   unsigned BitWidth = VT.getScalarSizeInBits();
   if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
                                    APInt::getAllOnesValue(BitWidth)))
     return DAG.getConstant(0, SDLoc(N), VT);
+
+  if (SDValue NewSel = foldBinOpIntoSelect(N))
+    return NewSel;
+
   // reassociate and
   if (SDValue RAND = ReassociateOps(ISD::AND, SDLoc(N), N0, N1))
     return RAND;
   // fold (and (or x, C), D) -> D if (C & D) == D
   if (N1C && N0.getOpcode() == ISD::OR)
     if (ConstantSDNode *ORI = isConstOrConstSplat(N0.getOperand(1)))
       if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
         return N1;
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
      !DAG.isConstantIntBuildVectorOrConstantInt(N1))
     return DAG.getNode(ISD::OR, SDLoc(N), VT, N1, N0);
   // fold (or x, 0) -> x
   if (isNullConstant(N1))
     return N0;
   // fold (or x, -1) -> -1
   if (isAllOnesConstant(N1))
     return N1;
+
+  if (SDValue NewSel = foldBinOpIntoSelect(N))
+    return NewSel;
+
   // fold (or x, c) -> c iff (x & ~c) == 0
   if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
     return N1;
 
   if (SDValue Combined = visitORLike(N0, N1, N))
     return Combined;
 
   // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16)
if (N0C && N1C)
     return DAG.FoldConstantArithmetic(ISD::XOR, SDLoc(N), VT, N0C, N1C);
   // canonicalize constant to RHS
   if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
      !DAG.isConstantIntBuildVectorOrConstantInt(N1))
     return DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0);
   // fold (xor x, 0) -> x
   if (isNullConstant(N1))
     return N0;
+
+  if (SDValue NewSel = foldBinOpIntoSelect(N))
+    return NewSel;
+
   // reassociate xor
   if (SDValue RXOR = ReassociateOps(ISD::XOR, SDLoc(N), N0, N1))
     return RXOR;
 
   // fold !(x cc y) -> (x !cc y)
   SDValue LHS, RHS, CC;
   if (TLI.isConstTrueVal(N1.getNode()) && isSetCCEquivalent(N0, LHS, RHS, CC)) {
     bool isInt = LHS.getValueType().isInteger();
SDValue DAGCombiner::visitSHL(SDNode *N) {
   if (N1C && N1C->getAPIntValue().uge(OpSizeInBits))
     return DAG.getUNDEF(VT);
   // fold (shl x, 0) -> x
   if (N1C && N1C->isNullValue())
     return N0;
   // fold (shl undef, x) -> 0
   if (N0.isUndef())
     return DAG.getConstant(0, SDLoc(N), VT);
+
+  if (SDValue NewSel = foldBinOpIntoSelect(N))
+    return NewSel;
+
   // if (shl x, c) is known to be zero, return 0
   if (DAG.MaskedValueIsZero(SDValue(N, 0),
                             APInt::getAllOnesValue(OpSizeInBits)))
     return DAG.getConstant(0, SDLoc(N), VT);
   // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
   if (N1.getOpcode() == ISD::TRUNCATE &&
       N1.getOperand(0).getOpcode() == ISD::AND) {
     if (SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode()))
SDValue DAGCombiner::visitSRA(SDNode *N) {
   if (isAllOnesConstant(N0))
     return N0;
   // fold (sra x, c >= size(x)) -> undef
   if (N1C && N1C->getAPIntValue().uge(OpSizeInBits))
     return DAG.getUNDEF(VT);
   // fold (sra x, 0) -> x
   if (N1C && N1C->isNullValue())
     return N0;
+
+  if (SDValue NewSel = foldBinOpIntoSelect(N))
+    return NewSel;
+
   // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
   // sext_inreg.
   if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
     unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
     EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
     if (VT.isVector())
       ExtVT = EVT::getVectorVT(*DAG.getContext(),
                                ExtVT, VT.getVectorNumElements());
SDValue DAGCombiner::visitSRL(SDNode *N) {
   if (isNullConstant(N0))
     return N0;
   // fold (srl x, c >= size(x)) -> undef
   if (N1C && N1C->getAPIntValue().uge(OpSizeInBits))
     return DAG.getUNDEF(VT);
   // fold (srl x, 0) -> x
   if (N1C && N1C->isNullValue())
     return N0;
+
+  if (SDValue NewSel = foldBinOpIntoSelect(N))
+    return NewSel;
+
   // if (srl x, c) is known to be zero, return 0
   if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
                                    APInt::getAllOnesValue(OpSizeInBits)))
     return DAG.getConstant(0, SDLoc(N), VT);
 
   // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
   if (N1C && N0.getOpcode() == ISD::SRL) {
     if (ConstantSDNode *N0C1 = isConstOrConstSplat(N0.getOperand(1))) {
SDValue DAGCombiner::visitFADD(SDNode *N) {
   // fold (fadd c1, c2) -> c1 + c2
   if (N0CFP && N1CFP)
     return DAG.getNode(ISD::FADD, DL, VT, N0, N1, Flags);
 
   // canonicalize constant to RHS
   if (N0CFP && !N1CFP)
     return DAG.getNode(ISD::FADD, DL, VT, N1, N0, Flags);
 
+  if (SDValue NewSel = foldBinOpIntoSelect(N))
+    return NewSel;
+
   // fold (fadd A, (fneg B)) -> (fsub A, B)
   if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
       isNegatibleForFree(N1, LegalOperations, TLI, &Options) == 2)
     return DAG.getNode(ISD::FSUB, DL, VT, N0,
                        GetNegatedExpression(N1, DAG, LegalOperations), Flags);
 
   // fold (fadd (fneg A), B) -> (fsub B, A)
   if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
SDValue DAGCombiner::visitFSUB(SDNode *N) {
   if (VT.isVector())
     if (SDValue FoldedVOp = SimplifyVBinOp(N))
       return FoldedVOp;
 
   // fold (fsub c1, c2) -> c1-c2
   if (N0CFP && N1CFP)
     return DAG.getNode(ISD::FSUB, DL, VT, N0, N1, Flags);
 
+  if (SDValue NewSel = foldBinOpIntoSelect(N))
+    return NewSel;
+
   // fold (fsub A, (fneg B)) -> (fadd A, B)
   if (isNegatibleForFree(N1, LegalOperations, TLI, &Options))
     return DAG.getNode(ISD::FADD, DL, VT, N0,
                        GetNegatedExpression(N1, DAG, LegalOperations), Flags);
 
   // FIXME: Auto-upgrade the target/function-level option.
   if (Options.UnsafeFPMath || N->getFlags()->hasNoSignedZeros()) {
     // (fsub 0, B) -> -B
SDValue DAGCombiner::visitFMUL(SDNode *N) {
   if (isConstantFPBuildVectorOrConstantFP(N0) &&
      !isConstantFPBuildVectorOrConstantFP(N1))
     return DAG.getNode(ISD::FMUL, DL, VT, N1, N0, Flags);
 
   // fold (fmul A, 1.0) -> A
   if (N1CFP && N1CFP->isExactlyValue(1.0))
     return N0;
 
+  if (SDValue NewSel = foldBinOpIntoSelect(N))
+    return NewSel;
+
   if (Options.UnsafeFPMath) {
     // fold (fmul A, 0) -> 0
     if (N1CFP && N1CFP->isZero())
       return N1;
 
     // fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
     if (N0.getOpcode() == ISD::FMUL) {
       // Fold scalars or any vector constants (not just splats).
SDValue DAGCombiner::visitFDIV(SDNode *N) {
   if (VT.isVector())
     if (SDValue FoldedVOp = SimplifyVBinOp(N))
       return FoldedVOp;
 
   // fold (fdiv c1, c2) -> c1/c2
   if (N0CFP && N1CFP)
     return DAG.getNode(ISD::FDIV, SDLoc(N), VT, N0, N1, Flags);
 
+  if (SDValue NewSel = foldBinOpIntoSelect(N))
+    return NewSel;
+
   if (Options.UnsafeFPMath) {
     // fold (fdiv X, c2) -> fmul X, 1/c2 if losing precision is acceptable.
     if (N1CFP) {
       // Compute the reciprocal 1.0 / c2.
       const APFloat &N1APF = N1CFP->getValueAPF();
       APFloat Recip(N1APF.getSemantics(), 1); // 1.0
       APFloat::opStatus st = Recip.divide(N1APF, APFloat::rmNearestTiesToEven);
       // Only do the transform if the reciprocal is a legal fp immediate that
SDValue DAGCombiner::visitFREM(SDNode *N) {
   ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
   EVT VT = N->getValueType(0);
 
   // fold (frem c1, c2) -> fmod(c1,c2)
   if (N0CFP && N1CFP)
     return DAG.getNode(ISD::FREM, SDLoc(N), VT, N0, N1,
                        &cast<BinaryWithFlagsSDNode>(N)->Flags);
 
+  if (SDValue NewSel = foldBinOpIntoSelect(N))
+    return NewSel;
+
   return SDValue();
 }
 
 SDValue DAGCombiner::visitFSQRT(SDNode *N) {
   if (!DAG.getTarget().Options.UnsafeFPMath)
     return SDValue();
 
   SDValue N0 = N->getOperand(0);

test/CodeGen/ARM/select_xform.ll

 ; T2: cmp r1, #10
 ; T2: subgt r0, #1
   %cmp = icmp sgt i32 %a, 10
   %conv = sext i1 %cmp to i32
   %add = add i32 %conv, %c
   ret i32 %add
 }
 
-; Do not fold the xor into the select
+; Fold the xor into the select.
 define i32 @t15(i32 %p) {
 entry:
 ; ARM-LABEL: t15:
-; ARM: mov     [[REG:r[0-9]+]], #2
+; ARM: mov     [[REG:r[0-9]+]], #3
 ; ARM: cmp     r0, #8
-; ARM: movwgt  [[REG:r[0-9]+]], #1
-; ARM: eor     r0, [[REG:r[0-9]+]], #1
+; ARM: movwgt  [[REG:r[0-9]+]], #0
 
 ; T2-LABEL: t15:
-; T2: movs    [[REG:r[0-9]+]], #2
+; T2: movs    [[REG:r[0-9]+]], #3
 ; T2: cmp     [[REG:r[0-9]+]], #8
 ; T2: it      gt
-; T2: movgt   [[REG:r[0-9]+]], #1
-; T2: eor     r0, [[REG:r[0-9]+]], #1
+; T2: movgt   [[REG:r[0-9]+]], #0
   %cmp = icmp sgt i32 %p, 8
   %a = select i1 %cmp, i32 1, i32 2
   %xor = xor i32 %a, 1
   ret i32 %xor
 }
 
 define i32 @t16(i32 %x, i32 %y) {
 entry:

test/CodeGen/PowerPC/select_const.ll

 }
 
 ; A binary operator with constant after the select should always get folded into the select.
 
 define i8 @sel_constants_add_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_add_constant:
 ; ISEL:       # BB#0:
 ; ISEL-NEXT:    andi. 3, 3, 1
-; ISEL-NEXT:    li 4, -4
-; ISEL-NEXT:    li 3, 23
+; ISEL-NEXT:    li 4, 1
+; ISEL-NEXT:    li 3, 28
 ; ISEL-NEXT:    isel 3, 4, 3, 1
-; ISEL-NEXT:    addi 3, 3, 5
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_add_constant:
 ; NO_ISEL:       # BB#0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
-; NO_ISEL-NEXT:    li 4, -4
-; NO_ISEL-NEXT:    li 3, 23
+; NO_ISEL-NEXT:    li 4, 1
+; NO_ISEL-NEXT:    li 3, 28
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB21_1
-; NO_ISEL-NEXT:    b .LBB21_2
+; NO_ISEL-NEXT:    blr
 ; NO_ISEL-NEXT:  .LBB21_1:
 ; NO_ISEL-NEXT:    addi 3, 4, 0
-; NO_ISEL-NEXT:  .LBB21_2:
-; NO_ISEL-NEXT:    addi 3, 3, 5
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = add i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sel_constants_sub_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_sub_constant:
 ; ISEL:       # BB#0:
+; ISEL-NEXT:    li 4, 0
 ; ISEL-NEXT:    andi. 3, 3, 1
-; ISEL-NEXT:    li 4, -4
-; ISEL-NEXT:    li 3, 23
-; ISEL-NEXT:    isel 3, 4, 3, 1
-; ISEL-NEXT:    addi 3, 3, -5
+; ISEL-NEXT:    oris 3, 4, 65535
+; ISEL-NEXT:    li 4, 18
+; ISEL-NEXT:    ori 3, 3, 65527
+; ISEL-NEXT:    isel 3, 3, 4, 1
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_sub_constant:
 ; NO_ISEL:       # BB#0:
+; NO_ISEL-NEXT:    li 4, 0
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
-; NO_ISEL-NEXT:    li 4, -4
-; NO_ISEL-NEXT:    li 3, 23
-; NO_ISEL-NEXT:    bc 12, 1, .LBB22_1
-; NO_ISEL-NEXT:    b .LBB22_2
-; NO_ISEL-NEXT:  .LBB22_1:
-; NO_ISEL-NEXT:    addi 3, 4, 0
-; NO_ISEL-NEXT:  .LBB22_2:
-; NO_ISEL-NEXT:    addi 3, 3, -5
+; NO_ISEL-NEXT:    oris 3, 4, 65535
+; NO_ISEL-NEXT:    li 4, 18
+; NO_ISEL-NEXT:    ori 3, 3, 65527
+; NO_ISEL-NEXT:    bclr 12, 1, 0
+; NO_ISEL-NEXT:  # BB#1:
+; NO_ISEL-NEXT:    ori 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = sub i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sel_constants_mul_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_mul_constant:
 ; ISEL:       # BB#0:
+; ISEL-NEXT:    lis 4, 16383
 ; ISEL-NEXT:    andi. 3, 3, 1
-; ISEL-NEXT:    li 4, -4
-; ISEL-NEXT:    li 3, 23
-; ISEL-NEXT:    isel 3, 4, 3, 1
-; ISEL-NEXT:    mulli 3, 3, 5
+; ISEL-NEXT:    ori 3, 4, 65531
+; ISEL-NEXT:    li 4, 115
+; ISEL-NEXT:    sldi 3, 3, 2
+; ISEL-NEXT:    isel 3, 3, 4, 1
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_mul_constant:
 ; NO_ISEL:       # BB#0:
+; NO_ISEL-NEXT:    lis 4, 16383
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
-; NO_ISEL-NEXT:    li 4, -4
-; NO_ISEL-NEXT:    li 3, 23
-; NO_ISEL-NEXT:    bc 12, 1, .LBB23_1
-; NO_ISEL-NEXT:    b .LBB23_2
-; NO_ISEL-NEXT:  .LBB23_1:
-; NO_ISEL-NEXT:    addi 3, 4, 0
-; NO_ISEL-NEXT:  .LBB23_2:
-; NO_ISEL-NEXT:    mulli 3, 3, 5
+; NO_ISEL-NEXT:    ori 3, 4, 65531
+; NO_ISEL-NEXT:    li 4, 115
+; NO_ISEL-NEXT:    sldi 3, 3, 2
+; NO_ISEL-NEXT:    bclr 12, 1, 0
+; NO_ISEL-NEXT:  # BB#1:
+; NO_ISEL-NEXT:    ori 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = mul i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sel_constants_sdiv_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_sdiv_constant:
 ; ISEL:       # BB#0:
 ; ISEL-NEXT:    andi. 3, 3, 1
-; ISEL-NEXT:    lis 5, 26214
-; ISEL-NEXT:    li 4, -4
-; ISEL-NEXT:    li 3, 23
-; ISEL-NEXT:    ori 12, 5, 26215
-; ISEL-NEXT:    isel 3, 4, 3, 1
-; ISEL-NEXT:    mulld 3, 3, 12
-; ISEL-NEXT:    rldicl 4, 3, 1, 63
-; ISEL-NEXT:    sradi 3, 3, 33
-; ISEL-NEXT:    add 3, 3, 4
+; ISEL-NEXT:    li 3, 4
+; ISEL-NEXT:    isel 3, 0, 3, 1
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_sdiv_constant:
 ; NO_ISEL:       # BB#0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
-; NO_ISEL-NEXT:    lis 5, 26214
-; NO_ISEL-NEXT:    li 4, -4
-; NO_ISEL-NEXT:    li 3, 23
-; NO_ISEL-NEXT:    ori 12, 5, 26215
+; NO_ISEL-NEXT:    li 3, 4
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB24_1
-; NO_ISEL-NEXT:    b .LBB24_2
+; NO_ISEL-NEXT:    blr
 ; NO_ISEL-NEXT:  .LBB24_1:
-; NO_ISEL-NEXT:    addi 3, 4, 0
-; NO_ISEL-NEXT:  .LBB24_2:
-; NO_ISEL-NEXT:    mulld 3, 3, 12
-; NO_ISEL-NEXT:    rldicl 4, 3, 1, 63
-; NO_ISEL-NEXT:    sradi 3, 3, 33
-; NO_ISEL-NEXT:    add 3, 3, 4
+; NO_ISEL-NEXT:    addi 3, 0, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = sdiv i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sel_constants_udiv_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_udiv_constant:
 ; ISEL:       # BB#0:
-; ISEL-NEXT:    lis 4, 16383
 ; ISEL-NEXT:    andi. 3, 3, 1
-; ISEL-NEXT:    li 5, 0
-; ISEL-NEXT:    ori 3, 4, 65535
-; ISEL-NEXT:    li 4, 23
-; ISEL-NEXT:    oris 12, 5, 52428
-; ISEL-NEXT:    sldi 3, 3, 2
-; ISEL-NEXT:    isel 3, 3, 4, 1
-; ISEL-NEXT:    ori 4, 12, 52429
-; ISEL-NEXT:    clrldi 3, 3, 56
-; ISEL-NEXT:    mulld 3, 3, 4
-; ISEL-NEXT:    rldicl 3, 3, 30, 34
+; ISEL-NEXT:    li 4, 50
+; ISEL-NEXT:    li 3, 4
+; ISEL-NEXT:    isel 3, 4, 3, 1
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_udiv_constant:
 ; NO_ISEL:       # BB#0:
-; NO_ISEL-NEXT:    lis 4, 16383
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
-; NO_ISEL-NEXT:    li 5, 0
-; NO_ISEL-NEXT:    ori 3, 4, 65535
-; NO_ISEL-NEXT:    li 4, 23
-; NO_ISEL-NEXT:    oris 12, 5, 52428
-; NO_ISEL-NEXT:    sldi 3, 3, 2
-; NO_ISEL-NEXT:    bc 12, 1, .LBB25_2
-; NO_ISEL-NEXT:  # BB#1:
-; NO_ISEL-NEXT:    ori 3, 4, 0
-; NO_ISEL-NEXT:    b .LBB25_2
-; NO_ISEL-NEXT:  .LBB25_2:
-; NO_ISEL-NEXT:    ori 4, 12, 52429
-; NO_ISEL-NEXT:    clrldi 3, 3, 56
-; NO_ISEL-NEXT:    mulld 3, 3, 4
-; NO_ISEL-NEXT:    rldicl 3, 3, 30, 34
+; NO_ISEL-NEXT:    li 4, 50
+; NO_ISEL-NEXT:    li 3, 4
+; NO_ISEL-NEXT:    bc 12, 1, .LBB25_1
+; NO_ISEL-NEXT:    blr
+; NO_ISEL-NEXT:  .LBB25_1:
+; NO_ISEL-NEXT:    addi 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = udiv i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sel_constants_srem_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_srem_constant:
 ; ISEL:       # BB#0:
+; ISEL-NEXT:    lis 4, 16383
 ; ISEL-NEXT:    andi. 3, 3, 1
-; ISEL-NEXT:    li 4, -4
-; ISEL-NEXT:    lis 12, 26214
-; ISEL-NEXT:    li 3, 23
-; ISEL-NEXT:    isel 3, 4, 3, 1
-; ISEL-NEXT:    ori 4, 12, 26215
-; ISEL-NEXT:    extsw 3, 3
-; ISEL-NEXT:    mulld 4, 3, 4
-; ISEL-NEXT:    rldicl 5, 4, 1, 63
-; ISEL-NEXT:    sradi 4, 4, 33
-; ISEL-NEXT:    add 4, 4, 5
-; ISEL-NEXT:    mulli 4, 4, 5
-; ISEL-NEXT:    subf 3, 4, 3
+; ISEL-NEXT:    ori 3, 4, 65535
+; ISEL-NEXT:    li 4, 3
+; ISEL-NEXT:    sldi 3, 3, 2
+; ISEL-NEXT:    isel 3, 3, 4, 1
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_srem_constant:
 ; NO_ISEL:       # BB#0:
+; NO_ISEL-NEXT:    lis 4, 16383
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
-; NO_ISEL-NEXT:    li 4, -4
-; NO_ISEL-NEXT:    lis 12, 26214
-; NO_ISEL-NEXT:    li 3, 23
-; NO_ISEL-NEXT:    bc 12, 1, .LBB26_1
-; NO_ISEL-NEXT:    b .LBB26_2
-; NO_ISEL-NEXT:  .LBB26_1:
-; NO_ISEL-NEXT:    addi 3, 4, 0
-; NO_ISEL-NEXT:  .LBB26_2:
-; NO_ISEL-NEXT:    ori 4, 12, 26215
-; NO_ISEL-NEXT:    extsw 3, 3
-; NO_ISEL-NEXT:    mulld 4, 3, 4
-; NO_ISEL-NEXT:    rldicl 5, 4, 1, 63
-; NO_ISEL-NEXT:    sradi 4, 4, 33
-; NO_ISEL-NEXT:    add 4, 4, 5
-; NO_ISEL-NEXT:    mulli 4, 4, 5
-; NO_ISEL-NEXT:    subf 3, 4, 3
+; NO_ISEL-NEXT:    ori 3, 4, 65535
+; NO_ISEL-NEXT:    li 4, 3
+; NO_ISEL-NEXT:    sldi 3, 3, 2
+; NO_ISEL-NEXT:    bclr 12, 1, 0
+; NO_ISEL-NEXT:  # BB#1:
+; NO_ISEL-NEXT:    ori 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = srem i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sel_constants_urem_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_urem_constant:
 ; ISEL:       # BB#0:
 ; ISEL-NEXT:    andi. 3, 3, 1
-; ISEL-NEXT:    li 4, -4
-; ISEL-NEXT:    li 12, 0
-; ISEL-NEXT:    li 3, 23
-; ISEL-NEXT:    isel 3, 4, 3, 1
-; ISEL-NEXT:    oris 4, 12, 52428
-; ISEL-NEXT:    rlwinm 3, 3, 0, 24, 31
-; ISEL-NEXT:    ori 4, 4, 52429
-; ISEL-NEXT:    clrldi 5, 3, 32
-; ISEL-NEXT:    mulld 4, 5, 4
-; ISEL-NEXT:    rldicl 4, 4, 30, 34
-; ISEL-NEXT:    mulli 4, 4, 5
-; ISEL-NEXT:    subf 3, 4, 3
+; ISEL-NEXT:    li 4, 2
+; ISEL-NEXT:    li 3, 3
+; ISEL-NEXT:    isel 3, 4, 3, 1
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_urem_constant:
 ; NO_ISEL:       # BB#0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
-; NO_ISEL-NEXT:    li 4, -4
-; NO_ISEL-NEXT:    li 12, 0
-; NO_ISEL-NEXT:    li 3, 23
+; NO_ISEL-NEXT:    li 4, 2
+; NO_ISEL-NEXT:    li 3, 3
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB27_1
-; NO_ISEL-NEXT:    b .LBB27_2
+; NO_ISEL-NEXT:    blr
 ; NO_ISEL-NEXT:  .LBB27_1:
 ; NO_ISEL-NEXT:    addi 3, 4, 0
-; NO_ISEL-NEXT:  .LBB27_2:
-; NO_ISEL-NEXT:    oris 4, 12, 52428
-; NO_ISEL-NEXT:    rlwinm 3, 3, 0, 24, 31
-; NO_ISEL-NEXT:    ori 4, 4, 52429
-; NO_ISEL-NEXT:    clrldi 5, 3, 32
-; NO_ISEL-NEXT:    mulld 4, 5, 4
-; NO_ISEL-NEXT:    rldicl 4, 4, 30, 34
-; NO_ISEL-NEXT:    mulli 4, 4, 5
-; NO_ISEL-NEXT:    subf 3, 4, 3
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = urem i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sel_constants_and_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_and_constant:
 ; ISEL:       # BB#0:
-; ISEL-NEXT:    lis 4, 16383
 ; ISEL-NEXT:    andi. 3, 3, 1
-; ISEL-NEXT:    ori 3, 4, 65535
-; ISEL-NEXT:    li 4, 23
-; ISEL-NEXT:    sldi 3, 3, 2
-; ISEL-NEXT:    isel 3, 3, 4, 1
-; ISEL-NEXT:    andi. 3, 3, 5
+; ISEL-NEXT:    li 4, 4
+; ISEL-NEXT:    li 3, 5
+; ISEL-NEXT:    isel 3, 4, 3, 1
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_and_constant:
 ; NO_ISEL:       # BB#0:
-; NO_ISEL-NEXT:    lis 4, 16383
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
-; NO_ISEL-NEXT:    ori 3, 4, 65535
-; NO_ISEL-NEXT:    li 4, 23
-; NO_ISEL-NEXT:    sldi 3, 3, 2
-; NO_ISEL-NEXT:    bc 12, 1, .LBB28_2
-; NO_ISEL-NEXT:  # BB#1:
-; NO_ISEL-NEXT:    ori 3, 4, 0
-; NO_ISEL-NEXT:    b .LBB28_2
-; NO_ISEL-NEXT:  .LBB28_2:
-; NO_ISEL-NEXT:    andi. 3, 3, 5
+; NO_ISEL-NEXT:    li 4, 4
+; NO_ISEL-NEXT:    li 3, 5
+; NO_ISEL-NEXT:    bc 12, 1, .LBB28_1
+; NO_ISEL-NEXT:    blr
+; NO_ISEL-NEXT:  .LBB28_1:
+; NO_ISEL-NEXT:    addi 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = and i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sel_constants_or_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_or_constant:
 ; ISEL:       # BB#0:
-; ISEL-NEXT:    lis 4, 16383
+; ISEL-NEXT:    li 4, 0
 ; ISEL-NEXT:    andi. 3, 3, 1
-; ISEL-NEXT:    ori 3, 4, 65535
+; ISEL-NEXT:    oris 3, 4, 65535
 ; ISEL-NEXT:    li 4, 23
-; ISEL-NEXT:    sldi 3, 3, 2
+; ISEL-NEXT:    ori 3, 3, 65533
 ; ISEL-NEXT:    isel 3, 3, 4, 1
-; ISEL-NEXT:    ori 3, 3, 5
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_or_constant:
 ; NO_ISEL:       # BB#0:
-; NO_ISEL-NEXT:    lis 4, 16383
+; NO_ISEL-NEXT:    li 4, 0
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
-; NO_ISEL-NEXT:    ori 3, 4, 65535
+; NO_ISEL-NEXT:    oris 3, 4, 65535
 ; NO_ISEL-NEXT:    li 4, 23
-; NO_ISEL-NEXT:    sldi 3, 3, 2
-; NO_ISEL-NEXT:    bc 12, 1, .LBB29_2
+; NO_ISEL-NEXT:    ori 3, 3, 65533
+; NO_ISEL-NEXT:    bclr 12, 1, 0
 ; NO_ISEL-NEXT:  # BB#1:
 ; NO_ISEL-NEXT:    ori 3, 4, 0
-; NO_ISEL-NEXT:    b .LBB29_2
-; NO_ISEL-NEXT:  .LBB29_2:
-; NO_ISEL-NEXT:    ori 3, 3, 5
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = or i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sel_constants_xor_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_xor_constant:
 ; ISEL:       # BB#0:
-; ISEL-NEXT:    lis 4, 16383
+; ISEL-NEXT:    li 4, 0
 ; ISEL-NEXT:    andi. 3, 3, 1
-; ISEL-NEXT:    ori 3, 4, 65535
-; ISEL-NEXT:    li 4, 23
-; ISEL-NEXT:    sldi 3, 3, 2
+; ISEL-NEXT:    oris 3, 4, 65535
+; ISEL-NEXT:    li 4, 18
+; ISEL-NEXT:    ori 3, 3, 65529
 ; ISEL-NEXT:    isel 3, 3, 4, 1
-; ISEL-NEXT:    xori 3, 3, 5
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_xor_constant:
 ; NO_ISEL:       # BB#0:
-; NO_ISEL-NEXT:    lis 4, 16383
+; NO_ISEL-NEXT:    li 4, 0
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
-; NO_ISEL-NEXT:    ori 3, 4, 65535
-; NO_ISEL-NEXT:    li 4, 23
-; NO_ISEL-NEXT:    sldi 3, 3, 2
-; NO_ISEL-NEXT:    bc 12, 1, .LBB30_2
+; NO_ISEL-NEXT:    oris 3, 4, 65535
+; NO_ISEL-NEXT:    li 4, 18
+; NO_ISEL-NEXT:    ori 3, 3, 65529
+; NO_ISEL-NEXT:    bclr 12, 1, 0
 ; NO_ISEL-NEXT:  # BB#1:
 ; NO_ISEL-NEXT:    ori 3, 4, 0
-; NO_ISEL-NEXT:    b .LBB30_2
-; NO_ISEL-NEXT:  .LBB30_2:
-; NO_ISEL-NEXT:    xori 3, 3, 5
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = xor i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sel_constants_shl_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_shl_constant:
 ; ISEL:       # BB#0:
+; ISEL-NEXT:    lis 5, 511
+; ISEL-NEXT:    lis 4, 2047
 ; ISEL-NEXT:    andi. 3, 3, 1
-; ISEL-NEXT:    li 4, -4
-; ISEL-NEXT:    li 3, 23
+; ISEL-NEXT:    ori 3, 4, 65535
+; ISEL-NEXT:    ori 12, 5, 65535
+; ISEL-NEXT:    sldi 3, 3, 5
+; ISEL-NEXT:    sldi 4, 12, 7
 ; ISEL-NEXT:    isel 3, 4, 3, 1
-; ISEL-NEXT:    slwi 3, 3, 5
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_shl_constant:
 ; NO_ISEL:       # BB#0:
+; NO_ISEL-NEXT:    lis 5, 511
+; NO_ISEL-NEXT:    lis 4, 2047
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
-; NO_ISEL-NEXT:    li 4, -4
-; NO_ISEL-NEXT:    li 3, 23
+; NO_ISEL-NEXT:    ori 3, 4, 65535
+; NO_ISEL-NEXT:    ori 12, 5, 65535
+; NO_ISEL-NEXT:    sldi 3, 3, 5
+; NO_ISEL-NEXT:    sldi 4, 12, 7
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB31_1
-; NO_ISEL-NEXT:    b .LBB31_2
+; NO_ISEL-NEXT:    blr
 ; NO_ISEL-NEXT:  .LBB31_1:
 ; NO_ISEL-NEXT:    addi 3, 4, 0
-; NO_ISEL-NEXT:  .LBB31_2:
-; NO_ISEL-NEXT:    slwi 3, 3, 5
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = shl i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sel_constants_lshr_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_lshr_constant:
 ; ISEL:       # BB#0:
 ; ISEL-NEXT:    andi. 3, 3, 1
-; ISEL-NEXT:    li 4, -4
-; ISEL-NEXT:    li 3, 23
+; ISEL-NEXT:    li 4, 7
+; ISEL-NEXT:    li 3, 0
 ; ISEL-NEXT:    isel 3, 4, 3, 1
-; ISEL-NEXT:    rlwinm 3, 3, 27, 29, 31
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_lshr_constant:
 ; NO_ISEL:       # BB#0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
-; NO_ISEL-NEXT:    li 4, -4
-; NO_ISEL-NEXT:    li 3, 23
+; NO_ISEL-NEXT:    li 4, 7
+; NO_ISEL-NEXT:    li 3, 0
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB32_1
-; NO_ISEL-NEXT:    b .LBB32_2
+; NO_ISEL-NEXT:    blr
 ; NO_ISEL-NEXT:  .LBB32_1:
 ; NO_ISEL-NEXT:    addi 3, 4, 0
-; NO_ISEL-NEXT:  .LBB32_2:
-; NO_ISEL-NEXT:    rlwinm 3, 3, 27, 29, 31
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = lshr i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sel_constants_ashr_constant(i1 %cond) {
-; ISEL-LABEL: sel_constants_ashr_constant:
+; ALL-LABEL: sel_constants_ashr_constant:
+; ALL:       # BB#0:
+; ALL-NEXT:    clrldi 3, 3, 63
+; ALL-NEXT:    neg 3, 3
+; ALL-NEXT:    blr
+  %sel = select i1 %cond, i8 -4, i8 23
+  %bo = ashr i8 %sel, 5
+  ret i8 %bo
+}
+
+define double @sel_constants_fadd_constant(i1 %cond) {
+; ISEL-LABEL: sel_constants_fadd_constant:
 ; ISEL:       # BB#0:
 ; ISEL-NEXT:    andi. 3, 3, 1
-; ISEL-NEXT:    li 4, -4
-; ISEL-NEXT:    li 3, 23
-; ISEL-NEXT:    isel 3, 4, 3, 1
-; ISEL-NEXT:    srawi 3, 3, 5
+; ISEL-NEXT:    addis 4, 2, .LCPI34_0@toc@ha
+; ISEL-NEXT:    addis 3, 2, .LCPI34_1@toc@ha
+; ISEL-NEXT:    addi 4, 4, .LCPI34_0@toc@l
+; ISEL-NEXT:    addi 3, 3, .LCPI34_1@toc@l
+; ISEL-NEXT:    isel 3, 3, 4, 1
+; ISEL-NEXT:    lxsdx 1, 0, 3
 ; ISEL-NEXT:    blr
 ;
-; NO_ISEL-LABEL: sel_constants_ashr_constant:
+; NO_ISEL-LABEL: sel_constants_fadd_constant:
 ; NO_ISEL:       # BB#0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
-; NO_ISEL-NEXT:    li 4, -4
-; NO_ISEL-NEXT:    li 3, 23
-; NO_ISEL-NEXT:    bc 12, 1, .LBB33_1
-; NO_ISEL-NEXT:    b .LBB33_2
-; NO_ISEL-NEXT:  .LBB33_1:
-; NO_ISEL-NEXT:    addi 3, 4, 0
-; NO_ISEL-NEXT:  .LBB33_2:
-; NO_ISEL-NEXT:    srawi 3, 3, 5
+; NO_ISEL-NEXT:    addis 4, 2, .LCPI34_0@toc@ha
+; NO_ISEL-NEXT:    addis 3, 2, .LCPI34_1@toc@ha
+; NO_ISEL-NEXT:    addi 4, 4, .LCPI34_0@toc@l
+; NO_ISEL-NEXT:    addi 3, 3, .LCPI34_1@toc@l
+; NO_ISEL-NEXT:    bc 12, 1, .LBB34_2
+; NO_ISEL-NEXT:  # BB#1:
+; NO_ISEL-NEXT:    ori 3, 4, 0
+; NO_ISEL-NEXT:    b .LBB34_2
+; NO_ISEL-NEXT:  .LBB34_2:
+; NO_ISEL-NEXT:    lxsdx 1, 0, 3
 ; NO_ISEL-NEXT:    blr
-  %sel = select i1 %cond, i8 -4, i8 23
-  %bo = ashr i8 %sel, 5
-  ret i8 %bo
-}
-
-define double @sel_constants_fadd_constant(i1 %cond) {
-; ALL-LABEL: sel_constants_fadd_constant:
-; ALL:       # BB#0:
-; ALL-NEXT:    andi. 3, 3, 1
-; ALL-NEXT:    bc 12, 1, .LBB34_2
-; ALL-NEXT:  # BB#1:
-; ALL-NEXT:    addis 3, 2, .LCPI34_0@toc@ha
-; ALL-NEXT:    addi 3, 3, .LCPI34_0@toc@l
-; ALL-NEXT:    lxsdx 0, 0, 3
-; ALL-NEXT:    b .LBB34_3
-; ALL-NEXT:  .LBB34_2:
-; ALL-NEXT:    addis 3, 2, .LCPI34_1@toc@ha
-; ALL-NEXT:    addi 3, 3, .LCPI34_1@toc@l
-; ALL-NEXT:    lxsspx 0, 0, 3
-; ALL-NEXT:  .LBB34_3:
-; ALL-NEXT:    addis 3, 2, .LCPI34_2@toc@ha
-; ALL-NEXT:    addi 3, 3, .LCPI34_2@toc@l
-; ALL-NEXT:    lxsdx 1, 0, 3
-; ALL-NEXT:    xsadddp 1, 0, 1
-; ALL-NEXT:    blr
   %sel = select i1 %cond, double -4.0, double 23.3
   %bo = fadd double %sel, 5.1
   ret double %bo
 }
 
 define double @sel_constants_fsub_constant(i1 %cond) {
-; ALL-LABEL: sel_constants_fsub_constant:
-; ALL:       # BB#0:
-; ALL-NEXT:    andi. 3, 3, 1
-; ALL-NEXT:    bc 12, 1, .LBB35_2
-; ALL-NEXT:  # BB#1:
-; ALL-NEXT:    addis 3, 2, .LCPI35_0@toc@ha
-; ALL-NEXT:    addi 3, 3, .LCPI35_0@toc@l
-; ALL-NEXT:    lxsdx 0, 0, 3
-; ALL-NEXT:    b .LBB35_3
-; ALL-NEXT:  .LBB35_2:
-; ALL-NEXT:    addis 3, 2, .LCPI35_1@toc@ha
-; ALL-NEXT:    addi 3, 3, .LCPI35_1@toc@l
-; ALL-NEXT:    lxsspx 0, 0, 3
-; ALL-NEXT:  .LBB35_3:
-; ALL-NEXT:    addis 3, 2, .LCPI35_2@toc@ha
-; ALL-NEXT:    addi 3, 3, .LCPI35_2@toc@l
-; ALL-NEXT:    lxsdx 1, 0, 3
-; ALL-NEXT:    xsadddp 1, 0, 1
-; ALL-NEXT:    blr
+; ISEL-LABEL: sel_constants_fsub_constant:
+; ISEL:       # BB#0:
+; ISEL-NEXT:    andi. 3, 3, 1
+; ISEL-NEXT:    addis 4, 2, .LCPI35_0@toc@ha
+; ISEL-NEXT:    addis 3, 2, .LCPI35_1@toc@ha
+; ISEL-NEXT:    addi 4, 4, .LCPI35_0@toc@l
+; ISEL-NEXT:    addi 3, 3, .LCPI35_1@toc@l
+; ISEL-NEXT:    isel 3, 3, 4, 1
+; ISEL-NEXT:    lxsdx 1, 0, 3
+; ISEL-NEXT:    blr
+;
+; NO_ISEL-LABEL: sel_constants_fsub_constant:
+; NO_ISEL:       # BB#0:
+; NO_ISEL-NEXT:    andi. 3, 3, 1
+; NO_ISEL-NEXT:    addis 4, 2, .LCPI35_0@toc@ha
+; NO_ISEL-NEXT:    addis 3, 2, .LCPI35_1@toc@ha
+; NO_ISEL-NEXT:    addi 4, 4, .LCPI35_0@toc@l
+; NO_ISEL-NEXT:    addi 3, 3, .LCPI35_1@toc@l
+; NO_ISEL-NEXT:    bc 12, 1, .LBB35_2
+; NO_ISEL-NEXT:  # BB#1:
+; NO_ISEL-NEXT:    ori 3, 4, 0
+; NO_ISEL-NEXT:    b .LBB35_2
+; NO_ISEL-NEXT:  .LBB35_2:
+; NO_ISEL-NEXT:    lxsdx 1, 0, 3
+; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, double -4.0, double 23.3
   %bo = fsub double %sel, 5.1
   ret double %bo
 }
 
 define double @sel_constants_fmul_constant(i1 %cond) {
-; ALL-LABEL: sel_constants_fmul_constant:
-; ALL:       # BB#0:
-; ALL-NEXT:    andi. 3, 3, 1
-; ALL-NEXT:    bc 12, 1, .LBB36_2
-; ALL-NEXT:  # BB#1:
-; ALL-NEXT:    addis 3, 2, .LCPI36_0@toc@ha
-; ALL-NEXT:    addi 3, 3, .LCPI36_0@toc@l
-; ALL-NEXT:    lxsdx 0, 0, 3
-; ALL-NEXT:    b .LBB36_3
-; ALL-NEXT:  .LBB36_2:
-; ALL-NEXT:    addis 3, 2, .LCPI36_1@toc@ha
-; ALL-NEXT:    addi 3, 3, .LCPI36_1@toc@l
-; ALL-NEXT:    lxsspx 0, 0, 3
-; ALL-NEXT:  .LBB36_3:
-; ALL-NEXT:    addis 3, 2, .LCPI36_2@toc@ha
-; ALL-NEXT:    addi 3, 3, .LCPI36_2@toc@l
-; ALL-NEXT:    lxsdx 1, 0, 3
-; ALL-NEXT:    xsmuldp 1, 0, 1
-; ALL-NEXT:    blr
+; ISEL-LABEL: sel_constants_fmul_constant:
+; ISEL:       # BB#0:
+; ISEL-NEXT:    andi. 3, 3, 1
+; ISEL-NEXT:    addis 4, 2, .LCPI36_0@toc@ha
+; ISEL-NEXT:    addis 3, 2, .LCPI36_1@toc@ha
+; ISEL-NEXT:    addi 4, 4, .LCPI36_0@toc@l
+; ISEL-NEXT:    addi 3, 3, .LCPI36_1@toc@l
+; ISEL-NEXT:    isel 3, 3, 4, 1
+; ISEL-NEXT:    lxsdx 1, 0, 3
+; ISEL-NEXT:    blr
+;
+; NO_ISEL-LABEL: sel_constants_fmul_constant:
+; NO_ISEL:       # BB#0:
+; NO_ISEL-NEXT:    andi. 3, 3, 1
+; NO_ISEL-NEXT:    addis 4, 2, .LCPI36_0@toc@ha
+; NO_ISEL-NEXT:    addis 3, 2, .LCPI36_1@toc@ha
+; NO_ISEL-NEXT:    addi 4, 4, .LCPI36_0@toc@l
+; NO_ISEL-NEXT:    addi 3, 3, .LCPI36_1@toc@l
+; NO_ISEL-NEXT:    bc 12, 1, .LBB36_2
+; NO_ISEL-NEXT:  # BB#1:
+; NO_ISEL-NEXT:    ori 3, 4, 0
+; NO_ISEL-NEXT:    b .LBB36_2
+; NO_ISEL-NEXT:  .LBB36_2:
+; NO_ISEL-NEXT:    lxsdx 1, 0, 3
+; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, double -4.0, double 23.3
   %bo = fmul double %sel, 5.1
   ret double %bo
 }
 
 define double @sel_constants_fdiv_constant(i1 %cond) {
-; ALL-LABEL: sel_constants_fdiv_constant:
-; ALL:       # BB#0:
-; ALL-NEXT:    andi. 3, 3, 1
-; ALL-NEXT:    bc 12, 1, .LBB37_2
-; ALL-NEXT:  # BB#1:
-; ALL-NEXT:    addis 3, 2, .LCPI37_0@toc@ha
-; ALL-NEXT:    addi 3, 3, .LCPI37_0@toc@l
-; ALL-NEXT:    lxsdx 0, 0, 3
-; ALL-NEXT:    b .LBB37_3
-; ALL-NEXT:  .LBB37_2:
-; ALL-NEXT:    addis 3, 2, .LCPI37_1@toc@ha
-; ALL-NEXT:    addi 3, 3, .LCPI37_1@toc@l
-; ALL-NEXT:    lxsspx 0, 0, 3
-; ALL-NEXT:  .LBB37_3:
-; ALL-NEXT:    addis 3, 2, .LCPI37_2@toc@ha
-; ALL-NEXT:    addi 3, 3, .LCPI37_2@toc@l
-; ALL-NEXT:    lxsdx 1, 0, 3
-; ALL-NEXT:    xsdivdp 1, 0, 1
-; ALL-NEXT:    blr
+; ISEL-LABEL: sel_constants_fdiv_constant:
+; ISEL:       # BB#0:
+; ISEL-NEXT:    andi. 3, 3, 1
+; ISEL-NEXT:    addis 4, 2, .LCPI37_0@toc@ha
+; ISEL-NEXT:    addis 3, 2, .LCPI37_1@toc@ha
+; ISEL-NEXT:    addi 4, 4, .LCPI37_0@toc@l
+; ISEL-NEXT:    addi 3, 3, .LCPI37_1@toc@l
+; ISEL-NEXT:    isel 3, 3, 4, 1
+; ISEL-NEXT:    lxsdx 1, 0, 3
+; ISEL-NEXT:    blr
+;
+; NO_ISEL-LABEL: sel_constants_fdiv_constant:
+; NO_ISEL:       # BB#0:
+; NO_ISEL-NEXT:    andi. 3, 3, 1
+; NO_ISEL-NEXT:    addis 4, 2, .LCPI37_0@toc@ha
+; NO_ISEL-NEXT:    addis 3, 2, .LCPI37_1@toc@ha
+; NO_ISEL-NEXT:    addi 4, 4, .LCPI37_0@toc@l
+; NO_ISEL-NEXT:    addi 3, 3, .LCPI37_1@toc@l
+; NO_ISEL-NEXT:    bc 12, 1, .LBB37_2
+; NO_ISEL-NEXT:  # BB#1:
+; NO_ISEL-NEXT:    ori 3, 4, 0
+; NO_ISEL-NEXT:    b .LBB37_2
+; NO_ISEL-NEXT:  .LBB37_2:
+; NO_ISEL-NEXT:    lxsdx 1, 0, 3
+; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, double -4.0, double 23.3
   %bo = fdiv double %sel, 5.1
   ret double %bo
 }
 
 define double @sel_constants_frem_constant(i1 %cond) {
 ; ALL-LABEL: sel_constants_frem_constant:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    andi. 3, 3, 1
 ; ALL-NEXT:    bc 12, 1, .LBB38_2
 ; ALL-NEXT:  # BB#1:
 ; ALL-NEXT:    addis 3, 2, .LCPI38_0@toc@ha
 ; ALL-NEXT:    addi 3, 3, .LCPI38_0@toc@l
 ; ALL-NEXT:    lxsdx 1, 0, 3
-; ALL-NEXT:    b .LBB38_3
+; ALL-NEXT:    blr
 ; ALL-NEXT:  .LBB38_2:
 ; ALL-NEXT:    addis 3, 2, .LCPI38_1@toc@ha
 ; ALL-NEXT:    addi 3, 3, .LCPI38_1@toc@l
 ; ALL-NEXT:    lxsspx 1, 0, 3
-; ALL-NEXT:  .LBB38_3:
-; ALL-NEXT:    mflr 0
-; ALL-NEXT:    std 0, 16(1)
-; ALL-NEXT:    stdu 1, -96(1)
-; ALL-NEXT:  .Lcfi0:
-; ALL-NEXT:    .cfi_def_cfa_offset 96
-; ALL-NEXT:  .Lcfi1:
-; ALL-NEXT:    .cfi_offset lr, 16
-; ALL-NEXT:    addis 3, 2, .LCPI38_2@toc@ha
-; ALL-NEXT:    addi 3, 3, .LCPI38_2@toc@l
-; ALL-NEXT:    lxsdx 2, 0, 3
-; ALL-NEXT:    bl fmod
-; ALL-NEXT:    nop
-; ALL-NEXT:    addi 1, 1, 96
-; ALL-NEXT:    ld 0, 16(1)
-; ALL-NEXT:    mtlr 0
 ; ALL-NEXT:    blr
   %sel = select i1 %cond, double -4.0, double 23.3
   %bo = frem double %sel, 5.1
   ret double %bo
 }
 

test/CodeGen/X86/2010-08-04-MaskedSignedCompare.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
 ; PR7814
 
 @g_16 = global i64 -3738643449681751625, align 8
 @g_38 = global i32 0, align 4
 @.str = private constant [4 x i8] c"%d\0A\00"
 
 define i32 @main() nounwind {
 ; CHECK-LABEL: main:
 ; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cmpq $0, {{.*}}(%rip)
+; CHECK-NEXT:    movb $-106, %al
+; CHECK-NEXT:    jne .LBB0_2
+; CHECK-NEXT:  # BB#1: # %entry
 ; CHECK-NEXT:    xorl %eax, %eax
-; CHECK-NEXT:    cmpq {{.*}}(%rip), %rax
-; CHECK-NEXT:    sbbl %eax, %eax
-; CHECK-NEXT:    andl $150, %eax
+; CHECK-NEXT:  .LBB0_2: # %entry
 ; CHECK-NEXT:    testb %al, %al
-; CHECK-NEXT:    jle .LBB0_1
-; CHECK-NEXT:  # BB#2: # %if.then
+; CHECK-NEXT:    jle .LBB0_3
+; CHECK-NEXT:  # BB#4: # %if.then
 ; CHECK-NEXT:    movl $1, {{.*}}(%rip)
 ; CHECK-NEXT:    movl $1, %esi
-; CHECK-NEXT:    jmp .LBB0_3
-; CHECK-NEXT:  .LBB0_1: # %entry.if.end_crit_edge
+; CHECK-NEXT:    jmp .LBB0_5
+; CHECK-NEXT:  .LBB0_3: # %entry.if.end_crit_edge
 ; CHECK-NEXT:    movl {{.*}}(%rip), %esi
-; CHECK-NEXT:  .LBB0_3: # %if.end
+; CHECK-NEXT:  .LBB0_5: # %if.end
 ; CHECK-NEXT:    pushq %rax
 ; CHECK-NEXT:    movl $.L.str, %edi
 ; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    callq printf
 ; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    popq %rcx
 ; CHECK-NEXT:    retq
 entry:

test/CodeGen/X86/avx512-insert-extract.ll

 ; SKX-LABEL: extractelement_v2i1_alt:
 ; SKX:       ## BB#0:
 ; SKX-NEXT:    vpcmpnleuq %xmm1, %xmm0, %k0
 ; SKX-NEXT:    kshiftlw $15, %k0, %k0
 ; SKX-NEXT:    kshiftrw $15, %k0, %k0
 ; SKX-NEXT:    kmovw %k0, %eax
 ; SKX-NEXT:    andl $1, %eax
 ; SKX-NEXT:    testb %al, %al
-; SKX-NEXT:    je LBB51_2
-; SKX-NEXT:  ## BB#1:
-; SKX-NEXT:    movb $-1, %al
-; SKX-NEXT:  LBB51_2:
-; SKX-NEXT:    addb $4, %al
+; SKX-NEXT:    sete %al
+; SKX-NEXT:    addb $3, %al
 ; SKX-NEXT:    movzbl %al, %eax
 ; SKX-NEXT:    retq
   %t1 = icmp ugt <2 x i64> %a, %b
   %t2 = extractelement <2 x i1> %t1, i32 0
   %sext = sext i1 %t2 to i8
   %res = add i8 %sext, 4
   ret i8 %res
 }

 ;
 ; SKX-LABEL: extractelement_v64i1_alt:
 ; SKX:       ## BB#0:
 ; SKX-NEXT:    vpcmpnleub %zmm1, %zmm0, %k0
 ; SKX-NEXT:    kshiftrq $63, %k0, %k0
 ; SKX-NEXT:    kmovw %k0, %eax
 ; SKX-NEXT:    andl $1, %eax
 ; SKX-NEXT:    testb %al, %al
-; SKX-NEXT:    je LBB55_2
-; SKX-NEXT:  ## BB#1:
-; SKX-NEXT:    movb $-1, %al
-; SKX-NEXT:  LBB55_2:
-; SKX-NEXT:    addb $4, %al
+; SKX-NEXT:    sete %al
+; SKX-NEXT:    addb $3, %al
 ; SKX-NEXT:    movzbl %al, %eax
 ; SKX-NEXT:    retq
   %t1 = icmp ugt <64 x i8> %a, %b
   %t2 = extractelement <64 x i1> %t1, i32 63
   %sext = sext i1 %t2 to i8
   %res = add i8 %sext, 4
   ret i8 %res
 }

test/CodeGen/X86/setcc.ll

 
 @v4 = common global i32 0, align 4
 
 define i32 @t4(i32 %a) {
 ; CHECK-LABEL: t4:
 ; CHECK:       ## BB#0:
 ; CHECK-NEXT:    movq _v4@{{.*}}(%rip), %rax
 ; CHECK-NEXT:    cmpl $1, (%rax)
-; CHECK-NEXT:    sbbl %eax, %eax
-; CHECK-NEXT:    andl $32768, %eax ## imm = 0x8000
-; CHECK-NEXT:    leal 65536(%rax,%rax), %eax
+; CHECK-NEXT:    movw $1, %ax
+; CHECK-NEXT:    adcw $0, %ax
+; CHECK-NEXT:    shll $16, %eax
 ; CHECK-NEXT:    retq
   %t0 = load i32, i32* @v4, align 4
   %not.tobool = icmp eq i32 %t0, 0
   %conv.i = sext i1 %not.tobool to i16
   %call.lobit = lshr i16 %conv.i, 15
   %add.i.1 = add nuw nsw i16 %call.lobit, 1
   %conv4.2 = zext i16 %add.i.1 to i32
   %add = shl nuw nsw i32 %conv4.2, 16