[PowerPC] Expand compare instructions to equivalent GPR code sequences.

[jtony]

Summary

The patterns (equal, equal to zero, great or equal to zero, signed great than zero, signed less or equal than, signed less than) that used to generate cmpw which sets CR bits are replaced by specific GPR code sequences that are outlined in the Compiler Writer's Guide (Appendix D). This will help us reduce the number of CR logical operations used.

This initial patch only handles those patterns that could be implemented in PPCInstrInfo.td. More patterns will be implemented in PPCISelDAGToDAG.cpp file in the next patch because of the limitation of table-gen (cannot handle multiple outs).

Note: that some of the test cases are added to test already existing patterns, that's why we have more test cases than patterns.

Also, the SETEQ pattern implemented here in the .td file could also be done in PPCISelDAGToDAG.cpp.

[inouehrs]

Comparison is often used with bit operators, like an example below.
In this example, as long as I test, the transformation is applied only when POS is 0; cmpd + isel are used for cases with POS > 0.
I feel it is nice if we can support comparisons used with bit operators.

const int POS = 1;
long set_flag(long a, long b, long flags) {
	flags |= ((a == b) << POS);
	return flags;
}

[hfinkel]

lib/Target/PowerPC/PPCInstrInfo.td

3162

Please indent this by one more space so the O is under the C.

3166

Indent by one.

3174

Please indent for the P to be under the S.

3267

// This happens frequently because instruction selection will concert SETLE 0 to SETLT 1.

(abbreviating instruction selection as ISEL is confusing in this context because we also have an ISEL instruction).

[jtony]

In D30469#691316, @inouehrs wrote:

Comparison is often used with bit operators, like an example below.
In this example, as long as I test, the transformation is applied only when POS is 0; cmpd + isel are used for cases with POS > 0.
I feel it is nice if we can support comparisons used with bit operators.

const int POS = 1;
long set_flag(long a, long b, long flags) {
	flags |= ((a == b) << POS);
	return flags;
}

Hi Hiroshi, that happens because current the SETEQ is implemented in the PPCInstrInfo.td file, which is downstream of DAG2DAG slection, I checked the debug info for the test case you provided here. The zero_extend(setcc) pattern is got converted to select_cc before it has a chance to use the pattern that I added in td file. One possible solution is do that in the DAG2DAG stage like all the other patterns in the CWG, this is a similar issue Nemanja and I have encountered for these pattern in D.2 of CWG. And there is also a new commit from trunk changes the conversion behavior from setcc to select_cc. I haven't tried what is the influence of that commit so I am not sure whether we should move this implementation here to the PPCISelDAG2DAG.cpp file or not. I will let Kit and Nemanja decide.

[jtony]

Resolve Hal's comments.

[nemanjai]

In D30469#692017, @jtony wrote:

In D30469#691316, @inouehrs wrote:

Comparison is often used with bit operators, like an example below.
In this example, as long as I test, the transformation is applied only when POS is 0; cmpd + isel are used for cases with POS > 0.
I feel it is nice if we can support comparisons used with bit operators.

const int POS = 1;
long set_flag(long a, long b, long flags) {
	flags |= ((a == b) << POS);
	return flags;
}

Hi Hiroshi, that happens because current the SETEQ is implemented in the PPCInstrInfo.td file, which is downstream of DAG2DAG slection, I checked the debug info for the test case you provided here. The zero_extend(setcc) pattern is got converted to select_cc before it has a chance to use the pattern that I added in td file. One possible solution is do that in the DAG2DAG stage like all the other patterns in the CWG, this is a similar issue Nemanja and I have encountered for these pattern in D.2 of CWG. And there is also a new commit from trunk changes the conversion behavior from setcc to select_cc. I haven't tried what is the influence of that commit so I am not sure whether we should move this implementation here to the PPCISelDAG2DAG.cpp file or not. I will let Kit and Nemanja decide.

This will be handled in a subsequent patch.

[jtony]

Update the test cases according to the new convention. 16 test cases file added for SETCC EQ.

[jtony]

The SETCC EQ pattern implemented here are moved to PPCISelDAGToDAG.cpp file in a following up patch, abandon this one.

lib/Target/PowerPC/PPCInstrInfo.td

multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag,
   def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))),
             (rfrag8 $s1)>;
   def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))),
             (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
   def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))),
             (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
 }
 
+multiclass ExtSetCCPat2<CondCode cc, PatFrag pfrag,
+                        OutPatFrag rfrag, OutPatFrag rfrag8> {
+    def : Pat<(i32 (zext (i1 (pfrag i32:$s1, i32:$s2, cc)))),
+              (rfrag $s1, $s2)>;
+    def : Pat<(i64 (zext (i1 (pfrag i64:$s1, i64:$s2, cc)))),
+              (rfrag8 $s1, $s2)>;
+    def : Pat<(i64 (zext (i1 (pfrag i32:$s1, i32:$s2, cc)))),
+              (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $s2), sub_32)>;
+    def : Pat<(i32 (zext (i1 (pfrag i64:$s1, i64:$s2, cc)))),
+              (EXTRACT_SUBREG (rfrag8 $s1, $s2), sub_32)>;
+  }
+
+// Instead of using rlwinm Rx,Ry,32-n,n,31, the more clever way rlwinm Rx,Ry,
+// 32-n,31,31 are used to extract just one bit. Similar thing for rldicl.
+defm : ExtSetCCPat2<SETEQ,
+                    PatFrag<(ops node:$in1, node:$in2, node:$cc),
+                            (setcc $in1, $in2, $cc)>,
+                    OutPatFrag<(ops node:$in1, node:$in2),
+                               (RLWINM (CNTLZW (SUBF $in1, $in2)), 27, 31, 31)>,
+                    OutPatFrag<(ops node:$in1, node:$in2),
+                               (RLDICL (CNTLZD (SUBF8 $in1, $in2)), 58, 63)> >;
+
 // Note that we do all inversions below with i(32|64)not, instead of using
 // (xori x, 1) because on the A2 nor has single-cycle latency while xori
 // has 2-cycle latency.
 
 defm : ExtSetCCPat<SETEQ,
                    PatFrag<(ops node:$in, node:$cc),
                            (setcc $in, 0, $cc)>,
                    OutPatFrag<(ops node:$in),

 defm : ExtSetCCPat<SETLE,
                    PatFrag<(ops node:$in, node:$cc),
                            (setcc $in, -1, $cc)>,
                    OutPatFrag<(ops node:$in),
                               (RLWINM $in, 1, 31, 31)>,
                    OutPatFrag<(ops node:$in),
                               (RLDICL $in, 1, 63)> >;
 
+// This happens frequently because instruction selection will convert
+// SETLE 0 to SETLT 1.
+defm : ExtSetCCPat<SETLT,
+                   PatFrag<(ops node:$in, node:$cc),
+                           (setcc $in, 1, $cc)>,
+                   OutPatFrag<(ops node:$in),
+                              (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>,
+                   OutPatFrag<(ops node:$in),
+                              (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >;
+
 // An extended SETCC with shift amount.
 multiclass ExtSetCCShiftPat<CondCode cc, PatFrag pfrag,
                             OutPatFrag rfrag, OutPatFrag rfrag8> {
   def : Pat<(i32 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))),
             (rfrag $s1, $sa)>;
   def : Pat<(i64 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))),
             (rfrag8 $s1, $sa)>;
   def : Pat<(i64 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))),

test/CodeGen/PowerPC/expand-isel.ll

if.end:
   %conv3 = zext i1 %cmp to i32
   br label %cleanup
 
 cleanup:
   %retval.0 = phi i32 [ %conv3, %if.end ], [ 1, %entry ]
   ret i32 %retval.0
 
 ; CHECK-LABEL: @testComplexISEL
-; CHECK: bc 12, 2, [[TRUE:.LBB[0-9]+]]
-; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
-; CHECK-NEXT:  [[TRUE]]
-; CHECK-NEXT: addi r3, r12, 0
-; CHECK-NEXT: [[SUCCESSOR]]
+; CHECK: sub [[REG1:r[0-9]+]], r4, r3
+; CHECK-NEXT: cntlzd [[REG2:r[0-9]+]], [[REG1]]
+; CHECK-NEXT: rldicl [[REG3:r[0-9]+]], [[REG2]], 58, 63
 ; CHECK-NEXT: clrldi r3, r3, 32
 ; CHECK-NEXT: blr
 }
 
 !1 = !{!2, !2, i64 0}
 !2 = !{!"int", !3, i64 0}
 !3 = !{!"omnipotent char", !4, i64 0}
 !4 = !{!"Simple C/C++ TBAA"}

test/CodeGen/PowerPC/expand-setcc.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+
+; Function Attrs: norecurse nounwind readnone
+define zeroext i1 @setcc_eq_i8(i8 signext %v0, i8 signext %v1) {
+entry:
+  %cmp = icmp eq i8 %v0, %v1
+  ret i1 %cmp
+
+; CHECK-LABEL: @setcc_eq_i8
+; CHECK: subf [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT: cntlzw [[REG2:r[0-9]+]], [[REG1]]
+; CHECK-NEXT: rlwinm [[REG3:r[0-9]+]], [[REG2]], 27, 31, 31
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define zeroext i1 @setcc_eq_i16(i16 signext %v0, i16 signext %v1) {
+entry:
+  %cmp = icmp eq i16 %v0, %v1
+  ret i1 %cmp
+
+; CHECK-LABEL: @setcc_eq_i16
+; CHECK: subf [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT: cntlzw [[REG2:r[0-9]+]], [[REG1]]
+; CHECK-NEXT: rlwinm [[REG3:r[0-9]+]], [[REG2]], 27, 31, 31
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define zeroext i1 @setcc_eq_i32(i32 signext %v0, i32 signext %v1) {
+entry:
+  %cmp = icmp eq i32 %v0, %v1
+  ret i1 %cmp
+
+; CHECK-LABEL: @setcc_eq_i32
+; CHECK: subf [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT: cntlzw [[REG2:r[0-9]+]], [[REG1]]
+; CHECK-NEXT: rlwinm [[REG3:r[0-9]+]], [[REG2]], 27, 31, 31
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define zeroext i1 @setcc_eq_i64(i64 signext %v0, i64 signext %v1) {
+entry:
+  %cmp = icmp eq i64 %v0, %v1
+  ret i1 %cmp
+
+; CHECK-LABEL: @setcc_eq_i64
+; CHECK: sub [[REG1:r[0-9]+]], r4, r3
+; CHECK-NEXT: cntlzd [[REG2:r[0-9]+]], [[REG1]]
+; CHECK-NEXT: rldicl [[REG3:r[0-9]+]], [[REG2]], 58, 63
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define zeroext i1 @setcc_eq0_i8(i8 signext %v0) {
+entry:
+  %cmp = icmp eq i8 %v0, 0
+  ret i1 %cmp
+
+; CHECK-LABEL: @setcc_eq0_i8
+; CHECK: cntlzw [[REG1:r[0-9]+]], r3
+; CHECK-NEXT: rlwinm [[REG2:r[0-9]+]], [[REG1]], 27, 31, 31
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define zeroext i1 @setcc_eq0_i16(i16 signext %v0) {
+entry:
+  %cmp = icmp eq i16 %v0, 0
+  ret i1 %cmp
+
+; CHECK-LABEL: @setcc_eq0_i16
+; CHECK: cntlzw [[REG1:r[0-9]+]], r3
+; CHECK-NEXT: rlwinm [[REG2:r[0-9]+]], [[REG1]], 27, 31, 31
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define zeroext i1 @setcc_eq0_i32(i32 signext %v0) {
+entry:
+  %cmp = icmp eq i32 %v0, 0
+  ret i1 %cmp
+
+; CHECK-LABEL: @setcc_eq0_i32
+; CHECK: cntlzw [[REG1:r[0-9]+]], r3
+; CHECK-NEXT: rlwinm [[REG2:r[0-9]+]], [[REG1]], 27, 31, 31
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define zeroext i1 @setcc_eq0_i64(i64 signext %v0) {
+entry:
+  %cmp = icmp eq i64 %v0, 0
+  ret i1 %cmp
+
+; CHECK-LABEL: @setcc_eq0_i64
+; CHECK: cntlzd [[REG1:r[0-9]+]], r3
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 58, 63
+; CHECK-NEXT: blr
+}
+; Function Attrs: norecurse nounwind readnone
+define zeroext i1 @setcc_ges0_i8(i8 signext %v0) {
+entry:
+  %cmp = icmp sge i8 %v0, 0
+  ret i1 %cmp
+
+; CHECK-LABEL: @setcc_ges0_i8
+; CHECK: nor [[REG1:r[0-9]+]], r3
+; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 31
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define zeroext i1 @setcc_ges0_i16(i16 signext %v0) {
+entry:
+  %cmp = icmp sge i16 %v0, 0
+  ret i1 %cmp
+
+; CHECK-LABEL: @setcc_ges0_i16
+; CHECK: nor [[REG1:r[0-9]+]], r3
+; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 31
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define zeroext i1 @setcc_ges0_i32(i32 signext %v0) {
+entry:
+  %cmp = icmp sge i32 %v0, 0
+  ret i1 %cmp
+
+; CHECK-LABEL: @setcc_ges0_i32
+
+; TO DO: note the CHECK-CWG here is for future work.
+; CHECK-CWG: srwi [[REG1:r[0-9]+]], r3, 31
+; CHECK-CWG-NEXT: xori [[REG2:r[0-9]+]], [[REG1]], 1
+; CHECK-CWG-NEXT: blr
+
+; CHECK: nor [[REG1:r[0-9]+]], r3
+; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 31
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define zeroext i1 @setcc_ges0_i64(i64 signext %v0) {
+entry:
+  %cmp = icmp sge i64 %v0, 0
+  ret i1 %cmp
+
+; CHECK-LABEL: @setcc_ges0_i64
+; CHECK: rldicl [[REG1:r[0-9]+]], r3, 1, 63
+; CHECK-NEXT: xori [[REG2:r[0-9]+]], [[REG1]], 1
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define zeroext i1 @setcc_gts0_i8(i8 signext %v0) {
+entry:
+  %cmp = icmp sgt i8 %v0, 0
+  ret i1 %cmp
+
+; CHECK-LABEL: @setcc_gts0_i8
+; CHECK: neg [[REG1:r[0-9]+]], r3
+; CHECK-NEXT: andc [[REG2:r[0-9]+]], [[REG1]], r3
+; CHECK-NEXT: srwi [[REG3:r[0-9]+]], [[REG2]], 31
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define zeroext i1 @setcc_gts0_i16(i16 signext %v0) {
+entry:
+  %cmp = icmp sgt i16 %v0, 0
+  ret i1 %cmp
+
+; CHECK-LABEL: @setcc_gts0_i16
+; CHECK: neg [[REG1:r[0-9]+]], r3
+; CHECK-NEXT: andc [[REG2:r[0-9]+]], [[REG1]], r3
+; CHECK-NEXT: srwi [[REG3:r[0-9]+]], [[REG2]], 31
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define zeroext i1 @setcc_gts0_i32(i32 signext %v0) {
+entry:
+  %cmp = icmp sgt i32 %v0, 0
+  ret i1 %cmp
+
+; CHECK-LABEL: @setcc_gts0_i32
+; CHECK: neg [[REG1:r[0-9]+]], r3
+; CHECK-NEXT: andc [[REG2:r[0-9]+]], [[REG1]], r3
+; CHECK-NEXT: srwi [[REG3:r[0-9]+]], [[REG2]], 31
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define zeroext i1 @setcc_gts0_i64(i64 signext %v0) {
+entry:
+  %cmp = icmp sgt i64 %v0, 0
+  ret i1 %cmp
+
+; CHECK-LABEL: @setcc_gts0_i64
+; CHECK: neg [[REG1:r[0-9]+]], r3
+; CHECK-NEXT: andc [[REG2:r[0-9]+]], [[REG1]], r3
+; CHECK-NEXT: rldicl [[REG3:r[0-9]+]], [[REG2]], 1, 63
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define zeroext i1 @setcc_les0_i8(i8 signext %v0) {
+entry:
+  %cmp = icmp sle i8 %v0, 0
+  ret i1 %cmp
+
+; CHECK-LABEL: @setcc_les0_i8
+; CHECK: neg [[REG1:r[0-9]+]], r3
+; CHECK-NEXT: orc [[REG2:r[0-9]+]], r3, [[REG1]]
+; CHECK-NEXT: srwi [[REG3:r[0-9]+]], [[REG2]], 31
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define zeroext i1 @setcc_les0_i16(i16 signext %v0) {
+entry:
+  %cmp = icmp sle i16 %v0, 0
+  ret i1 %cmp
+
+; CHECK-LABEL: @setcc_les0_i16
+; CHECK: neg [[REG1:r[0-9]+]], r3
+; CHECK-NEXT: orc [[REG2:r[0-9]+]], r3, [[REG1]]
+; CHECK-NEXT: srwi [[REG3:r[0-9]+]], [[REG2]], 31
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define zeroext i1 @setcc_les0_i32(i32 signext %v0) {
+entry:
+  %cmp = icmp sle i32 %v0, 0
+  ret i1 %cmp
+
+; CHECK-LABEL: @setcc_les0_i32
+; CHECK: neg [[REG1:r[0-9]+]], r3
+; CHECK-NEXT: orc [[REG2:r[0-9]+]], r3, [[REG1]]
+; CHECK-NEXT: srwi [[REG3:r[0-9]+]], [[REG2]], 31
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define zeroext i1 @setcc_les0_i64(i64 signext %v0) {
+entry:
+  %cmp = icmp sle i64 %v0, 0
+  ret i1 %cmp
+
+; CHECK-LABEL: @setcc_les0_i64
+; CHECK: neg [[REG1:r[0-9]+]], r3
+; CHECK-NEXT: orc [[REG2:r[0-9]+]], r3, [[REG1]]
+; CHECK-NEXT: rldicl [[REG3:r[0-9]+]], [[REG2]], 1, 63
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define zeroext i1 @setcc_lts0_i8(i8 signext %v0) {
+entry:
+  %cmp = icmp slt i8 %v0, 0
+  ret i1 %cmp
+
+; CHECK-LABEL: @setcc_lts0_i8
+; CHECK: srwi [[REG1:r[0-9]+]], r3, 31
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define zeroext i1 @setcc_lts0_i16(i16 signext %v0) {
+entry:
+  %cmp = icmp slt i16 %v0, 0
+  ret i1 %cmp
+
+; CHECK-LABEL: @setcc_lts0_i16
+; CHECK: srwi [[REG1:r[0-9]+]], r3, 31
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define zeroext i1 @setcc_lts0_i32(i32 signext %v0) {
+entry:
+  %cmp = icmp slt i32 %v0, 0
+  ret i1 %cmp
+
+; CHECK-LABEL: @setcc_lts0_i32
+; CHECK: srwi [[REG1:r[0-9]+]], r3, 31
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define zeroext i1 @setcc_lts0_i64(i64 signext %v0) {
+entry:
+  %cmp = icmp slt i64 %v0, 0
+  ret i1 %cmp
+
+; CHECK-LABEL: @setcc_lts0_i64
+; CHECK: rldicl [[REG1:r[0-9]+]], r3, 1, 63
+; CHECK-NEXT: blr
+}