[SelectionDAG] Make SelectionDAG aware of the known bits in USUBO and SSUBO and SUBC.

[deadalnix]

Summary

Depends on D30379

This improves the state of things for the sub class of operation.

[RKSimon]

Is there a test for ISD::SUBC ?

[deadalnix]

The test case in 32 bits is legalizing using SUBC but the it doesn't looks like the backend is able to find any optimization with the freed bits. I could come up with an example, but it would end up being contrived and I'm not sure it is worth it because the plan it to switch to USUBO/SUBCARRY anyway. I did not included SUBE in the list because it needs a different pattern, but I don't see a problem having SUBC in there.

[RKSimon]

Makes sense - LGTM

[deadalnix]

Rebase on top of the changes in D30379

[deadalnix]

Rebase and use setBits;

[RKSimon]

LGTM

llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

case ISD::SELECT_CC:
     if (!KnownOne && !KnownZero)
       break;
     computeKnownBits(Op.getOperand(2), KnownZero2, KnownOne2, Depth+1);
 
     // Only known if known in both the LHS and RHS.
     KnownOne &= KnownOne2;
     KnownZero &= KnownZero2;
     break;
-  case ISD::SSUBO:
-  case ISD::USUBO:
   case ISD::SMULO:
   case ISD::UMULO:
     if (Op.getResNo() != 1)
       break;
     // The boolean result conforms to getBooleanContents.
     // If we know the result of a setcc has the top bits zero, use this info.
     // We know that we have an integer-based boolean since these operations
     // are only available for integer.
case ISD::AssertZext: {
     KnownZero |= (~InMask);
     KnownOne  &= (~KnownZero);
     break;
   }
   case ISD::FGETSIGN:
     // All bits are zero except the low bit.
     KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - 1);
     break;
-
-  case ISD::SUB: {
+  case ISD::USUBO:
+  case ISD::SSUBO:
+    if (Op.getResNo() == 1) {
+      // If we know the result of a setcc has the top bits zero, use this info.
+      if (TLI->getBooleanContents(Op.getOperand(0).getValueType()) ==
+              TargetLowering::ZeroOrOneBooleanContent &&
+          BitWidth > 1)
+        KnownZero.setBits(1, BitWidth);
+      break;
+    }
+    LLVM_FALLTHROUGH;
+  case ISD::SUB:
+  case ISD::SUBC: {
     if (ConstantSDNode *CLHS = isConstOrConstSplat(Op.getOperand(0))) {
       // We know that the top bits of C-X are clear if X contains less bits
       // than C (i.e. no wrap-around can happen).  For example, 20-X is
       // positive if we can prove that X is >= 0 and < 16.
       if (CLHS->getAPIntValue().isNonNegative()) {
         unsigned NLZ = (CLHS->getAPIntValue()+1).countLeadingZeros();
         // NLZ can't be BitWidth with no sign bit
         APInt MaskV = APInt::getHighBitsSet(BitWidth, NLZ+1);

llvm/trunk/test/CodeGen/X86/known-bits.ll

 ; X32-NEXT:    xorl %eax, %eax
 ; X32-NEXT:    popl %ebx
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: knownbits_usubo_ssubo:
 ; X64:       # BB#0:
 ; X64-NEXT:    shlq $32, %rdi
 ; X64-NEXT:    shlq $32, %rsi
-; X64-NEXT:    subq %rsi, %rdi
-; X64-NEXT:    setb %cl
+; X64-NEXT:    cmpq %rsi, %rdi
+; X64-NEXT:    setb %al
 ; X64-NEXT:    seto %dl
-; X64-NEXT:    leal (%rdi,%rdi), %eax
-; X64-NEXT:    orb %cl, %dl
+; X64-NEXT:    orb %al, %dl
+; X64-NEXT:    xorl %eax, %eax
 ; X64-NEXT:    retq
   %1 = shl i64 %a0, 32
   %2 = shl i64 %a1, 32
   %u = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %1, i64 %2)
   %uval = extractvalue {i64, i1} %u, 0
   %uovf = extractvalue {i64, i1} %u, 1
   %s = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %1, i64 %2)
   %sval = extractvalue {i64, i1} %s, 0