[AMDGPU] Fix read-undef flags when schedule is reverted

[rampitec]

Summary

If two subregs of the same register are defined and we need to revert
schedule changing def order, we will end up with both instructions
having def,read-undef flags because adjustLaneLiveness() will only set
this flag but will not remove it.

Fix this by removing read-undef flags before calling adjustLaneLiveness.

[arsenm]

lib/Target/AMDGPU/GCNSchedStrategy.cpp

354–355

This doesn't handle implicit defs

[rampitec]

Also process implicit defs.

lib/Target/AMDGPU/GCNSchedStrategy.cpp

354–355

Yes, fixed.

[rampitec]

Run all instructions through flags update loop, even if not moved. Flags can be affected by other instructions moved around this one.

[rampitec]

Fixed typo in transferring patch.

[vpykhtin]

LGTM.

lib/Target/AMDGPU/GCNSchedStrategy.cpp

if (WavesAfter >= WavesUnsched)
     return;
 
   DEBUG(dbgs() << "Attempting to revert scheduling.\n");
   RegionEnd = RegionBegin;
   for (MachineInstr *MI : Unsched) {
     if (MI->getIterator() != RegionEnd) {
       BB->remove(MI);
       BB->insert(RegionEnd, MI);
-      if (LIS) {
+      if (LIS)
         LIS->handleMove(*MI, true);
-        RegisterOperands RegOpers;
-        RegOpers.collect(*MI, *TRI, MRI, ShouldTrackLaneMasks, false);
-        if (ShouldTrackLaneMasks) {
-          // Adjust liveness and add missing dead+read-undef flags.
-          SlotIndex SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();
-          RegOpers.adjustLaneLiveness(*LIS, MRI, SlotIdx, MI);
-        } else {
-          // Adjust for missing dead-def flags.
-          RegOpers.detectDeadDefs(*MI, *LIS);
-        }
-      }
-    }
+    }
+    // Reset read-undef flags and update them later.
+    for (auto &Op : MI->operands())
+      if (Op.isReg() && Op.isDef())
+        Op.setIsUndef(false);
     RegionEnd = MI->getIterator();
     ++RegionEnd;
     DEBUG(dbgs() << "Scheduling " << *MI);
   }
   RegionBegin = Unsched.front()->getIterator();
 
   placeDebugValues();
 }