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Differential D30428

[AMDGPU] Fix read-undef flags when schedule is reverted
ClosedPublic

Authored by rampitec on Feb 27 2017, 1:24 PM.

Details

Reviewers
vpykhtin
arsenm
alex-t
Commits
rG080889cad77a: [AMDGPU] Fix read-undef flags when schedule is reverted
rL296484: [AMDGPU] Fix read-undef flags when schedule is reverted
Summary

If two subregs of the same register are defined and we need to revert
schedule changing def order, we will end up with both instructions
having def,read-undef flags because adjustLaneLiveness() will only set
this flag but will not remove it.

Fix this by removing read-undef flags before calling adjustLaneLiveness.

Diff Detail

Repository
rL LLVM

Event Timeline

rampitec created this revision.Feb 27 2017, 1:24 PM
Herald added subscribers: tpr, dstuttard, tony-tye and 5 others. · View Herald TranscriptFeb 27 2017, 1:24 PM
arsenm added inline comments.Feb 27 2017, 1:28 PM
lib/Target/AMDGPU/GCNSchedStrategy.cpp
354–355 ↗(On Diff #89924)

This doesn't handle implicit defs

rampitec updated this revision to Diff 89936.Feb 27 2017, 2:11 PM
rampitec marked an inline comment as done.
rampitec added a reviewer: arsenm.

Also process implicit defs.

lib/Target/AMDGPU/GCNSchedStrategy.cpp
354–355 ↗(On Diff #89924)

Yes, fixed.

rampitec updated this revision to Diff 89965.Feb 27 2017, 7:52 PM

Run all instructions through flags update loop, even if not moved. Flags can be affected by other instructions moved around this one.

rampitec updated this revision to Diff 89969.Feb 27 2017, 8:08 PM

Fixed typo in transferring patch.

rampitec added a child revision: D30442: [AMDGPU] Add second pass of the scheduler.Feb 27 2017, 8:48 PM
vpykhtin accepted this revision.Feb 28 2017, 7:26 AM

LGTM.

This revision is now accepted and ready to land.Feb 28 2017, 7:26 AM
Closed by commit rL296484: [AMDGPU] Fix read-undef flags when schedule is reverted (authored by rampitec). · Explain WhyFeb 28 2017, 8:38 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AMDGPU/
27 lines

Diff 90044

llvm/trunk/lib/Target/AMDGPU/GCNSchedStrategy.cpp

Show First 20 Lines • Show All 342 Lines • ▼ Show 20 Lines if (WavesAfter >= WavesUnsched)
return; return;
DEBUG(dbgs() << "Attempting to revert scheduling.\n"); DEBUG(dbgs() << "Attempting to revert scheduling.\n");
RegionEnd = RegionBegin; RegionEnd = RegionBegin;
for (MachineInstr *MI : Unsched) { for (MachineInstr *MI : Unsched) {
if (MI->getIterator() != RegionEnd) { if (MI->getIterator() != RegionEnd) {
BB->remove(MI); BB->remove(MI);
BB->insert(RegionEnd, MI); BB->insert(RegionEnd, MI);
if (LIS) { if (LIS)
LIS->handleMove(*MI, true); LIS->handleMove(*MI, true);
}
// Reset read-undef flags and update them later.
for (auto &Op : MI->operands())
if (Op.isReg() && Op.isDef())
Op.setIsUndef(false);
RegisterOperands RegOpers; RegisterOperands RegOpers;
RegOpers.collect(*MI, *TRI, MRI, ShouldTrackLaneMasks, false); RegOpers.collect(*MI, *TRI, MRI, ShouldTrackLaneMasks, false);
if (ShouldTrackLaneMasks) { if (ShouldTrackLaneMasks) {
// Adjust liveness and add missing dead+read-undef flags. // Adjust liveness and add missing dead+read-undef flags.
SlotIndex SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot(); SlotIndex SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();
RegOpers.adjustLaneLiveness(*LIS, MRI, SlotIdx, MI); RegOpers.adjustLaneLiveness(*LIS, MRI, SlotIdx, MI);
} else { } else {
// Adjust for missing dead-def flags. // Adjust for missing dead-def flags.
RegOpers.detectDeadDefs(*MI, *LIS); RegOpers.detectDeadDefs(*MI, *LIS);
} }
}
}
RegionEnd = MI->getIterator(); RegionEnd = MI->getIterator();
++RegionEnd; ++RegionEnd;
DEBUG(dbgs() << "Scheduling " << *MI); DEBUG(dbgs() << "Scheduling " << *MI);
} }
RegionBegin = Unsched.front()->getIterator(); RegionBegin = Unsched.front()->getIterator();
placeDebugValues(); placeDebugValues();
} }