Remove CRC32 instructions from AArch64InstrInfo::hasShiftedReg

[azharudd]

Summary

A53 scheduler causes an assertion failure on all CRC instructions:
include/llvm/CodeGen/MachineInstr.h:280: const llvm::MachineOperand
&llvm::MachineInstr::getOperand(unsigned int) const: Assertion `i <
getNumOperands() && "getOperand() out of range!"' failed.

The case statements corresponding to CRC instructions are incorrect and should
be removed.

Also adding a testcase while on this.

[rengolin]

test/CodeGen/AArch64/arm64-crc32.ll

2 ↗

(On Diff #89422)

Why is this new run line related? Maybe add this to the commit message would help.

[rengolin]

Can you update the context around using git diff -U999?

[rengolin]

Hi, right, so Tim has approved it on the mailing list, which didn't get transferred here.

But he also said an additional interesting point why you have to use mcpu and not another mattr: this is a code path that only triggers with A53 because of its scheduler.

LGTM, too. Can you just add the scheduler info (instead of just saying it hits with A53) on the commit line?

thanks!

[azharudd]

Updated the context around the change.

[azharudd]

In D30274#692395, @rengolin wrote:

Can you update the context around using git diff -U999?

Thanks Renato. I have updated it.

[azharudd]

In D30274#692397, @rengolin wrote:

Hi, right, so Tim has approved it on the mailing list, which didn't get transferred here.

But he also said an additional interesting point why you have to use mcpu and not another mattr: this is a code path that only triggers with A53 because of its scheduler.

LGTM, too. Can you just add the scheduler info (instead of just saying it hits with A53) on the commit line?

thanks!

Updated the commit message to mention the A53 scheduler.

llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp

bool AArch64InstrInfo::hasShiftedReg(const MachineInstr &MI) const {
   case AArch64::ANDSWrs:
   case AArch64::ANDSXrs:
   case AArch64::ANDWrs:
   case AArch64::ANDXrs:
   case AArch64::BICSWrs:
   case AArch64::BICSXrs:
   case AArch64::BICWrs:
   case AArch64::BICXrs:
-  case AArch64::CRC32Brr:
-  case AArch64::CRC32CBrr:
-  case AArch64::CRC32CHrr:
-  case AArch64::CRC32CWrr:
-  case AArch64::CRC32CXrr:
-  case AArch64::CRC32Hrr:
-  case AArch64::CRC32Wrr:
-  case AArch64::CRC32Xrr:
   case AArch64::EONWrs:
   case AArch64::EONXrs:
   case AArch64::EORWrs:
   case AArch64::EORXrs:
   case AArch64::ORNWrs:
   case AArch64::ORNXrs:
   case AArch64::ORRWrs:
   case AArch64::ORRXrs:

llvm/trunk/test/CodeGen/AArch64/arm64-crc32.ll

 ; RUN: llc -mtriple=arm64-eabi -mattr=+crc -o - %s | FileCheck %s
+; RUN: llc -mtriple=arm64-eabi -mcpu=cortex-a53 -mattr=+crc -o - %s | FileCheck %s
 
 define i32 @test_crc32b(i32 %cur, i8 %next) {
 ; CHECK-LABEL: test_crc32b:
 ; CHECK: crc32b w0, w0, w1
   %bits = zext i8 %next to i32
   %val = call i32 @llvm.aarch64.crc32b(i32 %cur, i32 %bits)
   ret i32 %val
 }