AMDGPU/SI: Fix SI scheduler LiveOut Refcount issue

[axeldavy]

Summary

The LiveOuts of a scheduling region were not properly refcounted,
thus the scheduler was incorrectly expecting them to be released
when the last block of the region using them as scheduled.

[arsenm]

lib/Target/AMDGPU/SIMachineScheduler.cpp

1372 ↗

(On Diff #89038)

const reference

1374–1381 ↗

(On Diff #89038)

Double map lookup, use the iterator returned by find

[axeldavy]

I added the suggested changes.
Also, it seems that incrementing non-existing map element will create it with value 0 (and then increment it), thus I don't need to check at all the existence:
++LiveOutRegsNumUsages[ID][Reg];
is enough.

I will propose a patch that will update the other cases in the code that would benefit this.

[vpykhtin]

lib/Target/AMDGPU/SIMachineScheduler.cpp

1372 ↗

(On Diff #89800)

constructing std::set every time you need to find one register in it is an obvious overkill. In this case its better to swap these two loops, construct the OutRegs set once for a block and then search all out regs there.

[axeldavy]

lib/Target/AMDGPU/SIMachineScheduler.cpp

1372 ↗

(On Diff #89800)

Sorry, I didn't know for (-U9999999) when I sent this patch, I'll update with it.

Probably the good way is const std::set<unsigned> &OutRegs = Block->getOutRegs();

For blocks, the result of getOutRegs is computed once.

This is different to DAG->getOutRegs, which is added in this patch.

[axeldavy]

Prevented a set copy using a reference.

[vpykhtin]

LGTM, Thanks!

llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.h

public:
   std::set<unsigned> getInRegs() {
     std::set<unsigned> InRegs;
     for (const auto &RegMaskPair : RPTracker.getPressure().LiveInRegs) {
       InRegs.insert(RegMaskPair.RegUnit);
     }
     return InRegs;
   }
 
+  std::set<unsigned> getOutRegs() {
+    std::set<unsigned> OutRegs;
+    for (const auto &RegMaskPair : RPTracker.getPressure().LiveOutRegs) {
+      OutRegs.insert(RegMaskPair.RegUnit);
+    }
+    return OutRegs;
+  };
+
   unsigned getVGPRSetID() const { return VGPRSetID; }
   unsigned getSGPRSetID() const { return SGPRSetID; }
 
 private:
   void topologicalSort();
   // After scheduling is done, improve low latency placements.
   void moveLowLatencies();
 

llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.cpp

for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
     SIScheduleBlock *Block = Blocks[i];
     assert(Block->getID() == i);
   }
 #endif
 
   std::set<unsigned> InRegs = DAG->getInRegs();
   addLiveRegs(InRegs);
 
+  // Increase LiveOutRegsNumUsages for blocks
+  // producing registers consumed in another
+  // scheduling region.
+  for (unsigned Reg : DAG->getOutRegs()) {
+    for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
+      // Do reverse traversal
+      int ID = BlocksStruct.TopDownIndex2Block[Blocks.size()-1-i];
+      SIScheduleBlock *Block = Blocks[ID];
+      const std::set<unsigned> &OutRegs = Block->getOutRegs();
+
+      if (OutRegs.find(Reg) == OutRegs.end())
+        continue;
+
+      ++LiveOutRegsNumUsages[ID][Reg];
+      break;
+    }
+  }
+
   // Fill LiveRegsConsumers for regs that were already
   // defined before scheduling.
   for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
     SIScheduleBlock *Block = Blocks[i];
     for (unsigned Reg : Block->getInRegs()) {
       bool Found = false;
       for (SIScheduleBlock* Pred: Block->getPreds()) {
         std::set<unsigned> PredOutRegs = Pred->getOutRegs();