I think this is a fair approximation of the minimum necessary for some sort of testable codegen - though if people have any ideas on splitting things up further I'm all ears. Frame handling, and proper function prologue/epilogue handling is left for a later patch.
For the time being, this primarily targets RV32. Last I heard, @kparzysz is still hoping to get time to finish some prototype patches for his RFC on variable-sized register classes. In the ideal case, the RISCV backend will build upon these patches and act as a demonstrator to prove the approach. However, if it looks like that isn't going to happen any time soon then I'll bite the bullet and add in all the necessary 64-bit code paths and duplicated instruction definitions.