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[RISCV] Initial codegen support for ALU operations

Description

[RISCV] Initial codegen support for ALU operations

This adds the minimum necessary to support codegen for simple ALU operations
on RV32. Prolog and epilog insertion, support for memory operations etc etc
follow in future patches.

Leave guessInstructionProperties=1 until https://reviews.llvm.org/D37065 is
reviewed and lands.

Differential Revision: https://reviews.llvm.org/D29933

Event Timeline

shiva0217 added inline comments.
/llvm/trunk/lib/Target/RISCV/RISCV.td
43

Is there any reason we should define guessInstructionProperties = 0? With the definition, we have to define some instruction properties explicitly. Is there any case auto guess will produce the properties we are not expected?

asb added inline comments.Oct 23 2017, 11:47 PM
/llvm/trunk/lib/Target/RISCV/RISCV.td
43

Because the RISC-V backend specifies patterns separately to the instructions, the inference will not infer properties. It will default to mayLoad=0, mayStore=0, and assume that hasSideEffects=1.

Note I hadn't intended to flip the switch on guessInstructionProperties=0 yet. I've put it back to 1 until D37065 lands.

shiva0217 added inline comments.Oct 24 2017, 11:37 PM
/llvm/trunk/lib/Target/RISCV/RISCV.td
43

So after D37065 landing, we don't have to initial mayLoad/mayStore/hasSideEffest for each instruction pattern.
In that time we switch on guessInstructionProperties=0 which should act as no-op.
The intention for "guessInstructionProperties=0" is to declare that we separate Dag patterns from instruction patterns and we won't need interference. Is that right?