[AMDGPU] Implement register pressure callbacks

[rampitec]

Summary

Implement getRegPressureLimit and getRegPressureSetLimit callbacks in
SIRegisterInfo.

This makes standard converge scheduler to behave almost the same as
GCNScheduler, sometime slightly better sometimes a bit worse.
In gerenal that is also possible to switch GCNScheduler to use these
callbacks instead of getMaxWaves(), which also makes GCNScheduler
slightly better on some tests and slightly worse on another. A big
win is behavior with converge scheduler.

Note, these are used not only by scheduling, but in places like
MachineLICM.

[arsenm]

Typo in commit message "startdard"W

lib/Target/AMDGPU/SIRegisterInfo.cpp

1509–1510 ↗

(On Diff #87584)

Why doesn't this need to handle the tuples of registers?

1513 ↗

(On Diff #87584)

SGPR register classes are also more complex because of the variants that exclude m0 and add vcc etc. Why don't those need to be handled?

lib/Target/AMDGPU/SIRegisterInfo.h

275 ↗

(On Diff #87584)

const should be added here instead of using const_cast from the other overload?

[rampitec]

In D29700#670344, @arsenm wrote:

Typo in commit message "startdard"W

Thanks ;)

[rampitec]

lib/Target/AMDGPU/SIRegisterInfo.cpp

1509–1510 ↗

(On Diff #87584)

Since we are tracking subregs all supreregs are counted as their parts. I.e. only 32 bit registers are relevant. If you check GCNScheduler it does the same. In fact that is correct, as you want to count them in the same bucket.

1513 ↗

(On Diff #87584)

Again, what is matter are real 32 bit SGPRs. Everything else either counted through subregs, or returns RC size in a default case. What we need is to limit SGPR and VGPR more than their RC size to handle occupancy.

[rampitec]

lib/Target/AMDGPU/SIRegisterInfo.h

275 ↗

(On Diff #87584)

There is no prototype with const MF. Too bad.

[rampitec]

lib/Target/AMDGPU/SIRegisterInfo.h

275 ↗

(On Diff #87584)

Note, even if I implement my own function taking const MF and call it from non-const overload, the const_cast will just move into that function to call parent's getRegPressureLimit().

[arsenm]

LGTM

lib/Target/AMDGPU/SIRegisterInfo.h

275 ↗

(On Diff #87584)

I think the parent class should be fixed

llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.h

public:
 
   bool shouldCoalesce(MachineInstr *MI,
                       const TargetRegisterClass *SrcRC,
                       unsigned SubReg,
                       const TargetRegisterClass *DstRC,
                       unsigned DstSubReg,
                       const TargetRegisterClass *NewRC) const override;
 
+  unsigned getRegPressureLimit(const TargetRegisterClass *RC,
+                               MachineFunction &MF) const override;
+
+  unsigned getRegPressureSetLimit(const MachineFunction &MF,
+                                  unsigned Idx) const override;
+
 private:
   void buildSpillLoadStore(MachineBasicBlock::iterator MI,
                            unsigned LoadStoreOp,
                            int Index,
                            unsigned ValueReg,
                            bool ValueIsKill,
                            unsigned ScratchRsrcReg,
                            unsigned ScratchOffsetReg,
                            int64_t InstrOffset,
                            MachineMemOperand *MMO,
                            RegScavenger *RS) const;
 };
 
 } // End namespace llvm
 
 #endif

llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp

bool SIRegisterInfo::shouldCoalesce(MachineInstr *MI,
   // adjacent registers and constraint regalloc more than needed.
 
   // Always allow dword coalescing.
   if (SrcSize <= 4 || DstSize <= 4)
     return true;
 
   return NewSize <= DstSize || NewSize <= SrcSize;
 }
+
+unsigned SIRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
+                                             MachineFunction &MF) const {
+
+  const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
+  const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
+
+  unsigned Occupancy = ST.getOccupancyWithLocalMemSize(MFI->getLDSSize(),
+                                                       *MF.getFunction());
+  switch (RC->getID()) {
+  default:
+    return AMDGPURegisterInfo::getRegPressureLimit(RC, MF);
+  case AMDGPU::VGPR_32RegClassID:
+    return std::min(ST.getMaxNumVGPRs(Occupancy), ST.getMaxNumVGPRs(MF));
+  case AMDGPU::SGPR_32RegClassID:
+    return std::min(ST.getMaxNumSGPRs(Occupancy, true), ST.getMaxNumSGPRs(MF));
+  }
+}
+
+unsigned SIRegisterInfo::getRegPressureSetLimit(const MachineFunction &MF,
+                                                unsigned Idx) const {
+  if (Idx == getVGPRPressureSet())
+    return getRegPressureLimit(&AMDGPU::VGPR_32RegClass,
+                               const_cast<MachineFunction &>(MF));
+
+  if (Idx == getSGPRPressureSet())
+    return getRegPressureLimit(&AMDGPU::SGPR_32RegClass,
+                               const_cast<MachineFunction &>(MF));
+
+  return AMDGPURegisterInfo::getRegPressureSetLimit(MF, Idx);
+}