[AMDGPU] Add exec copy to LiveIntervals in SILowerControlFlow::emitElse

[rampitec]

Summary

This instruction is missing from LiveIntervals.
I'm not aware of any problems because of this though.

[arsenm]

I would expect this to fail the verifier. Do you have a test where this failed it?

[arsenm]

LGTM but a test would be nice

[rampitec]

In D28879#650594, @arsenm wrote:

I would expect this to fail the verifier. Do you have a test where this failed it?

No, I have not seen any failures. As I said I'm not aware of any problems because of this.

[arsenm]

In D28879#650748, @rampitec wrote:

In D28879#650594, @arsenm wrote:

I would expect this to fail the verifier. Do you have a test where this failed it?

No, I have not seen any failures. As I said I'm not aware of any problems because of this.

Oh, I forgot I moved this to the point in the pipeline where the verifier is disabled

llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp

void SILowerControlFlow::emitElse(MachineInstr &MI) {
 
   bool ExecModified = MI.getOperand(3).getImm() != 0;
   MachineBasicBlock::iterator Start = MBB.begin();
 
   // We are running before TwoAddressInstructions, and si_else's operands are
   // tied. In order to correctly tie the registers, split this into a copy of
   // the src like it does.
   unsigned CopyReg = MRI->createVirtualRegister(&AMDGPU::SReg_64RegClass);
+  MachineInstr *CopyExec =
     BuildMI(MBB, Start, DL, TII->get(AMDGPU::COPY), CopyReg)
       .add(MI.getOperand(1)); // Saved EXEC
 
   // This must be inserted before phis and any spill code inserted before the
   // else.
   unsigned SaveReg = ExecModified ?
     MRI->createVirtualRegister(&AMDGPU::SReg_64RegClass) : DstReg;
   MachineInstr *OrSaveExec =
     BuildMI(MBB, Start, DL, TII->get(AMDGPU::S_OR_SAVEEXEC_B64), SaveReg)
void SILowerControlFlow::emitElse(MachineInstr &MI) {
   if (!LIS) {
     MI.eraseFromParent();
     return;
   }
 
   LIS->RemoveMachineInstrFromMaps(MI);
   MI.eraseFromParent();
 
+  LIS->InsertMachineInstrInMaps(*CopyExec);
   LIS->InsertMachineInstrInMaps(*OrSaveExec);
 
   LIS->InsertMachineInstrInMaps(*Xor);
   LIS->InsertMachineInstrInMaps(*Branch);
 
   // src reg is tied to dst reg.
   LIS->removeInterval(DstReg);
   LIS->createAndComputeVirtRegInterval(DstReg);