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Differential D28551

[X86] Modify BypassSlowDivision tests to match their new names (NFC)
ClosedPublic

Authored by n.bozhenov on Jan 11 2017, 2:35 AM.

Details

Reviewers
spatel
RKSimon
jlebar
craig.topper
bkramer
Commits
rG3db8bcdbbabc: [X86] Modify BypassSlowDivision tests to match their new names (NFC)
rL291804: [X86] Modify BypassSlowDivision tests to match their new names (NFC)
Summary

[X86] Modify BypassSlowDivision tests to match their new names (NFC)

  • bypass-slow-division-32.ll: tests verifying correctness of divl-to-divb bypassing
  • bypass-slow-division-64.ll: tests verifying correctness of divq-to-divl bypassing
  • bypass-slow-division-tune.ll: tests verifying that bypassing is enabled only when appropriate

Diff Detail

Repository
rL LLVM

Event Timeline

n.bozhenov updated this revision to Diff 83935.Jan 11 2017, 2:35 AM
n.bozhenov retitled this revision from to [X86] Modify BypassSlowDivision tests to match their new names (NFC).
n.bozhenov updated this object.
n.bozhenov added reviewers: spatel, craig.topper, bkramer, jlebar, RKSimon.
n.bozhenov added subscribers: llvm-commits, zansari, DavidKreitzer, aaboud.
n.bozhenov mentioned this in D28197: [X86] Re-organize tests for bypassing slow division (NFC).Jan 11 2017, 2:38 AM
n.bozhenov mentioned this in D28196: [X86] Tune bypassing of slow division for Intel CPUs.Jan 11 2017, 2:43 AM
n.bozhenov added a parent revision: D28197: [X86] Re-organize tests for bypassing slow division (NFC).Jan 11 2017, 3:03 AM
n.bozhenov added a child revision: D28198: [X86] Replace AND+IMM64 with SRL/SHL.
RKSimon accepted this revision.Jan 11 2017, 7:23 AM
RKSimon edited edge metadata.

LGTM

This revision is now accepted and ready to land.Jan 11 2017, 7:23 AM
Closed by commit rL291804: [X86] Modify BypassSlowDivision tests to match their new names (NFC) (authored by n.bozhenov). · Explain WhyJan 12 2017, 11:59 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
test/
CodeGen/
X86/
23 lines
74 lines
52 lines

Diff 84160

llvm/trunk/test/CodeGen/X86/bypass-slow-division-32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mcpu=atom -mtriple=i686-linux | FileCheck %s ; Check that 32-bit division is bypassed correctly.
; RUN: llc < %s -mattr=+idivl-to-divb -mtriple=i686-linux | FileCheck %s
define i32 @Test_get_quotient(i32 %a, i32 %b) nounwind { define i32 @Test_get_quotient(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: Test_get_quotient: ; CHECK-LABEL: Test_get_quotient:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl %eax, %edx ; CHECK-NEXT: movl %eax, %edx
; CHECK-NEXT: orl %ecx, %edx ; CHECK-NEXT: orl %ecx, %edx
; CHECK-NEXT: testl $-256, %edx ; CHECK-NEXT: testl $-256, %edx
; CHECK-NEXT: je .LBB0_1 ; CHECK-NEXT: je .LBB0_1
; CHECK-NEXT: # BB#2: ; CHECK-NEXT: # BB#2:
; CHECK-NEXT: cltd ; CHECK-NEXT: cltd
; CHECK-NEXT: idivl %ecx ; CHECK-NEXT: idivl %ecx
; CHECK-NEXT: retl ; CHECK-NEXT: retl
; CHECK-NEXT: .LBB0_1: ; CHECK-NEXT: .LBB0_1:
; CHECK-NEXT: movzbl %al, %eax ; CHECK-NEXT: movzbl %al, %eax
; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def> ; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
; CHECK-NEXT: divb %cl ; CHECK-NEXT: divb %cl
; CHECK-NEXT: movzbl %al, %eax ; CHECK-NEXT: movzbl %al, %eax
; CHECK-NEXT: retl ; CHECK-NEXT: retl
%result = sdiv i32 %a, %b %result = sdiv i32 %a, %b
ret i32 %result ret i32 %result
} }
define i32 @Test_get_remainder(i32 %a, i32 %b) nounwind { define i32 @Test_get_remainder(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: Test_get_remainder: ; CHECK-LABEL: Test_get_remainder:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl %eax, %edx ; CHECK-NEXT: movl %eax, %edx
; CHECK-NEXT: orl %ecx, %edx ; CHECK-NEXT: orl %ecx, %edx
; CHECK-NEXT: testl $-256, %edx ; CHECK-NEXT: testl $-256, %edx
; CHECK-NEXT: je .LBB1_1 ; CHECK-NEXT: je .LBB1_1
; CHECK-NEXT: # BB#2: ; CHECK-NEXT: # BB#2:
; CHECK-NEXT: cltd ; CHECK-NEXT: cltd
; CHECK-NEXT: idivl %ecx ; CHECK-NEXT: idivl %ecx
; CHECK-NEXT: movl %edx, %eax ; CHECK-NEXT: movl %edx, %eax
; CHECK-NEXT: retl ; CHECK-NEXT: retl
; CHECK-NEXT: .LBB1_1: ; CHECK-NEXT: .LBB1_1:
; CHECK-NEXT: movzbl %al, %eax ; CHECK-NEXT: movzbl %al, %eax
; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def> ; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
; CHECK-NEXT: divb %cl ; CHECK-NEXT: divb %cl
; CHECK-NEXT: movzbl %ah, %eax # NOREX ; CHECK-NEXT: movzbl %ah, %eax # NOREX
; CHECK-NEXT: retl ; CHECK-NEXT: retl
%result = srem i32 %a, %b %result = srem i32 %a, %b
ret i32 %result ret i32 %result
} }
define i32 @Test_get_quotient_and_remainder(i32 %a, i32 %b) nounwind { define i32 @Test_get_quotient_and_remainder(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: Test_get_quotient_and_remainder: ; CHECK-LABEL: Test_get_quotient_and_remainder:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl %eax, %edx ; CHECK-NEXT: movl %eax, %edx
; CHECK-NEXT: orl %ecx, %edx ; CHECK-NEXT: orl %ecx, %edx
; CHECK-NEXT: testl $-256, %edx ; CHECK-NEXT: testl $-256, %edx
; CHECK-NEXT: je .LBB2_1 ; CHECK-NEXT: je .LBB2_1
; CHECK-NEXT: # BB#2: ; CHECK-NEXT: # BB#2:
; CHECK-NEXT: cltd ; CHECK-NEXT: cltd
; CHECK-NEXT: idivl %ecx ; CHECK-NEXT: idivl %ecx
; CHECK-NEXT: addl %edx, %eax ; CHECK-NEXT: addl %edx, %eax
Show All 13 Lines
} }
define i32 @Test_use_div_and_idiv(i32 %a, i32 %b) nounwind { define i32 @Test_use_div_and_idiv(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: Test_use_div_and_idiv: ; CHECK-LABEL: Test_use_div_and_idiv:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: pushl %ebx ; CHECK-NEXT: pushl %ebx
; CHECK-NEXT: pushl %edi ; CHECK-NEXT: pushl %edi
; CHECK-NEXT: pushl %esi ; CHECK-NEXT: pushl %esi
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ebx ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ebx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl %ecx, %edi ; CHECK-NEXT: movl %ecx, %edi
; CHECK-NEXT: orl %ebx, %edi ; CHECK-NEXT: orl %ebx, %edi
; CHECK-NEXT: testl $-256, %edi ; CHECK-NEXT: testl $-256, %edi
; CHECK-NEXT: je .LBB3_1 ; CHECK-NEXT: je .LBB3_1
; CHECK-NEXT: # BB#2: ; CHECK-NEXT: # BB#2:
; CHECK-NEXT: movl %ecx, %eax ; CHECK-NEXT: movl %ecx, %eax
; CHECK-NEXT: cltd ; CHECK-NEXT: cltd
; CHECK-NEXT: idivl %ebx ; CHECK-NEXT: idivl %ebx
Show All 30 Lines; CHECK-NEXT: retl
%result = add i32 %resultidiv, %resultdiv %result = add i32 %resultidiv, %resultdiv
ret i32 %result ret i32 %result
} }
define i32 @Test_use_div_imm_imm() nounwind { define i32 @Test_use_div_imm_imm() nounwind {
; CHECK-LABEL: Test_use_div_imm_imm: ; CHECK-LABEL: Test_use_div_imm_imm:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: movl $64, %eax ; CHECK-NEXT: movl $64, %eax
; CHECK-NEXT: nop
; CHECK-NEXT: nop
; CHECK-NEXT: nop
; CHECK-NEXT: nop
; CHECK-NEXT: nop
; CHECK-NEXT: nop
; CHECK-NEXT: retl ; CHECK-NEXT: retl
%resultdiv = sdiv i32 256, 4 %resultdiv = sdiv i32 256, 4
ret i32 %resultdiv ret i32 %resultdiv
} }
define i32 @Test_use_div_reg_imm(i32 %a) nounwind { define i32 @Test_use_div_reg_imm(i32 %a) nounwind {
; CHECK-LABEL: Test_use_div_reg_imm: ; CHECK-LABEL: Test_use_div_reg_imm:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: movl $1041204193, %eax # imm = 0x3E0F83E1 ; CHECK-NEXT: movl $1041204193, %eax # imm = 0x3E0F83E1
; CHECK-NEXT: imull {{[0-9]+}}(%esp) ; CHECK-NEXT: imull {{[0-9]+}}(%esp)
; CHECK-NEXT: movl %edx, %eax ; CHECK-NEXT: movl %edx, %eax
; CHECK-NEXT: sarl $3, %edx
; CHECK-NEXT: shrl $31, %eax ; CHECK-NEXT: shrl $31, %eax
; CHECK-NEXT: sarl $3, %edx
; CHECK-NEXT: leal (%edx,%eax), %eax ; CHECK-NEXT: leal (%edx,%eax), %eax
; CHECK-NEXT: retl ; CHECK-NEXT: retl
%resultdiv = sdiv i32 %a, 33 %resultdiv = sdiv i32 %a, 33
ret i32 %resultdiv ret i32 %resultdiv
} }
define i32 @Test_use_rem_reg_imm(i32 %a) nounwind { define i32 @Test_use_rem_reg_imm(i32 %a) nounwind {
; CHECK-LABEL: Test_use_rem_reg_imm: ; CHECK-LABEL: Test_use_rem_reg_imm:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl $1041204193, %edx # imm = 0x3E0F83E1 ; CHECK-NEXT: movl $1041204193, %edx # imm = 0x3E0F83E1
; CHECK-NEXT: movl %ecx, %eax ; CHECK-NEXT: movl %ecx, %eax
; CHECK-NEXT: imull %edx ; CHECK-NEXT: imull %edx
; CHECK-NEXT: movl %edx, %eax ; CHECK-NEXT: movl %edx, %eax
; CHECK-NEXT: sarl $3, %edx
; CHECK-NEXT: shrl $31, %eax ; CHECK-NEXT: shrl $31, %eax
; CHECK-NEXT: sarl $3, %edx
; CHECK-NEXT: addl %eax, %edx ; CHECK-NEXT: addl %eax, %edx
; CHECK-NEXT: movl %edx, %eax ; CHECK-NEXT: movl %edx, %eax
; CHECK-NEXT: shll $5, %eax ; CHECK-NEXT: shll $5, %eax
; CHECK-NEXT: addl %edx, %eax ; CHECK-NEXT: addl %edx, %eax
; CHECK-NEXT: subl %eax, %ecx ; CHECK-NEXT: subl %eax, %ecx
; CHECK-NEXT: movl %ecx, %eax ; CHECK-NEXT: movl %ecx, %eax
; CHECK-NEXT: retl ; CHECK-NEXT: retl
%resultrem = srem i32 %a, 33 %resultrem = srem i32 %a, 33
ret i32 %resultrem ret i32 %resultrem
} }
define i32 @Test_use_divrem_reg_imm(i32 %a) nounwind { define i32 @Test_use_divrem_reg_imm(i32 %a) nounwind {
; CHECK-LABEL: Test_use_divrem_reg_imm: ; CHECK-LABEL: Test_use_divrem_reg_imm:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl $1041204193, %edx # imm = 0x3E0F83E1 ; CHECK-NEXT: movl $1041204193, %edx # imm = 0x3E0F83E1
; CHECK-NEXT: movl %ecx, %eax ; CHECK-NEXT: movl %ecx, %eax
; CHECK-NEXT: imull %edx ; CHECK-NEXT: imull %edx
; CHECK-NEXT: movl %edx, %eax ; CHECK-NEXT: movl %edx, %eax
; CHECK-NEXT: sarl $3, %edx
; CHECK-NEXT: shrl $31, %eax ; CHECK-NEXT: shrl $31, %eax
; CHECK-NEXT: sarl $3, %edx
; CHECK-NEXT: addl %eax, %edx ; CHECK-NEXT: addl %eax, %edx
; CHECK-NEXT: movl %edx, %eax ; CHECK-NEXT: movl %edx, %eax
; CHECK-NEXT: shll $5, %eax ; CHECK-NEXT: shll $5, %eax
; CHECK-NEXT: addl %edx, %eax ; CHECK-NEXT: addl %edx, %eax
; CHECK-NEXT: subl %eax, %ecx ; CHECK-NEXT: subl %eax, %ecx
; CHECK-NEXT: addl %edx, %ecx ; CHECK-NEXT: addl %edx, %ecx
; CHECK-NEXT: movl %ecx, %eax ; CHECK-NEXT: movl %ecx, %eax
; CHECK-NEXT: retl ; CHECK-NEXT: retl
▲ Show 20 Lines • Show All 49 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/bypass-slow-division-64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mcpu=atom -mtriple=x86_64-unknown-linux-gnu | FileCheck %s ; Check that 64-bit division is bypassed correctly.
; RUN: llc < %s -mcpu=sandybridge -mtriple=x86_64-unknown-linux-gnu | FileCheck %s -check-prefix=SNB ; RUN: llc < %s -mattr=+idivq-to-divl -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
; Additional tests for 64-bit divide bypass ; Additional tests for 64-bit divide bypass
define i64 @Test_get_quotient(i64 %a, i64 %b) nounwind { define i64 @Test_get_quotient(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: Test_get_quotient: ; CHECK-LABEL: Test_get_quotient:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: movq %rdi, %rax ; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: movabsq $-4294967296, %rcx # imm = 0xFFFFFFFF00000000
; CHECK-NEXT: orq %rsi, %rax ; CHECK-NEXT: orq %rsi, %rax
; CHECK-NEXT: movabsq $-4294967296, %rcx # imm = 0xFFFFFFFF00000000
; CHECK-NEXT: testq %rcx, %rax ; CHECK-NEXT: testq %rcx, %rax
; CHECK-NEXT: je .LBB0_1 ; CHECK-NEXT: je .LBB0_1
; CHECK-NEXT: # BB#2: ; CHECK-NEXT: # BB#2:
; CHECK-NEXT: movq %rdi, %rax ; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: cqto ; CHECK-NEXT: cqto
; CHECK-NEXT: idivq %rsi ; CHECK-NEXT: idivq %rsi
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; CHECK-NEXT: .LBB0_1: ; CHECK-NEXT: .LBB0_1:
; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: divl %esi ; CHECK-NEXT: divl %esi
; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<def> ; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<def>
; CHECK-NEXT: retq ; CHECK-NEXT: retq
;
; SNB-LABEL: Test_get_quotient:
; SNB: # BB#0:
; SNB-NEXT: movq %rdi, %rax
; SNB-NEXT: orq %rsi, %rax
; SNB-NEXT: movabsq $-4294967296, %rcx # imm = 0xFFFFFFFF00000000
; SNB-NEXT: testq %rcx, %rax
; SNB-NEXT: je .LBB0_1
; SNB-NEXT: # BB#2:
; SNB-NEXT: movq %rdi, %rax
; SNB-NEXT: cqto
; SNB-NEXT: idivq %rsi
; SNB-NEXT: retq
; SNB-NEXT: .LBB0_1:
; SNB-NEXT: xorl %edx, %edx
; SNB-NEXT: movl %edi, %eax
; SNB-NEXT: divl %esi
; SNB-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<def>
; SNB-NEXT: retq
%result = sdiv i64 %a, %b %result = sdiv i64 %a, %b
ret i64 %result ret i64 %result
} }
define i64 @Test_get_remainder(i64 %a, i64 %b) nounwind { define i64 @Test_get_remainder(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: Test_get_remainder: ; CHECK-LABEL: Test_get_remainder:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: movq %rdi, %rax ; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: movabsq $-4294967296, %rcx # imm = 0xFFFFFFFF00000000
; CHECK-NEXT: orq %rsi, %rax ; CHECK-NEXT: orq %rsi, %rax
; CHECK-NEXT: movabsq $-4294967296, %rcx # imm = 0xFFFFFFFF00000000
; CHECK-NEXT: testq %rcx, %rax ; CHECK-NEXT: testq %rcx, %rax
; CHECK-NEXT: je .LBB1_1 ; CHECK-NEXT: je .LBB1_1
; CHECK-NEXT: # BB#2: ; CHECK-NEXT: # BB#2:
; CHECK-NEXT: movq %rdi, %rax ; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: cqto ; CHECK-NEXT: cqto
; CHECK-NEXT: idivq %rsi ; CHECK-NEXT: idivq %rsi
; CHECK-NEXT: movq %rdx, %rax ; CHECK-NEXT: movq %rdx, %rax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; CHECK-NEXT: .LBB1_1: ; CHECK-NEXT: .LBB1_1:
; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: divl %esi ; CHECK-NEXT: divl %esi
; CHECK-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def> ; CHECK-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def>
; CHECK-NEXT: movq %rdx, %rax ; CHECK-NEXT: movq %rdx, %rax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
;
; SNB-LABEL: Test_get_remainder:
; SNB: # BB#0:
; SNB-NEXT: movq %rdi, %rax
; SNB-NEXT: orq %rsi, %rax
; SNB-NEXT: movabsq $-4294967296, %rcx # imm = 0xFFFFFFFF00000000
; SNB-NEXT: testq %rcx, %rax
; SNB-NEXT: je .LBB1_1
; SNB-NEXT: # BB#2:
; SNB-NEXT: movq %rdi, %rax
; SNB-NEXT: cqto
; SNB-NEXT: idivq %rsi
; SNB-NEXT: movq %rdx, %rax
; SNB-NEXT: retq
; SNB-NEXT: .LBB1_1:
; SNB-NEXT: xorl %edx, %edx
; SNB-NEXT: movl %edi, %eax
; SNB-NEXT: divl %esi
; SNB-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def>
; SNB-NEXT: movq %rdx, %rax
; SNB-NEXT: retq
%result = srem i64 %a, %b %result = srem i64 %a, %b
ret i64 %result ret i64 %result
} }
define i64 @Test_get_quotient_and_remainder(i64 %a, i64 %b) nounwind { define i64 @Test_get_quotient_and_remainder(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: Test_get_quotient_and_remainder: ; CHECK-LABEL: Test_get_quotient_and_remainder:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: movq %rdi, %rax ; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: movabsq $-4294967296, %rcx # imm = 0xFFFFFFFF00000000
; CHECK-NEXT: orq %rsi, %rax ; CHECK-NEXT: orq %rsi, %rax
; CHECK-NEXT: movabsq $-4294967296, %rcx # imm = 0xFFFFFFFF00000000
; CHECK-NEXT: testq %rcx, %rax ; CHECK-NEXT: testq %rcx, %rax
; CHECK-NEXT: je .LBB2_1 ; CHECK-NEXT: je .LBB2_1
; CHECK-NEXT: # BB#2: ; CHECK-NEXT: # BB#2:
; CHECK-NEXT: movq %rdi, %rax ; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: cqto ; CHECK-NEXT: cqto
; CHECK-NEXT: idivq %rsi ; CHECK-NEXT: idivq %rsi
; CHECK-NEXT: addq %rdx, %rax ; CHECK-NEXT: addq %rdx, %rax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; CHECK-NEXT: .LBB2_1: ; CHECK-NEXT: .LBB2_1:
; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: divl %esi ; CHECK-NEXT: divl %esi
; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<def>
; CHECK-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def> ; CHECK-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def>
; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<def>
; CHECK-NEXT: addq %rdx, %rax ; CHECK-NEXT: addq %rdx, %rax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
;
; SNB-LABEL: Test_get_quotient_and_remainder:
; SNB: # BB#0:
; SNB-NEXT: movq %rdi, %rax
; SNB-NEXT: orq %rsi, %rax
; SNB-NEXT: movabsq $-4294967296, %rcx # imm = 0xFFFFFFFF00000000
; SNB-NEXT: testq %rcx, %rax
; SNB-NEXT: je .LBB2_1
; SNB-NEXT: # BB#2:
; SNB-NEXT: movq %rdi, %rax
; SNB-NEXT: cqto
; SNB-NEXT: idivq %rsi
; SNB-NEXT: addq %rdx, %rax
; SNB-NEXT: retq
; SNB-NEXT: .LBB2_1:
; SNB-NEXT: xorl %edx, %edx
; SNB-NEXT: movl %edi, %eax
; SNB-NEXT: divl %esi
; SNB-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def>
; SNB-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<def>
; SNB-NEXT: addq %rdx, %rax
; SNB-NEXT: retq
%resultdiv = sdiv i64 %a, %b %resultdiv = sdiv i64 %a, %b
%resultrem = srem i64 %a, %b %resultrem = srem i64 %a, %b
%result = add i64 %resultdiv, %resultrem %result = add i64 %resultdiv, %resultrem
ret i64 %result ret i64 %result
} }

llvm/trunk/test/CodeGen/X86/bypass-slow-division-tune.ll

; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+idivl-to-divb < %s | FileCheck -check-prefix=DIV32 %s ; Check that a division is bypassed when appropriate only.
; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+idivq-to-divl < %s | FileCheck -check-prefix=DIV64 %s ; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=atom < %s | FileCheck -check-prefixes=ATOM,CHECK %s
; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=silvermont < %s | FileCheck -check-prefixes=REST,CHECK %s
; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=skylake < %s | FileCheck -check-prefixes=REST,CHECK %s
; Verify that div32 is bypassed only for Atoms.
define i32 @div32(i32 %a, i32 %b) { define i32 @div32(i32 %a, i32 %b) {
entry: entry:
; DIV32-LABEL: div32: ; ATOM-LABEL: div32:
; DIV32: orl %{{.*}}, [[REG:%[a-z]+]] ; ATOM: orl %{{.*}}, [[REG:%[a-z]+]]
; DIV32: testl $-256, [[REG]] ; ATOM: testl $-256, [[REG]]
; DIV32: divb ; ATOM: divb
; DIV64-LABEL: div32: ;
; DIV64-NOT: divb ; REST-LABEL: div32:
; REST-NOT: divb
;
%div = sdiv i32 %a, %b %div = sdiv i32 %a, %b
ret i32 %div ret i32 %div
} }
; Verify that div64 is always bypassed.
define i64 @div64(i64 %a, i64 %b) { define i64 @div64(i64 %a, i64 %b) {
entry: entry:
; DIV32-LABEL: div64: ; CHECK-LABEL: div64:
; DIV32-NOT: divl ; CHECK-DAG: movabsq $-4294967296, [[REGMSK:%[a-z]+]]
; DIV64-LABEL: div64: ; CHECK-DAG: orq %{{.*}}, [[REG:%[a-z]+]]
; DIV64-DAG: movabsq $-4294967296, [[REGMSK:%[a-z]+]] ; CHECK: testq [[REGMSK]], [[REG]]
; DIV64-DAG: orq %{{.*}}, [[REG:%[a-z]+]] ; CHECK: divl
; DIV64: testq [[REGMSK]], [[REG]] ;
; DIV64: divl
%div = sdiv i64 %a, %b %div = sdiv i64 %a, %b
ret i64 %div ret i64 %div
} }
; Verify that no extra code is generated when optimizing for size. ; Verify that no extra code is generated when optimizing for size.
define i64 @div64_optsize(i64 %a, i64 %b) optsize {
; CHECK-LABEL: div64_optsize:
; CHECK-NOT: divl
%div = sdiv i64 %a, %b
ret i64 %div
}
define i32 @div32_optsize(i32 %a, i32 %b) optsize { define i32 @div32_optsize(i32 %a, i32 %b) optsize {
; DIV32-LABEL: div32_optsize: ; CHECK-LABEL: div32_optsize:
; DIV32-NOT: divb ; CHECK-NOT: divb
%div = sdiv i32 %a, %b %div = sdiv i32 %a, %b
ret i32 %div ret i32 %div
} }
define i32 @div32_minsize(i32 %a, i32 %b) minsize { define i32 @div32_minsize(i32 %a, i32 %b) minsize {
; DIV32-LABEL: div32_minsize: ; CHECK-LABEL: div32_minsize:
; DIV32-NOT: divb ; CHECK-NOT: divb
%div = sdiv i32 %a, %b %div = sdiv i32 %a, %b
ret i32 %div ret i32 %div
} }