[AArch64] Use generic bitreverse intrinsic, rather than AArch64 specific.

[mcrosier]

Summary

Per the title, this patch replaces the target-specific intrinsic with a target-independent equivalent.

This requires the LLVM side change here: https://reviews.llvm.org/D28379.

In D28379, making the bitreverse intrinsic legal for AArch64 and lowering to a rbit instruction accordingly.

Chad

[RKSimon]

test/CodeGen/arm_acle.c

247 ↗

(On Diff #83367)

Since you're here is it worth dealing with the AARCH32 case as well? We know it works on the llvm side.

[mcrosier]

test/CodeGen/arm_acle.c

247 ↗

(On Diff #83367)

I was thinking I would commit a separate patch once this one and D28379 were approved.

[sbaranga]

This looks straight-forward to me. LGTM.

-Silviu

cfe/trunk/lib/CodeGen/CGBuiltin.cpp

if (BuiltinID == AArch64::BI__builtin_arm_prefetch) {
     return Builder.CreateCall(F, {Address, RW, Locality, IsData});
   }
 
   if (BuiltinID == AArch64::BI__builtin_arm_rbit) {
     assert((getContext().getTypeSize(E->getType()) == 32) &&
            "rbit of unusual size!");
     llvm::Value *Arg = EmitScalarExpr(E->getArg(0));
     return Builder.CreateCall(
-        CGM.getIntrinsic(Intrinsic::aarch64_rbit, Arg->getType()), Arg, "rbit");
+        CGM.getIntrinsic(Intrinsic::bitreverse, Arg->getType()), Arg, "rbit");
   }
   if (BuiltinID == AArch64::BI__builtin_arm_rbit64) {
     assert((getContext().getTypeSize(E->getType()) == 64) &&
            "rbit of unusual size!");
     llvm::Value *Arg = EmitScalarExpr(E->getArg(0));
     return Builder.CreateCall(
-        CGM.getIntrinsic(Intrinsic::aarch64_rbit, Arg->getType()), Arg, "rbit");
+        CGM.getIntrinsic(Intrinsic::bitreverse, Arg->getType()), Arg, "rbit");
   }
 
   if (BuiltinID == AArch64::BI__clear_cache) {
     assert(E->getNumArgs() == 2 && "__clear_cache takes 2 arguments");
     const FunctionDecl *FD = E->getDirectCallee();
     Value *Ops[2];
     for (unsigned i = 0; i < 2; i++)
       Ops[i] = EmitScalarExpr(E->getArg(i));

cfe/trunk/test/CodeGen/arm_acle.c

 // ARM-LABEL: test_revsh
 // ARM: call i16 @llvm.bswap.i16(i16 %t)
 int16_t test_revsh(int16_t t) {
   return __revsh(t);
 }
 
 // ARM-LABEL: test_rbit
 // AArch32: call i32 @llvm.arm.rbit
-// AArch64: call i32 @llvm.aarch64.rbit.i32
+// AArch64: call i32 @llvm.bitreverse.i32
 uint32_t test_rbit(uint32_t t) {
   return __rbit(t);
 }
 
 // ARM-LABEL: test_rbitl
 // AArch32: call i32 @llvm.arm.rbit
-// AArch64: call i64 @llvm.aarch64.rbit.i64
+// AArch64: call i64 @llvm.bitreverse.i64
 long test_rbitl(long t) {
   return __rbitl(t);
 }
 
 // ARM-LABEL: test_rbitll
 // AArch32: call i32 @llvm.arm.rbit
 // AArch32: call i32 @llvm.arm.rbit
-// AArch64: call i64 @llvm.aarch64.rbit.i64
+// AArch64: call i64 @llvm.bitreverse.i64
 uint64_t test_rbitll(uint64_t t) {
   return __rbitll(t);
 }
 
 /* 9.4 Saturating intrinsics */
 #ifdef __ARM_32BIT_STATE
 
 /* 9.4.1 Width-specified saturation intrinsics */

cfe/trunk/test/CodeGen/builtins-arm64.c

 // RUN: %clang_cc1 -triple arm64-unknown-linux -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
 
 void f0(void *a, void *b) {
   __clear_cache(a,b);
 // CHECK: call {{.*}} @__clear_cache
 }
 
 void *tp (void) {
   return __builtin_thread_pointer ();
 // CHECK: call {{.*}} @llvm.thread.pointer()
 }
 
-// CHECK: call {{.*}} @llvm.aarch64.rbit.i32(i32 %a)
+// CHECK: call {{.*}} @llvm.bitreverse.i32(i32 %a)
 unsigned rbit(unsigned a) {
   return __builtin_arm_rbit(a);
 }
 
-// CHECK: call {{.*}} @llvm.aarch64.rbit.i64(i64 %a)
+// CHECK: call {{.*}} @llvm.bitreverse.i64(i64 %a)
 unsigned long long rbit64(unsigned long long a) {
   return __builtin_arm_rbit64(a);
 }
 
 void hints() {
   __builtin_arm_nop();    //CHECK: call {{.*}} @llvm.aarch64.hint(i32 0)
   __builtin_arm_yield();  //CHECK: call {{.*}} @llvm.aarch64.hint(i32 1)
   __builtin_arm_wfe();    //CHECK: call {{.*}} @llvm.aarch64.hint(i32 2)