[ARM] Classification Improvements to ARM Sched-Models. NFCI.

[javed.absar]

Summary

This is a series of patches to enable adding of machine sched models for ARM processors easier and compact. They define new sched-readwrites for groups of ARM instructions. This has been missing so far, and as a consequence, machine scheduler models for individual sub-targets have tended to be larger than they needed to be. These patches should help write schedulers better and faster in the future for ARM sub-targets. The current patch focuses on floating-point instructions.

[javed.absar]

Hi Renato/James:
Gentle reminder on this review.
Thanks.

[rengolin]

Hi Javed,

There's a lot of repetition in this patch. Can't you group the similar latencies together?

Cheers,
Renato

[javed.absar]

Hi Renato:

Thanks. OK, I will collapse the schedwrites into one wherever sub-targets, which currently have sched-model in place, do not differentiate.

I tried not to club too many of the sched-defs into one bucket because then sub-targets wouldn't be able to specify different latencies/resources if there was indeed a difference in the pipeline behavior for different instruction classes (e.g. between MUL32 and MUL64).
Best Regards, Javed.

[rengolin]

In D28194#637818, @javed.absar wrote:

I tried not to club too many of the sched-defs into one bucket because then sub-targets wouldn't be able to specify different latencies/resources if there was indeed a difference in the pipeline behavior for different instruction classes (e.g. between MUL32 and MUL64).

I see where you're coming from, but I'd rather have that differentiation done by the sub-architectures when they need, than just explode the combinations now, and having to apply larger patches every time one sub-arch needs one cost changed. :)

--renato

[javed.absar]

Hi Renato:

Based on your feedback, I have removed sub-categories of of FPCVT and FPMOV. This removes the duplication you mentioned about for the sub-target. Please have a look and let me know if this is ok.
Thanks
Javed

[rengolin]

lib/Target/ARM/ARMScheduleSwift.td

307

useless whitespace change

610

don't comment out changes. If it's irrelevant, delete. If not, uncomment.

[javed.absar]

Hi Renato:
Thanks. I have removed the commented lines and unnecessary white-space, as you recommended.
Best Regards
Javed

[rovka]

Hi Javed,

The latest diff doesn't look right, could you re-upload it please? Also, it would be great if you could include more context.

Thanks,
Diana

[javed.absar]

Hi Diana:
Please find re-uploaded and with more context. Something went wrong with previous uploading. Apologies for that.

Thanks and Best Regards
Javed

[javed.absar]

Hi Diana:
Gentle reminder. Please let me know if you are ok with this patch.
best regards

[rovka]

Hi Javed,

Sorry about the delay, I was out of office for a few days. Comments below.

Cheers,
Diana

lib/Target/ARM/ARMInstrVFP.td

402 ↗

(On Diff #84091)

Why are half precision division and multiplication modeled the same as single precision, but half precision add/sub/sqrt aren't?

lib/Target/ARM/ARMSchedule.td

58 ↗

(On Diff #84091)

Typo: integer

lib/Target/ARM/ARMScheduleA9.td

1948 ↗

(On Diff #84091)

Why isn't this just a SchedAlias for A9WriteFDivS?

2554 ↗

(On Diff #84091)

Missed a spot.

[javed.absar]

Hi Diana:
I have fixed the issues you correctly pointed out. Thanks for that.
Best Regards
Javed

[javed.absar]

Removing the commented obsolete def. Missed it earlier.

[rovka]

LGTM, thanks.

lib/Target/ARM/ARMScheduleSwift.td

   def : InstRW <[SwiftDiv],
         (instregex "SDIV", "UDIV", "t2SDIV", "t2UDIV")>;
 
-
   // 4.2.19 Integer Load Single Element
   // 4.2.20 Integer Load Signextended
   def SwiftWriteP2P01ThreeCycle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP01]> {

 
   // 4.2.36 Advanced SIMD and VFP, Convert
   def : InstRW<[SwiftWriteP1FourCycle], (instregex "VCVT", "V(S|U)IT", "VTO(S|U)")>;
-  // Fixpoint conversions.
-  //def : WriteRes<WriteCvtFP, [SwiftUnitP1]> { let Latency = 4; }
 
   // 4.2.37 Advanced SIMD and VFP, Move
   def : InstRW<[SwiftWriteP0TwoCycle],