This is a series of patches to enable adding of machine sched models for ARM processors easier and compact. They define new sched-readwrites for groups of ARM instructions. This has been missing so far, and as a consequence, machine scheduler models for individual sub-targets have tended to be larger than they needed to be. These patches should help write schedulers better and faster in the future for ARM sub-targets. The current patch focuses on floating-point instructions.
Thanks. OK, I will collapse the schedwrites into one wherever sub-targets, which currently have sched-model in place, do not differentiate.
I tried not to club too many of the sched-defs into one bucket because then sub-targets wouldn't be able to specify different latencies/resources if there was indeed a difference in the pipeline behavior for different instruction classes (e.g. between MUL32 and MUL64).
Best Regards, Javed.
I see where you're coming from, but I'd rather have that differentiation done by the sub-architectures when they need, than just explode the combinations now, and having to apply larger patches every time one sub-arch needs one cost changed. :)
Based on your feedback, I have removed sub-categories of of FPCVT and FPMOV. This removes the duplication you mentioned about for the sub-target. Please have a look and let me know if this is ok.
Sorry about the delay, I was out of office for a few days. Comments below.
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Why are half precision division and multiplication modeled the same as single precision, but half precision add/sub/sqrt aren't?
|58 ↗||(On Diff #84091)|
|1948 ↗||(On Diff #84091)|
Why isn't this just a SchedAlias for A9WriteFDivS?
|2554 ↗||(On Diff #84091)|
Missed a spot.