[ARM] Add custom MachineInstr builder. NFC.

[rovka]

Summary

Add a subclass of MIBuilderBase for the ARM backend. This should allow us to get
rid of the AddDefaultPred, AddDefaultCC etc helpers and have a cleaner interface
instead.

This patch doesn't remove uses of the helpers, but it contains an example of how
to use the new builder in the ARM backend. A more thorough cleanup will follow
in other patches.

[MatzeB]

I wonder if the added complexity of a custom arm instruction builder is worth it. How about a solution that just provides functions to construct the operands but keeps using the default MachineInstrBuilder to add them:

MachineOperand CCRegOp(unsigned CCReg = 0) {
  return MachineOperand::CreateReg(CCReg, false);
}

// Use:
BuildMI(). ... .addOperand(CCRegOp())

• We could rename MachineInstrBuilder::addOperand() to add() to make this a bit shorter.

For the predicate condition code + register pair you could either provide two functions or maybe extend MachineInstrBuilder to accept pairs of operands:

class MachineInstrBuilder {
  // ...
  add(std::pair<MachineOperand, MachineOperand> Operands) {
    add(Operands.first);
    add(Operands.second);
  }
};
// ...
std::pair<MachineOperand, MachineOperand> predOps(ARMCC::CondCodes Pred = ARMCC::AL,
                                 unsigned PredReg = 0) const {
  return std::make_pair(
    MachineOperand::CreateImm(static_cast<int64_t>(Pred))),
    MachineOperand::CreateReg(PredReg, false)
  );
}
// ...
// Use
BuildMI(). ... .add(predOps(Pred))

[rovka]

Abandoning this in favor of https://reviews.llvm.org/D28557 & co.

lib/Target/ARM/ARMBaseInstrInfo.h

bool canCauseFpMLxStall(unsigned Opcode) const {
     return MLxHazardOpcodes.count(Opcode);
   }
 
   /// Returns true if the instruction has a shift by immediate that can be
   /// executed in one cycle less.
   bool isSwiftFastImmShift(const MachineInstr *MI) const;
 };
 
+// FIXME: Remove these when all uses are gone
 static inline
 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
   return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
 }
 
 static inline
 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
   return MIB.addReg(0);

lib/Target/ARM/ARMBaseInstrInfo.cpp

 //===----------------------------------------------------------------------===//
 
 #include "ARM.h"
 #include "ARMBaseInstrInfo.h"
 #include "ARMBaseRegisterInfo.h"
 #include "ARMConstantPoolValue.h"
 #include "ARMFeatures.h"
 #include "ARMHazardRecognizer.h"
+#include "ARMInstrBuilder.h"
 #include "ARMMachineFunctionInfo.h"
 #include "MCTargetDesc/ARMAddressingModes.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/CodeGen/LiveVariables.h"
 #include "llvm/CodeGen/MachineConstantPool.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineJumpTableInfo.h"
 #include "llvm/CodeGen/MachineMemOperand.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/SelectionDAGNodes.h"
 #include "llvm/CodeGen/TargetSchedule.h"
 #include "llvm/IR/Constants.h"
 #include "llvm/IR/Function.h"
 #include "llvm/IR/GlobalValue.h"
MachineInstr *ARMBaseInstrInfo::convertToThreeAddress(
   case ARMII::AddrMode2: {
     bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
     unsigned Amt = ARM_AM::getAM2Offset(OffImm);
     if (OffReg == 0) {
       if (ARM_AM::getSOImmVal(Amt) == -1)
         // Can't encode it in a so_imm operand. This transformation will
         // add more than 1 instruction. Abandon!
         return nullptr;
-      UpdateMI = BuildMI(MF, MI.getDebugLoc(),
+      UpdateMI =
+          BuildMI<ARMInstrBuilder>(MF, MI.getDebugLoc(),
                                    get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
-                     .addReg(BaseReg)
-                     .addImm(Amt)
-                     .addImm(Pred)
-                     .addReg(0)
-                     .addReg(0);
+              .addPred(Pred)
+              .addCC();
     } else if (Amt != 0) {
       ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
       unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
       UpdateMI = BuildMI(MF, MI.getDebugLoc(),
                          get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
                      .addReg(BaseReg)
                      .addReg(OffReg)
                      .addReg(0)

lib/Target/ARM/ARMInstrBuilder.h

+//===-- ARMInstrBuilder.h - Simplify creation of ARM insts ------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains a special instruction builder for ARM, which provides
+// functionality for handling special ARM operands such as predicates and CC.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_ARM_ARMINSTRBUILDER_H
+#define LLVM_LIB_TARGET_ARM_ARMINSTRBUILDER_H
+
+#include "MCTargetDesc/ARMBaseInfo.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+
+namespace llvm {
+
+class ARMInstrBuilder : public MIBuilderBase<ARMInstrBuilder> {
+public:
+  using MIBuilderBase<ARMInstrBuilder>::MIBuilderBase;
+
+  const ARMInstrBuilder &addPred(ARMCC::CondCodes Pred = ARMCC::AL,
+                                 unsigned PredReg = 0) const {
+    return addImm(static_cast<int64_t>(Pred)).addReg(PredReg);
+  }
+
+  const ARMInstrBuilder &addCC(unsigned CCReg = 0) const {
+    return addReg(CCReg);
+  }
+};
+} // End llvm namespace
+
+#endif