AMD family 17h (znver1) enablement

[GGanesh]

Summary

This patch enables the following

1. AMD family 17h architecture using "znver1" tune flag (-march, -mcpu).
2. ISAs that are enabled for "znver1" architecture.
3. Checks ADX isa from cpuid to identify "znver1" flag when -march=native is used.
4. Enables CLZERO feature and adds the builtin macro __builtin_ia32_clzero for clzero instruction.
5. ISAs FMA4, XOP are disabled as they are dropped from amdfam17.
6. For the time being, it uses the btver2 scheduler model.
7. Test file is updated to check this flag.

This is linked to llvm review item https://reviews.llvm.org/D28017

[RKSimon]

lib/Basic/Targets.cpp

3191

Don't need to specify avx as you have avx2

3211

SSE4A?

[RKSimon]

Also, I don't think there is any clzero support on clang yet so adding that feature probably isn't safe. You may need to put up a separate clzero patch for review, preferably including _mm_clzero support to the headers as well.

[GGanesh]

The clzero builtins and feature addition will be handled separately in another patch.
SSE4a and movbe are added to the ISA list.

[RKSimon]

lib/Basic/Targets.cpp

3189

Same as what I asked on D28017 - is there an accepted order that we should be using here?

[GGanesh]

lib/Basic/Targets.cpp

3189

Some of them seems to be chronological.
Some of them are alphabetical.

I personally don't have any preference as such.
Alphabetical order suits a long list.
I would like to know your suggestion.

[RKSimon]

lib/Basic/Targets.cpp

3189

@craig.topper Any preferences?

No strong preference and nothing that should slow the acceptance of this patch - alphabetical can be easier to maintain but it's unlikely this code changes often.

Sorting by feature groups/age can be more understandable, and can help account for the fall-through behaviour used in many of the cases here - speaking of which would it be useful to fall-through from CK_ZNVER1 to CK_BTVER2 to CK_BTVER1 since they seem to have a common set of features?

[GGanesh]

Fallback to CK_BTVER1 is ok but not to CK_BTVER2. This is not possible because of the partial YMM writes. They have different behavior for znver1 with AVX and their legacy SIMD counterparts. So, as of now leaving them to alphabetical order.

[RKSimon]

In D28018#639765, @GGanesh wrote:

Fallback to CK_BTVER1 is ok but not to CK_BTVER2. This is not possible because of the partial YMM writes. They have different behavior for znver1 with AVX and their legacy SIMD counterparts. So, as of now leaving them to alphabetical order.

That makes sense for the llvm patch, but for this clang patch in X86TargetInfo::initFeatureMap we don't need to handle those behaviour features just the instruction set features which we can fall though.

[GGanesh]

Yes. True I mentioned that for the grouping or the order of the features enabled. These initFeatureMap are done based on the intrinsics and the CodeGen part.

[GGanesh]

If Okay, can you please commit these on my behalf. I don't have write access.

[RKSimon]

LGTM - @craig.topper any additional comments?

[craig.topper]

LGTM

lib/Basic/Targets.cpp

enum CPUKind {
     /// Bulldozer architecture processors.
     //@{
     CK_BDVER1,
     CK_BDVER2,
     CK_BDVER3,
     CK_BDVER4,
     //@}
 
+    /// \name zen
+    /// Zen architecture processors.
+    //@{
+    CK_ZNVER1,
+    //@}
+
     /// This specification is deprecated and will be removed in the future.
     /// Users should prefer \see CK_K8.
     // FIXME: Warn on this when the CPU is set to it.
     //@{
     CK_x86_64,
     //@}
 
     /// \name Geode
return llvm::StringSwitch<CPUKind>(CPU)
         .Case("barcelona", CK_AMDFAM10)
         .Case("amdfam10", CK_AMDFAM10)
         .Case("btver1", CK_BTVER1)
         .Case("btver2", CK_BTVER2)
         .Case("bdver1", CK_BDVER1)
         .Case("bdver2", CK_BDVER2)
         .Case("bdver3", CK_BDVER3)
         .Case("bdver4", CK_BDVER4)
+        .Case("znver1", CK_ZNVER1)
         .Case("x86-64", CK_x86_64)
         .Case("geode", CK_Geode)
         .Default(CK_Generic);
   }
 
   enum FPMathKind {
     FP_Default,
     FP_SSE,
bool setCPU(const std::string &Name) override {
     case CK_OpteronSSE3:
     case CK_AMDFAM10:
     case CK_BTVER1:
     case CK_BTVER2:
     case CK_BDVER1:
     case CK_BDVER2:
     case CK_BDVER3:
     case CK_BDVER4:
+    case CK_ZNVER1:
     case CK_x86_64:
       return true;
     }
     llvm_unreachable("Unhandled CPU kind");
   }
 
   bool setFPMath(StringRef Name) override;
 
case CK_BTVER1:
     setFeatureEnabledImpl(Features, "ssse3", true);
     setFeatureEnabledImpl(Features, "sse4a", true);
     setFeatureEnabledImpl(Features, "lzcnt", true);
     setFeatureEnabledImpl(Features, "popcnt", true);
     setFeatureEnabledImpl(Features, "prfchw", true);
     setFeatureEnabledImpl(Features, "cx16", true);
     setFeatureEnabledImpl(Features, "fxsr", true);
     break;
+  case CK_ZNVER1:
+    setFeatureEnabledImpl(Features, "adx", true);
+    setFeatureEnabledImpl(Features, "aes", true);
+    setFeatureEnabledImpl(Features, "avx2", true);
+    setFeatureEnabledImpl(Features, "bmi", true);
+    setFeatureEnabledImpl(Features, "bmi2", true);
+    setFeatureEnabledImpl(Features, "clflushopt", true);
+    setFeatureEnabledImpl(Features, "cx16", true);
+    setFeatureEnabledImpl(Features, "f16c", true);
+    setFeatureEnabledImpl(Features, "fma", true);
+    setFeatureEnabledImpl(Features, "fsgsbase", true);
+    setFeatureEnabledImpl(Features, "fxsr", true);
+    setFeatureEnabledImpl(Features, "lzcnt", true);
+    setFeatureEnabledImpl(Features, "mwaitx", true);
+    setFeatureEnabledImpl(Features, "movbe", true);
+    setFeatureEnabledImpl(Features, "pclmul", true);
+    setFeatureEnabledImpl(Features, "popcnt", true);
+    setFeatureEnabledImpl(Features, "prfchw", true);
+    setFeatureEnabledImpl(Features, "rdrnd", true);
+    setFeatureEnabledImpl(Features, "rdseed", true);
+    setFeatureEnabledImpl(Features, "sha", true);
+    setFeatureEnabledImpl(Features, "sse4a", true);
+    setFeatureEnabledImpl(Features, "xsave", true);
+    setFeatureEnabledImpl(Features, "xsavec", true);
+    setFeatureEnabledImpl(Features, "xsaveopt", true);
+    setFeatureEnabledImpl(Features, "xsaves", true);
+    break;
   case CK_BDVER4:
     setFeatureEnabledImpl(Features, "avx2", true);
     setFeatureEnabledImpl(Features, "bmi2", true);
     setFeatureEnabledImpl(Features, "mwaitx", true);
     // FALLTHROUGH
   case CK_BDVER3:
     setFeatureEnabledImpl(Features, "fsgsbase", true);
     setFeatureEnabledImpl(Features, "xsaveopt", true);
case CK_BDVER2:
     defineCPUMacros(Builder, "bdver2");
     break;
   case CK_BDVER3:
     defineCPUMacros(Builder, "bdver3");
     break;
   case CK_BDVER4:
     defineCPUMacros(Builder, "bdver4");
     break;
+  case CK_ZNVER1:
+    defineCPUMacros(Builder, "znver1");
+    break;
   case CK_Geode:
     defineCPUMacros(Builder, "geode");
     break;
   }
 
   // Target properties.
   Builder.defineMacro("__REGISTER_PREFIX__", "");