This patch enables the following
- AMD family 17h architecture using "znver1" tune flag (-march, -mcpu).
- ISAs that are enabled for "znver1" architecture.
- Checks ADX isa from cpuid to identify "znver1" flag when -march=native is used.
- Enables CLZERO feature and adds the builtin macro __builtin_ia32_clzero for clzero instruction.
- ISAs FMA4, XOP are disabled as they are dropped from amdfam17.
- For the time being, it uses the btver2 scheduler model.
- Test file is updated to check this flag.
This item is linked to clang review item https://reviews.llvm.org/D28018